FUJITSU MB90F244PFT-G

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13510-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90F244
MB90F244
■ DESCRIPTION
The MB90F244 is a 16-bit microcontroller optimized for applications in mechatronics such as HDD units. The
architecture of the MB90F244 is based on the MB90242A, and embedded with a 128-Kbyte flash memory.
The instruction set is based on the AT architecture of the F2MC* family, with additional high-level language
supporting instruction, expanded addressing modes, enhanced multiplication and division instructions, and
improved bit processing instructions. In addition, long-word data can now be processed due to the inclusion of
a 32-bit accumulator.
The MB90F244 includes a variety of peripherals on chip, such as the device is equipped with 8-channel
8/10-bit A/D converter, UART, 3-channel 16-bit reload timers, 1-channel 16-bit timer, 4-channel 16-bit input
capture and 4-channel DTP/external interrupts.
Differences between the MB90F244 and MB90F243 to meet the 3.3 V ±0.3 V power supply voltage are that the
power consumption of the MB90F244 is about 10% less than that of the MB90F243 and the operating frequency
of the MB90F244 is up to 50 MHz from 32 MHz of the MB90F243.
* : F2MC stands for FUJITSU Flexible Microcontroller.
■ PACKAGE
80-pin Plastic TQFP
(FPT-80P-M15)
MB90F244
■ FEATURES
• Minimum execution time (target): 40.0 ns at 50 MHz oscillation (3.3 V ±0.3 V)
• Instruction set optimized for controller applications
Variety of data types: bit, byte, word, long-word
Expanded addressing modes: 25 types
High coding efficiency
Improvement of high-precision arithmetic operations through use of 32-bit accumulator
Enhanced multiplication and division instructions (signed arithmetic operations)
• Instruction set supports high-level language (C language) and multitasking
Inclusion of system stack pointer
Variety of pointers
High instruction set symmetry
Barrel shift instruction
Stack check function
• Improved execution speed: 8-byte queue
• Powerful interrupt functions
Interrupt processing time: 0.64 µs at 50 MHz oscillation
Priority levels: 8 levels (programmable)
External interrupt inputs: 4 channels
• Automatic transfer function independent of CPU
Extended intelligent I/O service: Max.15 channels
• 128-Kbyte flash memory
Access time (min.) : 80 ns
Sector structure of 16K + 512 × 2 + 7K + 8K + 32K + 64K
Program/erase operations from both EPROM programmer and CPU through built-in flash memory interface
circuit
Built-in programming booster circuit for flash memory
• Internal RAM: 1.152 kbyte
According to mode settings, data stored on RAM can be executed as CPU instructions.
• General-purpose ports: Max. 63 channels (single-chip mode)
Max. 38 channels (external bus mode)
• 18-bit timebase timer
• Watchdog timer
• UART: 8 bits × 1 channel
• 8/16-bit I/O simple serial interface (max. 12.5 Mbps): 1 channel
• 8/10-bit A/D converter: Analog inputs: 8 channels
Resolution: 10 bits (switchable to 8 bits/10 bits)
Conversion time: Min. 1 µs
Conversion result store register: 4 channels
• 16-bit I/O timer
16-bit free-run timer: 1 channel (operating clock: 0.16 µs)
16-bit input capture: 4 channels
• 16-bit reload timer: 3 channels
• Low-power consumption modes
Sleep mode
Stop mode
Hardware standby mode
• Packages: TQFP-80 (FPT-80P-M15)
(For more information about the package, see section “■ Package Dimensions.”)
(Continued)
2
MB90F244
(Continued)
• PLL clock multiple function
• CMOS technology
• Power supply voltage: 3.3 V ±0.3 V or 5.0 V ±0.5 V
(Varies with conditions such as the operating frequency. See section
“■ Electrical Characteristics.”)
3
P20/A00/AQ0
P21/A01/AQ1
P22/A02/AQ2
P23/A03/AQ3
P24/A04/AQ4
P25/A05/AQ5
P26/A06/AQ6
P27/A07/AQ7
VSS
P30/A08/AQ8
P31/A09/AQ9
P32/A10/AQ10
P33/A11/AQ11
P34/A12/AQ12
P35/A13/AQ13
P36/A14/AQ14
P37/A15/AQ15
P40/A16/AQ16
P41/A17/AQ17
P42/A18/SID0/AQ18
RST
P57/ASR3/INT3/BYTE
P56/RD/CE
P55/WRL/WR/OE
P54/WRH/WE
P53/HRQ
P52/HAK
P51/RDY
CLK/RY/BY
P82/INT2/ATG
P81/INT1
P80/INT0
P75/SOD1
P74/SID1
P73/SCK1
P72/TOT2
P71/TOT1
P70/TOT0/AN4
HST
MD2
MB90F244
■ PIN ASSIGNMENT
(Top view)
VSS
X0
X1
VCC 5
P00/D00/DQ0
P01/D01/DQ1
P02/D02/DQ2
P03/D03/DQ3
P04/D04/DQ4
P05/D05/DQ5
P06/D06/DQ6
P07/D07/DQ7
P10/D08/DQ8
P11/D09/DQ9
P12/D10/DQ10
P13/D11/DQ11
P14/D12/DQ12
P15/D13/DQ13
P16/D14/DQ14
P17/D15/DQ15
4
MD1
MD0
VCC
P65/AN5
P67/AN7
P66/AN6
P63/AN3
P62/AN2
VSS
P61/AN1
P60/AN0
AVSS
AVRL
AVRH
AVCC
P47/A23/ASR2/TIN2
P46/A22/ASR1/TIN1
P45/A21/ASR0/TIN0
P44/A20/SCK0
P43/A19/SOD0
(FPT-80P-M15)
MB90F244
■ PIN DESCRIPTION
Pin no.
Pin name
TQFP-80*
62
X0
63
X1
Circuit
type
Function
A
Crystal oscillator pins (50 MHz)
MD0 to MD2
C
Operating mode selection input pins
Connect directly to VCC5 or VSS. In the flash memory mode,
these pins are set to be VID (= 12.0 V) input pins by performing
a proper operation.
60
RST
B
External reset request input pin
42
HST
D
Hardware standby input pin
P00 to P07
E
General-purpose I/O port
39 to 41
65 to 72
73 to 80
1 to 8
10 to 17
18
*: FPT-80P-M15
D00 to D07
I/O pins for the lower 8 bits of the external data bus
DQ0 to DQ7
Data I/O pins for each operation command
This function is valid in the flash memory mode.
P10 to P17
E
General-purpose I/O port
This function is valid when the external bus 8-bit mode.
D08 to D15
I/O pins for the upper 8 bits of the external data bus
This function is valid when 16-bit bus mode.
DQ8 to DQ15
Data I/O pins for each operation command
This function is valid in the flash memory mode.
P20 to P27
F
General-purpose I/O port
A00 to A07
Output pins for the medium 8 bits of the external address bus
AQ0 to AQ7
Address input pins for each operation command
This function is valid in the flash memory mode.
P30 to P37
F
General-purpose I/O port
This function is valid when the corresponding bit of the middle
address control register specification is “port”.
A08 to A15
Output pins for the medium 8 bits of the external address bus
This function is valid when the corresponding bit of the middle
address control register specification is “port”.
AQ8 to AQ15
Address input pins for each operation command
This function is valid in the flash memory mode.
P40
F
General-purpose I/O port
This function is valid when the corresponding bit of the upper
address control register specification is “port”.
A16
External address bus output pin of the bit 16
This function is valid when the corresponding bit of the upper
address control register specification is “address”.
AQ16
Address input pin for each operation command
This function is valid in the flash memory mode.
(Continued)
5
MB90F244
Pin no.
TQFP-80*
19
20
21
22
*: FPT-80P-M15
6
Pin name
P41
Circuit
type
F
Function
General-purpose I/O port
This function is valid when the upper address control register
specification is “port”.
A17
External address bus output pin of the bit 17
This function is valid when the corresponding bit of the upper
address control register specification is “address”.
AQ17
Address input pin for each operation command
This function is valid in the flash memory mode.
P42
F
General-purpose I/O port
This function is valid when the corresponding bit of the upper
address control register specification is “port”.
A18
External address bus output pin of the bit 18
This function is valid when the corresponding bit of the upper
address control register specification is “address”.
SID0
UART #0 data input pin
During UART #0 input operations, these inputs may be used at
any time; therefore, it is necessary to stop output by other
functions on this pin, except when using them for output
deliberately.
AQ18
Address input pin for each operation command
This function is valid in the flash memory mode.
P43
G
General-purpose I/O port
This function is valid when the UART #0 data output is disabled
and the corresponding bit of the upper address control register
specification is “port”.
A19
External address bus output pin of the bit 19
This function is valid when the UART #0 data output is disabled
and the corresponding bit of the upper address control register
specification is “address”.
SOD0
UART #0 data output pin
This function is valid when the UART #0 data output is enabled.
P44
G
General-purpose I/O port
This function is valid when the UART #0 clock output is
disabled and the corresponding bit of the upper address control
register specification is “port”.
A20
External address bus output pin of the bit 20
This function is valid when the UART #0 clock output is
disabled and the corresponding bit of the upper address control
register specification is “address”.
SCK0
UART #0 clock I/O pin
(Continued)
MB90F244
Pin no.
TQFP-80*
23
24
25
*: FPT-80P-M15
Pin name
P45
Circuit
type
G
Function
General-purpose I/O port
This function is valid when the corresponding bit of the upper
address control register specification is “port”.
A21
External address bus output pin of the bit 21
This function is valid when the corresponding bit of the upper
address control register specification is “address”.
ASR0
16-bit input capture #0 data input pin
During 16-bit input capture #0 input operations, these inputs
may be used at any time; therefore, it is necessary to stop
output by other functions on this pin, except when using them
for output deliberately.
TIN0
16-bit timer #0 data input pin
During 16-bit timer #0 input operations, these inputs may be
used at any time; therefore, it is necessary to stop output by
other functions on this pin, except when using them for output
deliberately.
P46
G
General-purpose I/O port
This function is valid when the corresponding bit of the upper
address control register specification is “port”.
A22
External address bus output pin of the bit 22
This function is valid when the corresponding bit of the upper
address control register specification is “address”.
ASR1
16-bit input capture #1 data input pin
During 16-bit input capture #1 input operations, these inputs
may be used at any time; therefore, it is necessary to stop
output by other functions on this pin, except when using them
for output deliberately.
TIN1
16-bit timer #1 data input pin
During 16-bit timer #1 input operations, these inputs may be
used at any time; therefore, it is necessary to stop output by
other functions on this pin, except when using them for output
deliberately.
P47
G
General-purpose I/O port
This function is valid when the corresponding bit of the upper
address control register specification is “port”.
A23
External address bus output pin for the bit 23
This function is valid when the corresponding bit of the upper
address control register specification is “address”.
ASR2
16-bit input capture #2 data input pin
During 16-bit input capture #2 input operations, these inputs
may be used at any time; therefore, it is necessary to stop
output by other functions on this pin, except when using them
for output deliberately.
TIN2
16-bit timer #2 data input pin
During 16-bit timer #2 input operations, these inputs may be
used at any time; therefore, it is necessary to stop output by
other functions on this pin, except when using them for output
deliberately.
(Continued)
7
MB90F244
Pin no.
Pin name
TQFP-80*
53
P51
Circuit
type
H
RDY
54
P52
P53
H
57
58
59
*: FPT-80P-M15
8
P54
General-purpose I/O port
This function is valid when the hold function is disabled.
Hold acknowledge output pin
This function is valid when the hold function is enabled.
H
HRQ
56
General-purpose I/O port
This function is valid when the ready function is disabled.
Ready input pin
This function is valid when the ready function is enabled.
HAK
55
Function
General-purpose I/O port
This function is valid when the hold function is disabled.
Hold request input pin
This function is valid and when the hold function is enabled.
F
General-purpose I/O port
This function is valid in external bus 8-bit mode, or when WRH
pin output is disabled.
WRH
Write strobe output pin for the upper 8 bits of the data bus
This function is valid in modes where the external bus
16-bit mode is enabled, and WRH pin output is enabled.
WE
Write enable input pin
This function is valid in the flash memory mode.
P55
F
General-purpose I/O port
This function is valid when WRL pin output is disabled.
WRL / WR
Write strobe output pin for the lower 8 bits of the data bus
This function is valid WRL pin output is enabled.
OE
Output enable input pin for each operation command
This function is valid in the flash memory mode.
P56
F
General-purpose I/O port
RD
Read strobe output pin for the data bus
CE
Chip enable input pin for each operation command
This function is valid in the flash memory mode.
P57
F
General-purpose I/O port
ASR3
16-bit input capture #3 data input pin
During 16-bit input capture #3 input operations, these inputs
may be used at any time; therefore, it is necessary to stop
output by other functions on this pin, except when using them
for output deliberately.
INT3
DTP/external interrupt #3 data input pin
During DTP/external interrupt #3 input operations, these inputs
may be used at any time; therefore, it is necessary to stop
output by other functions on this pin, except when using them
for output deliberately.
BYTE
Byte access control input pin
This function is valid in the flash memory mode.
(Continued)
MB90F244
Pin no.
TQFP-80*
30,
31,
33,
34,
35,
36,
37
Pin name
P60,
P61,
P62,
P63,
P66,
P67,
P65
Circuit
type
Function
I
N-ch open-drain type I/O ports
When bits corresponding to the ADER are set to “0”, reading
instructions other than the read-modify-write group returns the
pin level. The value written on the data register is output to this
pin directly.
AN0,
AN1,
AN2,
AN3,
AN6,
AN7,
AN5
43
44,
45
P70
8/10-bit A/D converter analog input pins
Use this function after setting bits corresponding to the ADER to
“1” and setting corresponding bits of the data register to “1”.
J
TOT0
16-bit timer output pin
This function is valid when the bit corresponded to ADER is set
to “0” and also the output of 16-bit timer #0 is enabled.
AN4
8/10-bit AD converter analog input pin
This function can be used when the bit corresponded to ADER
is set to “1” and also the bit correponded to the data resister is
set to “1”.
P70,
P72
G
TOT1,
TOT2
46
P73
P74
G
P75
SOD1
*: FPT-80P-M15
General-purpose I/O port
This function is valid when the SSI #1 clock output is disabled.
SSI #1 clock output I/O pin
G
SID1
48
General-purpose I/O port
This function is valid when the reload timer #1, and #2 output is
disabled.
16-bit timer output pins
This function is valid when the 16-bit timer #1, and #2 output is
enabled.
SCK1
47
General-purpose I/O port
This function is valid when the bit corresponded to ADER is set
to “0” and also the output of 16-bit timer #0 is disabled.
General-purpose I/O port
This function is always valid.
SSI #1 data input pin
During SSI #1 input operations, these inputs may be used at
any time; therefore, it is necessary to stop output by other
functions on this pin, except when using them for output
deliberately.
G
General-purpose I/O port
This function is valid when the SSI #1 data output is disabled.
SSI #1 data output pin
This function is valid when the SSI #1 data output is disabled.
(Continued)
9
MB90F244
(Continued)
Pin no.
TQFP-80*
49,
50
Pin name
P80,
P81
Circuit
type
G
INT0,
INT1
51
52
P82
General-purpose I/O port
This function is always valid.
DTP/external interrupt input pin
When external interrupts are enabled, these inputs may be
used at any time; therefore, it is necessary to stop output by
other functions on this pin, except when using them for output
deliberately.
G
General-purpose I/O port
This function is always valid.
INT2
DTP/external interrupt input pin
When external interrupts are enabled, these inputs may be
used at any time; therefore, it is necessary to stop output by
other functions on this pin, except when using them for output
deliberately.
Because an input to this pin is clamped to Low when the CPU
stops, use INT0 or INT1 to wake up the system from the stop
mode.
ATG
8/10-bit A/D converter trigger input pin
When 8/10-bit A/D converter is waiting for activation, this input
may be used at any time; therefore, it is necessary to stop
output by other functions on this pin, except when using it for
output deliberately.
CLK
G
RY/BY
CLK output pin
Open-drain pin output ready/busy signal in the program deleting
operation
This function is valid in the flash memory mode.
38
VCC
Power
supply
Digital circuit power supply pin
64
VCC5
Power
supply
Power supply voltage (5.0 V) input pin for flash memory
9,
32,
61
VSS
Power
supply
Digital circuit power supply (GND) pin
26
AVCC
Power
supply
Analog circuit power supply pin
This power supply must only be turned on or off when electric
potential of AVCC or greater is applied to VCC.
27
AVRH
Power
supply
8/10-bit A/D converter external reference voltage input pin
This pin must only be turned on or off when electric potential of
AVRH or greater is applied to AVCC.
28
AVRL
Power
supply
8/10-bit A/D converter external reference voltage input pin
29
AVSS
Power
supply
Analog circuit power supply (GND) pin
*: FPT-80P-M15
10
Function
MB90F244
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Clock halt
• 50 MHz
• Oscillation feedback resistor:
Approximately 1 MΩ
X0
Clock input
X1
R
B
• CMOS-level hysteresis input
(without standby control)
• Pull-up resistor: Approximately 50 kΩ
R
P-ch Tr
N-ch Tr
Diffusion resistor
Digital input
CMOS
C
• CMOS-level input
• High voltage control for flash memory
testing
Control signal
Mode input
Diffusion resistor
D
• CMOS-level hysteresis input
(without standby control)
P-ch Tr
N-ch Tr
Diffusion resistor
Digital input
CMOS
(Continued)
11
MB90F244
(Continued)
Type
Circuit
Remarks
E
Digital output
Digital output
Diffusion resistor
Flash memory
mode
Standby control
signal
TTL
Flash memory
input
Digital input
TTL
F
Digital output
Digital output
Diffusion resistor
Flash memory
mode
TTL
Standby control
signal
CMOS
Digital input
Digital output
• CMOS-level output
• CMOS-level hysteresis input
(with standby control)
Digital output
Diffusion resistor
Digital input
CMOS
H
Digital output
Diffused resistor
Standby control
signal
• CMOS-level output
• CMOS-level hysteresis input
• TTL-level input (flash memory mode)
(with standby control)
Flash memory
input
G
Standby control
signal
• CMOS-level output
• TTL-level input
(with standby control)
• CMOS-level output
• TTL-level input
(with standby control)
Digital output
Digital input
TTL
(Continued)
12
MB90F244
(Continued)
Type
Circuit
Remarks
I
Digital output
• N-ch open-drain CMOS-level output
• CMOS-level hysteresis input
(analog input)
(with analog input control)
Diffusion resistor
Analog input
Analog input
control
Digital input
CMOS
J
Digital output
Digital output
Diffusion resistor
Analog input
control
• N-ch open-drain CMOS-level output
• CMOS-level hysteresis input
(analog input)
(with analog input control)
Analog input
Digital input
CMOS
13
MB90F244
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to the input or output
pins other than medium-and high-voltage pins or if higher than the voltage which shown on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics”is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly might thermally damage elements. When using,
take great care not to exceed the absolute maximum ratings.
In addition, for the same reasons take care to prevent the analog power supply from exceeding the digital power
supply.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistors.
3. Precautions when Using an External Clock
When an external clock is used, drive X0 only.
• For example an external clock
X0
X1
4. Power Supply Pins
When there are several VCC and VSS pins, those pins that should have the same electric potential are connected
within the device when the device is designed in order to prevent misoperation, such as latch-up. However, all
of those pins must be connected to the power supply and ground externally in order to reduce unnecessary
emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the
total output current standards.
In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with
the lowest possible impedance.
Finally, it is recommended to connect a capacitor of about 0.1 µF between VCC and VSS near this device as a
bypass capacitor.
14
MB90F244
5. Crystal Oscillation Circuit
Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit
board so that the bypass capacitor connecting X0 and X1 pins and the crystal oscillator (or ceramic oscillator)
to ground is located as close to the device as possible.
In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded
by ground provides stable operation, such an arrangement is strongly recommended.
6. Sequence for Applying the A/D Converter Power Supply and the Analog Inputs
Always be sure to apply the digital power supply (VCC) before applying the A/D converter power supply (AVCC,
AVRH, and AVRL) and the analog inputs (AN0 to AN7).
In addition, when the power is turned off, turn off the A/D converter power supply and the analog inputs first,
and then turn off the digital power supply. (Turning on or off the analog and digital power supplies simultaneously
will not cause any problems.)
Whether applying or cutting off the power, be certain that AVRH does not exceed AVCC.
7. External Reset Input
To reliably reset the controller by inputting an “L” level to the RST pin, ensure that the “L” level is applied for at
least five machine cycles.
8. HST Pin
When turning on the system, be sure to set the HST pin to “H” level. Never set the HST pin to “L” level while the
RST pin is in “L” level.
9. CLK Pin
STOP
X1
To internal blocks
ex. 50 MHz
X0
Divide by 2 circuit
CLK
STOP
Note: CLK pin cannot use as I/O port.
Care must be taken that this is different from standard specification for F2MC-16F family.
15
MB90F244
10.Specifed Interrupt Sequence
When the interrupt stack area is allocated to the external memory, even if the higher priority level interrupt may
generate while the former interrupt is waiting in the stack area, the latter higher priority level interrupt routine
has to wait untill the former interrupt routine is excuted. In this case the former interrupt routine is excuted in the
latter higher priority level.
Normal interrupt sequence
Interrupt level
(ILM = 0)
Interrupt level
(ILM = 1)
Interrupt level
(ILM = 7)
B
C
B
C
A
B interrupt generation
C interrupt generation
A: Main routine operation (ILM = 7)
B: Priority 0 interrupt routine (ILM = 0)
C: Priority 1 interrupt routine (ILM = 1)
16
Specified interrupt sequence
A
A
B interrupt generation
A
C interrupt generation
Program operation
Program transition
(Resister stack)
MB90F244
■ BLOCK DIAGRAM
SCK0
SID0
SOD0
UART
SCK1
SID1
SOD1
8/16-bit I/O simple
serial interface
16-bit timer
ASR0 to ASR3
TIN0/TOT0 to
TIN2/TOT2
8/10-bit
A/D converter
16-bit reload timer
I/O port × 63
Internal data bus
AVCC
AVRH
AVRL
AVSS
AN0 to AN7
ATG
16-bit input
capture (ICU)
× 4 channels
External bus interface
F2MC-16F CPU
RAM
INT0 to INT3
X0
X1
RST
HST
MD0 to MD2
DTP/external
Interrupt
× 4 channels
Flash memory interface
Flash memory
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P51 to P57
P60 to P63
P65 to P67
P70 to P75
P80 to P82
D00 to D15
A00 to A23
CLK
RDY
HAK
HRQ
WRH
WRL/WR
RD
DQ0 to DQ15
AQ0 to AQ18
WE
OE
CE
BYTE
RY/BY
VCC 5
Clock controller
PLL
Other pins
VCC, VSS
17
MB90F244
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated registers
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
USPCU
User stack upper limit register
SSPCU
System stack upper limit register
USPCL
User stack lower limit register
SSPCL
System stack lower limit register
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bits
16 bits
32 bits
• General-purpose registers
Max. 32 banks
R7
R6
R5
R4
R3
R2
R1
R0
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180H + (RP × 10 H )
16 bits
• Processor status (PS)
ILM
RP
—
I
S
T
N
CCR
18
Z
V
C
MB90F244
■ MEMORY MAP
Single-chip mode
Internal ROM/
external bus mode
External ROM/
external bus mode
FFFFFF H
Flash memory
ROM
Flash memory
ROM
FE0 0 0 0 H
: access
inhibited
0 0 0 5 7F H
RAM
RAM
RAM
000100H
0 0 0 0C0 H
000020H
: Internal access
memory
: Exernal access
memory
Peripheral
Peripheral
Peripheral
I/O
I/O
I/O
000000H
19
MB90F244
■ I/O MAP
Address
Register
name
Read/
write
Resource
name
Initial value
000000H
PDR0
Port 0 data register
R/W
Port 0
XXXXXXXX B
000001H
PDR1
Port 1 data register
R/W
Port 1
XXXXXXXX B
000002H
PDR2
Port 2 data register
R/W
Port 2
XXXXXXXX B
000003H
PDR3
Port 3 data register
R/W
Port 3
XXXXXXXX B
000004H
PDR4
Port 4 data register
R/W
Port 4
XXXXXXXX B
000005H
PDR5
Port 5 data register
R/W
Port 5
XXXXXXX– B
000006H
PDR6
Port 6 data register
R/W
Port 6
111–1111 B
000007H
PDR7
Port 7 data register
R/W
Port 7
– – XXXXXX B
000008H
PDR8
Port 8 data register
R/W
Port 8
– – – – – XXX B
Register
000009H
to
00000FH
(Vacancy)
000010H
DDR0
Port 0 data direction register
R/W
Port 0
00000000 B
000011H
DDR1
Port 1 data direction register
R/W
Port 1
00000000 B
000012H
DDR2
Port 2 data direction register
R/W
Port 2
00000000 B
000013H
DDR3
Port 3 data direction register
R/W
Port 3
00000000 B
000014H
DDR4
Port 4 data direction register
R/W
Port 4
00000000 B
000015H
DDR5
Port 5 data direction register
R/W
Port 5
0000000– B
000016H
ADER
Analog input enable register
R/W
Analog input
enabled
11111111B
000017H
DDR7
Port 7 data direction register
R/W
Port 7
––000000 B
000018H
DDR8
Port 8 data direction register
R/W
Port 8
– – – – – 00 0 B
000019H
to
00001FH
(Vacancy)
000020H
SCR1
Serial control status register 1
R/W
000021H
SSR1
Serial status register 1
R/W
000022H
SDR1L
Serial data register 1 (L)
R/W
000023H
SDR1H
Serial data register 1 (H)
R/W
XXXXXXXX B
00000100 B
000024H
to
000027H
8/16-bit I/O
simple serial
interface ch. 1
– – – – – – 00 B
XXXXXXXX B
(Vacancy)
000028H
UMC0
Mode control register 0
R/W
000029H
USR0
Status register 0
R/W
00002AH
UIDR0/
UODR0
00002BH
URD0
00002CH
to
00002EH
10000000 B
Input data register 0/
output data register 0
R/W
Rate and data register 0
R/W
00010000 B
UART ch. 0
XXXXXXXX B
00000000 B
(Vacancy)
(Continued)
20
MB90F244
Address
Register
name
00002FH
CKSCR
000030H
ENIR
Read/
write
Resource
name
Initial value
Clock selection register
R/W
PLL
– – – – 1 1 0 0B
DTP/interrupt enable register
R/W
Register
––––0000B
DTP/external
interrupt
000031H
EIRR
DTP/interrupt source register
R/W
000032H
ELVR
Request level setting register
R/W
00000000B
R/W
0 0 0 0 0 0 0 0B
R/W
– – – – 0 0 0 0B
000033H
to
00003FH
000040H
000041H
000042H
000043H
000044H
000045H
(Vacancy)
TMCSR0
Timer control status register #0
TMR0
16-bit timer register #0
TMRLR0
16-bit reload register #0
000046H
000049H
00004AH
00004BH
00004CH
00004DH
TMCSR1
TMR1
16-bit timer register #1
TMRLR1
16-bit reload register #1
000052H
000053H
000054H
000055H
TMCSR2
000061H
000062H
000063H
000064H
000065H
XXXXXXXX B
XXXXXXXX B
W
XXXXXXXX B
W
XXXXXXXX B
R/W
0 0 0 0 0 0 0 0B
R/W
– – – – 0 0 0 0B
R
R
Timer control status register #2
TMR2
16-bit timer register #2
TMRLR2
16-bit reload register #2
000056H
to
00005FH
000060H
16-bit timer #0
16-bit timer #1
XXXXXXXX B
XXXXXXXX B
W
XXXXXXXX B
W
XXXXXXXX B
R/W
0 0 0 0 0 0 0 0B
R/W
– – – – 0 0 0 0B
(Vacancy)
00004FH
000051H
R
Timer control status register #1
00004EH
000050H
R
(Vacancy)
000047H
000048H
––––0000B
R
R
16-bit timer #2
XXXXXXXX B
XXXXXXXX B
W
XXXXXXXX B
W
XXXXXXXX B
R
XXXXXXXX B
R
XXXXXXXX B
16-bit input
XXXXXXXX B
capture 0 and 1
XXXXXXXX B
(Vacancy)
ICP0
Input capture register 0
ICP1
Input capture register 1
ICS0
Input capture control status register 0 and 1
R
R
R/W
00000000B
(Vacancy)
(Continued)
21
MB90F244
Address
000066H
000067H
000068H
000069H
00006AH
Register
name
ICP2
Input capture register 2
R
ICP3
Input capture register 3
R
ICS1
Input capture control status register
2 and 3
00006BH
00006CH
00006DH
00006EH
Read/
write
Register
Resource
name
Initial value
XXXXXXXX B
XXXXXXXX B
16-bit input
XXXXXXXX B
capture 2 and 3
XXXXXXXX B
R/W
00000000B
(Vacancy)
R
TCDT
Timer data register
TCCS
Timer control status register
R
00006FH
0 0 0 0 0 0 0 0B
16-bit freerun
timer
0 0 0 0 0 0 0 0B
R/W
00000000B
(Vacancy)
000070H
ADCS 1
A/D control status register 1
R/W
0 0 0– 0 0 0 0 B
000071H
ADCS 2
A/D control status register 2
R/W
– 0 0 0– – 0 0 B
000072H
ADCT 1
Conversion time setting register 1
R/W
XXXXXXXX B
000073H
ADCT 2
Conversion time setting register 2
R/W
XXXXXXXX B
000074H
ADTL0
A/D data register 0 (L)
R
XXXXXXXX B
000075H
ADTH0
A/D data register 0 (H)
R
000076H
ADTL1
A/D data register 1 (L)
R
000077H
ADTH1
A/D data register 1 (H)
R
– – – – – – XX B
000078H
ADTL2
A/D data register 2 (L)
R
XXXXXXXX B
000079H
ADTH2
A/D data register 2 (H)
R
– – – – – – XX B
00007AH
ADTL3
A/D data register 3 (L)
R
XXXXXXXX B
00007BH
ADTH3
A/D data register 3 (H)
R
– – – – – – XX B
00007CH
to
00008FH
(Vacancy)
000090H
to
00009EH
(System reserved area)*1
Delayed interrupt source generation/
release register
R/W
STBYC
Standby control register
R/W
0000A3H
MACR
Middle address control register
W
0000A4H
HACR
High address control register
W
0000A5H
EPCR
External pin control register
W
00009FH
DIRR
0000A0H
8/10-bit A/D
converter
– – – – – – XX B
XXXXXXXX B
Delayed interrupt
generation
– – – – – – – 0B
module
Low-power
consumption
mode
0 0 0 1XXXX B
*2
External pin
*2
*2
(Continued)
22
MB90F244
(Continued)
Address
Register
name
Read/
write
Resource
name
Initial value
0000A8H
WTC
Watchdog timer control register
R/W
Watchdog
timer
XXXXXXXX B
0000A9H
TBTC
Timebase timer control register
R/W
Timebase
timer
0XX0 0 0 0 0 B
0000AEH
FMCS
Control status register
R/W
Flash memory
0 0 0 X0– – 0 B
0000B0H
ICR00
Interrupt control register 00
R/W*3
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W*3
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W*
3
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W*
3
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W*3
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W*3
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W*3
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W*
3
0000B8H
ICR08
Interrupt control register 08
R/W*
3
0000B9H
ICR09
Interrupt control register 09
R/W*3
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W*3
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W*
3
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W*
3
00000111B
0000BDH
ICR13
Interrupt control register 13
R/W*
3
00000111B
0000BEH
ICR14
Interrupt control register 14
R/W*3
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W*3
00000111B
Register
0000C0H
to
0000FFH
Interrupt
controller
00000111B
00000111B
(External area)*3
Explanation of read/write
R/W : Readable and writable
R : Read only
W : Write only
Explanation of initial values
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X: The initial value of this bit is undefined.
– : This bit is unused. No initial value is defined.
*1: Access prohibited.
*2: The initial values are changed depending on a bus mode.
*3: The only area available for the external access below address 0000FFH is this area. Addresses not explained
in the table are “(reserved area)”; accesses to these areas are handled accesses to internal areas. No access
signal is generated for the external bus.
Note: Do not use any “(vacancy)”.
23
MB90F244
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 4.0
V
VCC5
VSS – 0.3
VSS + 7.0
V
*1
AVCC
VSS – 0.3
VSS + 4.0
V
*2
AVRH
VSS – 0.3
VSS + 4.0
V
*2
AVRL
VSS – 0.3
VSS + 4.0
V
*2
VI1
VSS – 0.3
VCC + 0.3
V
*3
VI2
VSS – 0.3
VCC5 + 0.3
V
*4
Output voltage
VO
VSS – 0.3
VCC + 0.3
V
*3
“L” level maximum output current
IOL

10
mA
“L” level average output current
IOLAV

3
mA
“L” level total maximum output current
ΣIOL

60
mA
“L” level total average output current
ΣIOLAV

30
mA
“H” level maximum output current
IOH

–10
mA
“H” level average output current
IOHAV

–3
mA
“H” level total maximum output current ΣIOH

–60
mA
Power supply voltage
Input voltage
“H” level total average output current
ΣIOHAV

–30
mA
Power consumption
PD

350
mW
Operating temperature
TA
0
+70
°C
Storage temperature
Tstg
–55
+125
°C
*1:
*2:
*3:
*4:
VCC5 must always exceed VCC.
AVCC, AVRH and AVRL must not exceed VCC. Also AVRL must not exceed AVRH.
VI1 and VO must not exceed VCC + 0.3 V.
VI2 must not exceed VCC5 + 0.3 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
24
MB90F244
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
3.0
3.6
V
Normal operation
VCC
3.0
3.6
V
Maintaining the stop
status
VCC5
4.5
5.5
V
0
+70
°C
TA
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
25
MB90F244
3. DC Characteristics
(VCC5 = 5.0 V ±0.5 V, VCC = 3.3 V ±0.3 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
VIH2
VIH1S
“H” level input
voltage
VIH2S
P60 to P63,
P65 to P67,
P70
—
RST, HST
VIHM
MD0 to MD2
VIL2
—
VIL2S
Condition
—
VIH2S5
VIL1S
“L” level input
voltage
Pin name
—
P60 to P63,
P65 to P67,
P70
—
Value
Unit
Remarks
Min.
Max.
0.7 VCC
VCC5 + 0.3
V
TTL input
0.8 VCC
VCC + 0.3
V
CMOS hysteresis input
0.8 VCC
VCC5 + 0.3
V
CMOS hysteresis input
0.8 VCC5 VCC5 + 0.3
V
CMOS hysteresis input
0.7 VCC5 VCC5 + 0.3
V
CMOS input
VSS – 0.3
0.2 VCC
V
TTL input
VSS – 0.3
0.2 VCC
V
CMOS hysteresis input
VSS – 0.3
0.2 VCC
V
CMOS hysteresis input
VIL2S5
RST, HST
VSS – 0.3
0.2 VCC5
V
CMOS hysteresis input
VILM
MD0 to MD2
VSS – 0.3
0.2 VCC5
V
CMOS input
“H” level output
voltage
VOH
All ports
VCC = 3.0 V
except port 6 IOH = –1.6 mA
VCC – 0.3
—
V
“L” level output
voltage
VOL
All ports
—
0.4
V
IIH1
VCC = 3.6 V
MD0 to MD2 VCC5 = 5.5 V
VIH = 0.7 VCC5
—
–10
µA CMOS input
VCC = 3.6 V
VCC5 = 5.5 V
VIH = 2.2 V
—
–10
µA TTL input
IIH3
VCC = 3.6 V
Except port 6,
VCC5 = 5.5 V
RST, HST
VIH = 0.8 VCC
—
–10
µA CMOS hysteresis input
IIH4
P60 to P63,
P65 to P67
VCC = 3.6 V
VCC5 = 5.5 V
VIH = 0.7 VCC
—
–10
µA
IIL1
VCC = 3.6 V
MD0 to MD2 VCC5 = 5.5 V
VIL = 0.3 VCC5
—
10
µA CMOS input
VCC = 3.6 V
VCC5 = 5.5 V
VIL = 0.8 V
—
10
µA TTL input
IIL3
VCC = 3.6 V
Except port 6,
VCC5 = 5.5 V
RST, HST
VIL = 0.2 VCC
—
10
µA CMOS hysteresis input
IIL4
P60 to P63,
P65 to P67
VCC = 3.6 V
VCC5 = 5.5 V
VIL = 0.3 VCC
—
10
µA
IIH2
“H” level input
current
IIL2
“L” level input
current
—
—
VCC = 3.0 V
IOL = 2.0 mA
CMOS hysteresis input
Only port 6
CMOS hysteresis input
Only port 6
(Continued)
26
MB90F244
(Continued)
(VCC5 = 5.0 V ±0.5 V, VCC = 3.3 V ±0.3 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol Pin name
ICC1
Power supply
current*1
Condition
VCC
CPU
normal
mode at
25 MHz
Value
Min. Typ. Max.
Unit
Remarks
VCC = 3.15 V to
3.6 V
—
—
50
mA
Flash memory
read state
VCC = 3.3 V
±0.15 V
—
—
45
mA
Flash memory
read state
Flash memory
read state
ICC1
VCC
ICC51
VCC5
—
—
—
33
mA
ICC2
VCC
VCC = 3.15 V to
3.6 V
—
—
50
Flash memory
mA program/erase
state
VCC = 3.3 V
±0.15 V
—
—
45
Flash memory
mA program/erase
state
—
—
53
Flash memory
mA program/erase
state
CPU sleep mode
At 25 MHz
—
—
20
mA
—
—
5
mA
CPU stop mode
TA = +25°C
—
—
100
µA
—
—
100
µA
—
10
—
pF
22
—
220
kΩ
—
—
—
10
µA
—
TBD
—
3.6
V
ICC2
VCC
ICC52
VCC5
ICCS
VCC
ICC5S
VCC5
ICCH
VCC
CPU
normal
mode at
25 MHz
—
ICC5H
VCC5
Input
capacitance
CIN
Except VCC,
VCC5, VSS
Pull-up resistor
RPULL
RST
Open-drain
output leakage
voltage
ILEAK
Port 6
Low VCC5 lock
voltage*2
VLKO
—
VCC = 3.3 V
VCC5 = 5.0 V
—
*1: Because the current values are tentative values, they are subject to change without notice due to our efforts to
improve the characteristics of these devices.
*2: To prevent improper commands from being activated during rise and fall of VCC5, the internal VCC5 detection
circuit of the flash memory allows only read accesses and ignores write accesses while VCC5 is lower than VLKO.
27
MB90F244
4. Flash Memory Programming/Eraseing Characteristics
(VCC5 = 5.0 V ±0.5 V, VCC = 3.3 V ±0.3 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Condition
Sector eraseing time
Chip eraseing time
Byte programmimg
time
Chip programming
time
Erase/program cycle
TA = +25°C,
VCC = 3.3 V,
VCC5 = 5.0 V
—
Min.
Value
Typ.
Max.
—
1.5
13.5
sec
—
—
27.0
sec
—
16
—
µs
—
2.1
—
sec
100
—
—
cycles
Unit
Remarks
Except for the write time before
internal erase operation
Except for the write time before
internal erase operation
Except for the over head time of
the system
Except for the over head time of
the system
* : The internal automatic algorithm continues operations for up to 48 ms, for each 1-byte writing operation.
28
MB90F244
5. AC Characteristics
(1) Clock Timing
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Symbol
Parameter
Pin name
Condition
Value
Min.
Max.
Unit
FC
X0, X1
VCC = 3.15 V to 3.6 V
—
50
MHz
FC
X0, X1
VCC = 3.3 V ±0.3 V
—
40
MHz
Clock cycle time
tC
X0, X1
1/FC
—
ns
Input clock pulse width
PWH,
PWL
X0
10
—
ns
Input clock
rising/falling time
tCR,
tCF
X0
—
8
ns
Clock frequency
—
Remarks
• Clock timing
tC
0.7 VCC
0.3 VCC
PWH
PWL
tCF
tCR
• Relationship between clock frequency and power supply voltage
Power supply voltagse VCC (V)
3.6
Operation assurunce range
(TA = –0°C to +70°C)
3.15
3.0
40
Source oscillation clock FC (MHz)
50
29
MB90F244
(2) Clock Output Timing
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Symbol
Parameter
Pin name
Cycle time
tCYC
CLK
CLK ↑ → CLK↓
tCHCL
CLK
Value
Condition
—
Min.
Max.
2 tC*
—
1 tCYC/2 – 15 1 tCYC/2 + 15
Unit
Remarks
ns
ns
* : For information on tC (clock cycle time), see “(1) Clock Timing.”
tCYC
tCHCL
2.0 V
2.0 V
0.8 V
CLK
(3) Reset and Hardware Standby Input
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Reset input time
Symbol
Pin name
tRSTL
RST
Hardware standby input time tHSTL
HST
Condition
—
Value
Unit
Min.
Max.
5 tCYC*
—
ns
5 tCYC*
—
ns
Remarks
* : For information on tCYC (cycle time), see “(2) Clock Output Timing.”
Note: When hardware standby input is given, the machine cycle is simultaneously selected to be divide-by-32.
tRSTL, tHSTL
RST
HST
30
0.2 VCC5
0.2 VCC5
MB90F244
(4) Power-on Reset
(AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Symbol
Parameter
Pin name
Power supply rising time
tR
VCC, VCC5
Power supply cut-off time
tOFF
VCC, VCC5
Condition
—
Value
Unit
Min.
Max.
—
30
ms
1
—
ms
Remarks
*
* : Before the power supply rising, VCC must be lower than 0.2 V.
Note: The above standards are the values needed in order to activate a power-on reset.
tR
2.1 V
0.2 V
VCC
0.2 V
0.2 V
tOFF
If power supply voltage needs to be changed in the course of operation, a smooth voltage rise is
recommended by suppressing the voltage variation as shown below.
3.3 V
VCC
3.0 V
Hold RAM data
It is recommended that the rate of
increase in the voltage be kept to
no more than 50 mV/ms.
VSS
31
MB90F244
(5) Bus Read Timing
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Address cycle time
Symbol
Pin name
Value
Condition
Min.
Max.
—
tACYC
AN23 to AN00
2 tCYC* – 10
Valid address → RD ↓ time tAVRL
AN23 to AN00
1 tCYC*/2 – 13
—
ns
RD pulse width
tRLRH
RD
1 tCYC* – 20
—
ns
RD ↓ → data read time
tRLDV
D15 to D00
—
1 tCYC* – 30
ns
Valid address → data read
time
tAVDV
D15 to D00
—
3 tCYC*/2 – 30
ns
RD ↑ → data hold time
tRHDX
D15 to D00
0
—
ns
RD ↑ → address valid time
tRHAX
AN23 to AN00
1 tCYC*/2 – 20
—
ns
Valid address → CLK ↑ time tAVCH
AN23 to AN00,
CLK
1 tCYC*/2 – 20
—
ns
RD ↓ → CLK ↓ time
RD, CLK
1 tCYC*/2 – 20
—
ns
tRLCL
—
* : For information on tCYC (cycle time), see “(2) Clock Output Timing.”
tRLCL
tAVCH
2.0 V
0.8 V
CLK
tAVRL
tRLRH
RD
2.0 V
0.8 V
tRHAX
tACYC
AN23 to AN00
2.0 V
0.8 V
2.0 V
0.8 V
tRLDV
tRHDX
tAVDV
D 15 to D00
32
Unit Remarks
2.0 V
0.8 V
2.0 V
0.8 V
ns
MB90F244
(6) Bus Write Timing
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
Valid address → WR ↓ time tAVWL
AN23 to AN00
WR pulse width
tWLWH
WRL, WRH
Write data → WR ↑ time
tDVWH
D15 to D00
WR ↑ → Data hold time
tWHDX
Value
Condition
—
D15 to D00
Unit Remarks
Min.
Max.
1 tCYC*/2 – 13
—
ns
1 tCYC* – 20
—
ns
1 tCYC* – 33
—
ns
1 tCYC*/2 – 15
—
ns
WR ↑ → Address valid time tWHAX
AN23 to AN00
1 tCYC*/2 – 15
—
ns
WR ↑ → CLK ↓ time
WRL, WRH,
CLK
1 tCYC*/2 – 20
—
ns
tWLCL
* : For information on tCYC (cycle time), see “(2) Clock Output Timing.”
tWLCL
0.8 V
CLK
WR
(WRL, WRH)
tAVWL
tWLWH
2.0 V
0.8 V
AN23 to AN00
tWHAX
2.0 V
0.8 V
2.0 V
0.8 V
tDVWH
D 15 to D00
0.7 V
Write data
0.2 V
tWHDX
0.7 V
0.2 V
33
MB90F244
(7) Ready Input Timing
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol Pin name
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Condition
Value
Unit
Min.
Max.
15
38
ns
0
38
ns
Source oscillation
50 MHz
Remarks
Note: If the RDY setup time is insufficient, use the auto ready function.
CLK
2.0 V
2.0 V
0.8 V
RD/WR
tRYHS
tRYHH
0.8 VCC
RDY
AN23 to AN00
0.8 VCC
External address
Wait cycle
D15 to D00
Read data
D15 to D00
Wait cycle
Write data
(8) Hold Timing
(VCC = 3.0 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Pin floating → HAK ↓ time
Symbol Pin name
tXHAL
HAK
HAK time ↑ → Pin valid time tHAHV
HAK
Condition
—
Value
Unit
Min.
Max.
30
1 tCYC*
ns
1 tCYC*
2 tCYC*
ns
Remarks
* : For information on tCYC (cycle time), see “(2) Clock Output Timing.”
Note: At least one cycle is required from the time when HRQ is fetched until HAK changes.
HRQ
0.2 V
HAK
tXHAL
Pins
34
2.0 V
0.8 V
0.8 V
tHAHV
2.0 V
0.8 V
MB90F244
(9) UART Timing
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Unit
Min.
Max.
8 tCYC*
—
ns
–80
80
ns
100
—
ns
Serial clock cycle time tSCYC
—
SCK ↓ → SOD delay
time
tSLOV
—
Valid SID → SCK ↑
tIVSH
—
SCK ↑ → Valid
SID hold time
tSHIX
—
60
—
ns
Serial clock “H” pulse
width
tSHSL
—
4 tCYC*
—
ns
Serial clock “L” pulse
width
tSLSH
—
4 tCYC*
—
ns
SCK ↓ → SOD delay
time delay time
tSLOV
—
—
150
ns
Valid SID → SCK ↑
tIVSH
—
60
—
ns
SCK ↑ → Valid SID
hold time
tSHIX
—
60
—
ns
For internal shift clock
mode output pin,
CL = 80 pF
For external shift clock
mode output pin,
CL = 80 pF
Remarks
* : For information on tCYC (cycle time), see “(2) Clock Output Timing.”
Notes: • These are the AC characteristics for CLK synchronous mode.
• CL is the load capacitance added to pins during testing.
35
MB90F244
• Internal shift clock mode
tSCYC
SCK0
2.0 V
0.8 V
0.8 V
tSLOV
2.0 V
0.8 V
SOD0
tIVSH
tSHIX
0.8 VCC
2.0 VCC
SID0
0.8 VCC
2.0 VCC
• External shift clock mode
tSLSH
SCK0
tSHSL
2.0 VCC
2.0 VCC
0.8 VCC
0.8 VCC
tSLOV
SOD0
2.0 VCC
0.8 VCC
tIVSH
SID0
36
0.8 VCC
2.0 VCC
tSHIX
0.8 VCC
2.0 VCC
MB90F244
(10) Serial I/O Timing
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol Pin name
Serial clock cycle time tSCYC
—
SCK ↑ → SOD delay
time
tSLOV
—
Valid SID → SCK ↑
tIVSH
—
SCK ↑ → Valid
SID hold time
tSHIX
—
Value
Condition
For internal shift clock
mode output pin,
CL = 80 pF
Unit Remarks
Min.
Max.
2 tCYC*
—
ns
—
1 tCYC*/2
ns
–15
—
ns
1/2 tCYC*
—
ns
* : For information on tCYC (cycle time), see “(2) Clock Output Timing.”
Note: CL is the load capacitance added to pins during testing.
• Internal shift clock mode
tSCYC
SCK1
2.0 V
0.8 V
0.8 V
tSLOV
SOD1
2.0 VCC
0.8 VCC
tIVSH
SID1
0.8 VCC
2.0 VCC
tSHIX
0.8 VCC
2.0 VCC
37
MB90F244
(11) Timer Input Timing
(VCC = 3.0 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Input pulse width
Symbol
tTIWH,
tTIWL
Pin name
Condition
ASR0 to ASR3,
TIN0 to TIN2
—
Value
Min.
Max.
4 tCYC*
—
Unit
Remarks
ns
* : For information on tCYC (cycle time), see “(2) Clock Output Timing.”
2.0 V
2.0 V
ASR0 to ASR3
TIN0 to TIN2
0.8 V
0.8 V
tTIWH
tTIWL
(12) Timer Output Timing
(VCC = 3.0 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
CLK ↑ → Change time
Symbol
tTO
CLK
Pin name
Condition
TOT0 to TOT2
VCC = 3.3 V ±0.3 V
2.0 V
2.0 V
TOT0 to TOT2
0.8 V
tTO
38
Value
Min.
Max.
—
40
Unit Remarks
ns
MB90F244
(13) Trigger Input Timing
(VCC = 3.0 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Input pulse width
Symbol
tTRGH,
tTRGL
Pin name
Value
Condition
ATG,
INT0 to INT3
—
Min.
Max.
5 tCYC*
—
Unit
Remarks
ns
* : For information on tCYC (cycle time), see “(2) Clock Output Timing.”
ATG
INT0 to INT3
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTRGH
tTRGL
39
MB90F244
6. A/D Converter Electrical Characteristics
(VCC = 3.3 V ±0.3 V, VCC5 = 5.0 V ±0.5 V, AVSS = VSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol Pin name
Total error
Linearity error
Differential linearity
error
Zero transition
voltage
Full-scale transition
voltage
8, 10
10
—
—
—
—
—
—
8
—
—
8
T.B.D
T.B.D
bit
LSB Target: ±4.0
LSB Target: ±2.0
—
—
—
—
T.B.D
LSB Target: ±1.9
AVRL
–1.0 LSB
AVRL
+1.0 LSB
AVRL
+4.0 LSB
mV
—
bit
AN4
AVRL
–1.0 LSB
AVRL
+1.0 LSB
AVRL
+1.5 LSB
mV
VFST
AN0 to AN3,
AN5 to AN7
AVRH
–4.0 LSB
AVRH
–1.0 LSB
AVRH
+1.0 LSB
mV
VFST
AN4
AVRH
–2.0 LSB
AVRH
–1.0 LSB
AVRH
+1.0 LSB
mV
1.00
440
120
120
200
—
—
—
—
—
—
—
—
—
—
µs
ns
ns
ns
ns
—
0.1
3
µA
—
—
—
7
7
AVRH
AVCC
AVRH – 2.7
9
8
V
V
V
mA
mA
—
5
µA
1.0
—
1.5
5
mA
µA
—
—
—
—
—
Conversion period b
Conversion period c
Remarks
—
V0T
Conversion period a
Analog port input
IAIN
current
Analog input voltage
—
—
Reference voltage
—
Interchannel
disparity
Unit
AN0 to AN3,
AN5 to AN7
Sampling period
Reference voltage
supply current
Max.
V0T
Conversion time
Power supply
current
Min.
Value
Typ.
AN0 to AN3,
AN5 to AN7
AN4
—
—
—
Resolution
Condition
IA
IAS*2
IR
IRS*2
—
—
—
—
—
—
AN0 to AN7
Setup by ADCT
register
VCC = 3.3 V ±0.3 V*1
—
AN0 to AN7
AVRL
AVRL + 2.7
AVRH
AVRH – AVRL ≥ 2.7
AVRL
0
AVCC = 3.3 V ±0.3 V
—
AVCC
—
AVCC = 3.3 V ±0.15 V
AVCC = 3.3 V
—
—
Stop mode
—
AVRH
AVCC = 3.3 V
Stop
mode
AVRH
—
AN0 to AN3,
AN5 to AN7
—
—
—
4
8-bit precision in
calculation
8-bit precision in
calculation
No rating for
AN4 because
LSB of calculated
by 8-bit
precision
*1: When FC = 50 MHz (frequency), and the machine cycle is 4.0 ns.
The minimum value of the ADCT resister is #A224, differs from that of the MB90F243.
*2: Current when the A/D converter is not operating and the CPU is stopped.
Notes: • The smaller | AVRH – AVRL |, the greater the error would become relatively.
• If the output impedance of the external circuit for the analog input is high, sampling period might be
insufficient. When the sampling period set at near the minimum value, the output impedance of the external
circuit should be less than approximately 300 Ω.
40
MB90F244
• Analog input circuit model diagram
CO = Approx. 60 pF
RON1
RON2
Analog input pin
Approx.
300 Ω
AVRH
Be switched on,
only while A/D
conversion is
performed.
Approx.
C1
150 Ω
Approx.
4 pF
Comparator
Comparator
•
•
•
Comparator
AVRL
Note: Use the values shows as reference only.
41
MB90F244
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divide into 210 .
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values caused by the zero transition error, full-scale
transition error, non-linearity error, differential linearity error, and noise
Digital output
11 1111 1111
11 1111 1110
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1 LSB × N + VOT)
Linearity error
00 0000 0010
00 0000 0001
00 0000 0000
VOT
1 LSB =
VNT
V(N + 1)T
VFST – VOT
[V]
1022
VNT – (1 LSB × N + VOT)
Digital output N
[LSB]
linearity error =
1 LSB
V(N+1)T – VNT
Digital output N
=
– 1 LSB [LSB]
differential linearity error
1 LSB
VOT: Voltage for digital output transit from “000H” to “001H”
VFST: Voltage for digital output transit from “3FEH” to “3FFH”
42
VFST
Analog input
MB90F244
■ INSTRUCTIONS (412 INSTRUCTIONS)
Table 1
Explanation of Items in Table of Instructions
Item
Mnemonic
Explanation
Upper-case letters and symbols: Represented as they appear in assembler
Lower-case letters: Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table 4 for details about meanings of letters in items.
B
Indicates the correction value for calculating the number of actual cycles during
execution of instruction.
The number of actual cycles during execution of instruction is summed with the value in
the “cycles” column.
Operation
Indicates operation of instruction.
LH
Indicates special operations involving the bits 15 through 08 of the accumulator.
Z: Transfers “0”.
X: Extends before transferring.
—: Transfers nothing.
AH
Indicates special operations involving the high-order 16 bits in the accumulator.
*: Transfers from AL to AH.
—: No transfer.
Z: Transfers 00H to AH.
X: Transfers 00H or FFH to AH by extending AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky
bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.
—: No change.
S: Set by execution of instruction.
R: Reset by execution of instruction.
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction (a single instruction
that reads data from memory, etc., processes the data, and then writes the result to
memory.).
*: Instruction is a read-modify-write instruction
—: Instruction is not a read-modify-write instruction
Note: Cannot be used for addresses that have different meanings depending on
whether they are read or written.
43
MB90F244
Table 2
Explanation of Symbols in Table of Instructions
Symbol
A
Explanation
32-bit accumulator
The number of bits used varies according to the instruction.
Byte: Low order 8 bits of AL
Word: 16 bits of AL
Long: 32 bits of AL, AH
AH
High-order 16 bits of A
AL
Low-order 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
SPCU
Stack pointer upper limit register
SPCL
Stack pointer lower limit register
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
addr16
addr24
addr24 0 to 15
addr24 16 to 23
io
Compact direct addressing
Direct addressing
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24
I/O area (000000H to 0000FFH)
(Continued)
44
MB90F244
(Continued)
Symbol
#imm4
#imm8
#imm16
#imm32
ext (imm8)
disp8
disp16
bp
Explanation
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset value
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
Branch specification relative to PC
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
45
MB90F244
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Effective Address Fields
Address format
Number of bytes in
address extemsion*
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left
—
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
0
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
1
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacemen
2
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + dip16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
* : The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in
the Table of Instructions.
46
MB90F244
Table 4
Code
Number of Execution Cycles for Each Form of Addressing
Operand
(a)*
Number of execution cycles for each from of addressing
00 to 07
Ri
RWi
RLi
Listed in Table of Instructions
08 to 0B
@RWj
1
0C to 0F
@RWj +
4
10 to 17
@RWi + disp8
1
18 to 1B
@RWj + disp16
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + dip16
@addr16
2
2
2
1
* : “(a)” is used in the “cycles” (number of cycles) column and column B (correction value) in the Table of Instructions.
Table 5
Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
Operand
(b)*
(c)*
(d)*
byte
word
long
Internal register
+
0
+
0
+
0
Internal RAM even address
+
0
+
0
+
0
Internal RAM odd address
+
0
+
1
+
2
Even address not in internal RAM
+
1
+
1
+
2
Odd address not in internal RAM
+
1
+
3
+
6
External data bus (8 bits)
+
1
+
3
+
6
* : “(b)”, “(c)”, and “(d)” are used in the “cycles” (number of cycles) column and column B (correction value) in the
Table of Instructions.
47
MB90F244
Table 6
Mnemonic
B
Operation
2
2
2
3
1
1
1
2
2+ 2+ (a)
2
2
2
2
2
2
6
3
3
3
3
5
2
2
1
1
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi))+disp8)
byte (A) ← ((SP)+disp8)
byte (A) ←(addr24)
byte (A) ← ((A))
byte (A) ← imm4
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
2
2
MOVX A, dir
2
3
MOVX A, addr16
1
2
MOVX A, Ri
1
2
MOVX A, ear
2+ 2+ (a)
MOVX A, eam
2
2
MOVX A, io
2
2
MOVX A, #imm8
2
2
MOVX A, @A
3
MOVX A,@RWi+disp8 2
6
MOVX A, @RLi+disp8 3
3
3
MOVX A, @SP+disp8
3
5
MOVPX A, addr24
2
2
MOVPX A, @A
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
(b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi))+disp8)
byte (A) ← ((RLi))+disp8)
byte (A) ← ((SP)+disp8)
byte (A) ←(addr24)
byte (A) ← ((A))
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVP
MOVP
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, @SP+disp8
A, addr24
A, @A
A, #imm4
#
~
Transfer Instructions (Byte) [50 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
*
*
*
*
*
*
*
–
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
X
X
X
X
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVP
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
@SP+disp8, A
addr24, A
2
2
2
3
1
1
2
2
2+ 2+ (a)
2
2
6
3
3
3
3
5
(b)
(b)
0
0
(b)
(b)
(b)
(b)
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)) +disp8) ← (A)
byte ((SP)+disp8) ← (A)
byte (addr24) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOVP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Ri, ear
Ri, eam
@A, Ri
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
2
2
2+ 3+ (a)
3
2
3
2
2+ 3+ (a)
2
2
3
3
3
3
2
3
3+ 2+ (a)
0
(b)
(b)
0
(b)
0
(b)
(b)
0
(b)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte ((A)) ← (Ri)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
@AL, AH
2
(b)
byte ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
2
(Continued)
48
MB90F244
(Continued)
Mnemonic
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
#
~
B
2
3
0
2+ 3+ (a) 2× (b)
2
4
0
2+ 5+ (a) 2× (b)
Operation
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH AH
I
S
T
N
Z
V
C
RMW
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
49
MB90F244
Table 7
Mnemonic
B
Operation
2
2
3
2
1
2
1
1
2
1
2+ 2+ (a)
2
2
2
2
3
2
2
3
3
6
3
3
5
3
2
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
(c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
word (A) ← ((SP) +disp8
word (A) ← (addr24)
word (A) ← ((A))
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
3
4
1
1
2
2+
2
2
3
3
5
2
2
2+
2
2+
3
4
4
4+
2
2
2
2
1
2
2+ (a)
2
3
6
3
3
3
2
3+ (a)
3
3+ (a)
2
3
2
2+ (a)
(c)
(c)
0
0
0
0
(c)
(c)
(c)
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← imm16
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
word ((SP) +disp8) ← (A)
word (addr24) ← (A)
word ((A)) ← (RWi)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
MOVW @AL, AH
2
2
(c)
XCHW
XCHW
XCHW
XCHW
2
3
0
2+ 3+ (a) 2× (c)
2
4
0
2+ 5+ (a) 2× (c)
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
A, @SP+disp8
MOVPWA, addr24
MOVPWA, @A
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, # imm16
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi+disp8, A
@RLi+disp8, A
@SP+disp8, A
MOVPWaddr24, A
MOVPW@A, RWi
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
A, ear
A, eam
RWi, ear
RWi, eam
#
Transfer Instructions (Word) [40 Instructions]
~
LH AH
I
S
T
N
Z
V
C
RMW
*
*
*
*
*
*
*
–
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For an explanation of “(a)” and “(c)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual
Cycles.”
50
MB90F244
Table 8
Mnemonic
#
Transfer Instructions (Long Word) [11 Instructions]
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
MOVL A, ear
2
1
MOVL A, eam
2+ 3+ (a)
MOVL A, # imm32
5
3
MOVL A, @SP + disp8 3
4
MOVPL A, addr24
5
4
MOVPL A, @A
2
3
0
(d)
0
(d)
(d)
(d)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (A) ← ((SP) +disp8)
long (A) ← (addr24)
long (A) ← ((A))
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVPL@A, RLi
(d)
long ((A)) ← (RLi)
–
–
–
–
–
*
*
–
–
–
(d)
(d)
0
(d)
long ((SP) + disp8) ← (A)
long (addr24) ← (A)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
2
5
MOVL @SP + disp8, A 3
4
MOVPL addr24, A
5
4
MOVL ear, A
2
2
MOVL eam, A
2+ 3+ (a)
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
51
MB90F244
Table 9
Mnemonic
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
#
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
ADD
A, #imm8
ADD
A, dir
ADD
A, ear
ADD
A, eam
ADD
ear, A
ADD
eam, A
ADDC A
ADDC A, ear
ADDC A, eam
ADDDC A
2
2
0
2
3
(b)
2
2
0
2+ 3+ (a) (b)
2
2
0
2+ 3+ (a) 2× (b)
1
2
0
2
2
0
2+ 3+ (a) (b)
1
3
0
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (Decimal)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
2
2
0
2
3
(b)
2
2
0
2+ 3+ (a) (b)
2
2
0
2+ 3+ (a) 2× (b)
1
2
0
2
2
0
2+ 3+ (a) (b)
1
3
0
byte (A) ← (A) – imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C) (Decimal)
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
ADDW A
1
2
0
ADDW A, ear
2
2
0
ADDW A, eam
2+ 3+ (a) (c)
ADDW A, #imm16 3
2
0
ADDW ear, A
2
2
0
ADDW eam, A
2+ 3+ (a) 2× (c)
ADDCW A, ear
2
2
0
ADDCW A, eam
2+ 3+ (a) (c)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
SUBW A
1
2
0
SUBW A, ear
2
2
0
SUBW A, eam
2+ 3+ (a) (c)
SUBW A, #imm16 3
2
0
SUBW ear, A
2
2
0
SUBW eam, A
2+ 3+ (a) 2× (c)
SUBCW A, ear
2
2
0
SUBCW A, eam
2+ 3+ (a) (c)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) – imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
ADDL
ADDL
ADDL
A, ear
2
5
A, eam
2+ 6+ (a)
A, #imm32 5
4
0
(d)
0
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
SUBL
SUBL
SUBL
A, ear
2
5
A, eam
2+ 6+ (a)
A, #imm32 5
4
0
(d)
0
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) – imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
52
MB90F244
Table 10
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic
#
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
INC
INC
ear
eam
2
2
0
byte (ear) ← (ear) +1
2+ 3+ (a) 2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
DEC
DEC
ear
eam
2
2
0
byte (ear) ← (ear) –1
2+ 3+ (a) 2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
INCW
INCW
ear
eam
2
2
0
word (ear) ← (ear) +1
2+ 3+ (a) 2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
DECW ear
DECW eam
2
2
0
word (ear) ← (ear) –1
2+ 3+ (a) 2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
INCL
INCL
ear
eam
2
4
0
long (ear) ← (ear) +1
2+ 5+ (a) 2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
DECL
DECL
ear
eam
2
4
0
long (ear) ← (ear) –1
2+ 5+ (a) 2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
#
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
2
2
2
2+ 2+ (a)
2
2
0
0
(b)
0
byte (AH) – (AL)
byte (A) – (ear)
byte (A) – (eam)
byte (A) – imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
2
2
2
2+ 2+ (a)
3
2
0
0
(c)
0
word (AH) – (AL)
word (A) – (ear)
word (A) – (eam)
word (A) – imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
3
2+ 4+ (a)
5
3
0
(d)
0
long (A) – (ear)
long (A) – (eam)
long (A) – imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
53
MB90F244
Table 12
Mnemonic
Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions]
#
~
1
DIVU
A
1
*
DIVU
A, ear
2
*2
DIVU
A, eam 2+
MULU
MULU
MULU
MULUW
MULUW
MULUW
Operation
A, eam 2+
*5
0 word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A) Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
*7 long (A)/word (eam)
1
2
2+
1
2
2+
*8
*9
*10
*11
*12
*13
0
0
(b)
0
0
(c)
DIVUW A, ear
DIVUW
B
A
A, ear
A, eam
A
A, ear
A, eam
2
*3
*4
Quotient → word (A) Remainder → word (eam)
byte (AH) × byte (AL) → word (A)
byte (A) × byte (ear) → word (A)
byte (A) × byte (eam) → word (A)
word (AH) × word (AL) → long (A)
word (A) × word (ear) → long (A)
word (A) × word (eam) → long (A)
LH AH
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(b)” and “(c), refer to Table 5, “Correction Values for Number of Cycle Used to Calculate
Number of Actual Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
54
3 when dividing into zero, 6 when an overflow occurs, and 14 normally.
3 when dividing into zero, 5 when an overflow occurs, and 13 normally.
5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally.
3 when dividing into zero, 5 when an overflow occurs, and 21 normally.
4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally.
(b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
(c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, and 7 when byte (AH) is not 0.
3 when byte (ear) is zero, and 7 when byte (ear) is not 0.
4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0.
3 when word (AH) is zero, and 11 when word (AH) is not 0.
3 when word (ear) is zero, and 11 when word (ear) is not 0.
4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0.
MB90F244
Table 13
Mnemonic
Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions]
#
~
1
DIV
A
2
*
DIV
A, ear
2
*2
DIV
A, eam 2+
DIVW A, ear
2
*3
*4
DIVW
A, eam 2+
*5
MUL
MUL
A
A, ear
*8
*9
*10
*11
*12
*13
2
2
MUL
A, eam 2+
MULW A
2
MULW A, ear
2
MULW A, eam 2+
B
Operation
0 word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A) Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
*7 long (A)/word (eam)
Quotient → word (A) Remainder → word (eam)
0
0
(b)
0
0
(b)
byte (AH) × byte (AL) → word (A)
byte (A) × byte (ear) → word (A)
byte (A) × byte (eam) → word (A)
word (AH) × word (AL) → long (A)
word (A) × word (ear) → long (A)
word (A) × word (eam) → long (A)
LH AH
I
S
T
N
Z
V
C
RMW
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(b)” and “(c)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally.
3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally.
4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally.
When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally.
When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally.
When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs,
and 31 + (a) normally.
When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs,
and 32 + (a) normally.
(b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
(c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.
Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in
a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation.
55
MB90F244
Table 14
Mnemonic
#
~
Logical 1 Instructions (Byte, Word) [39 Instructions]
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
0
2
2
0
2+ 3+ (a) (b)
2
3
0
2+ 3+ (a) 2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
0
2
2
0
2+ 3+ (a) (b)
2
3
0
2+ 3+ (a) 2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
*
XOR
XOR
XOR
XOR
XOR
NOT
NOT
NOT
A, #imm8
A, ear
A, eam
ear, A
eam, A
A
ear
eam
2
2
0
2
2
0
2+ 3+ (a) (b)
2
3
0
2+ 3+ (a) 2× (b)
1
2
0
2
2
0
2+ 3+ (a) 2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
byte (A) ← not (A)
byte (ear) ← not (ear)
byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
1
2
0
3
2
0
2
2
0
2+ 3+ (a) (c)
2
3
0
2+ 3+ (a) 2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
*
ORW
ORW
ORW
ORW
ORW
ORW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
1
2
0
3
2
0
2
2
0
2+ 3+ (a) (c)
2
3
0
2+ 3+ (a) 2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
*
XORW
XORW
XORW
XORW
XORW
XORW
NOTW
NOTW
NOTW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
A
ear
eam
1
2
0
3
2
0
2
2
0
2+ 3+ (a) (c)
2
3
0
2+ 3+ (a) 2× (c)
1
2
0
2
2
0
2+ 3+ (a) 2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
word (A) ← not (A)
word (ear) ← not (ear)
word (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
56
MB90F244
Table 15
Mnemonic
#
~
Logical 2 Instructions (Long Word) [6 Instructions]
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
ANDL A, ear
ANDL A, eam
2
5
2+ 6+ (a)
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
A, ear
A, eam
2
5
2+ 6+ (a)
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
XORL A, ear
XORL A, eam
2
5
2+ 6+ (a)
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 16
Mnemonic
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
B
2
0
Operation
byte (A) ← 0 – (A)
NEG
A
1
NEG
NEG
ear
eam
2
2
0
byte (ear) ← 0 – (ear)
2+ 3+ (a) 2× (b) byte (eam) ← 0 – (eam)
2
0
word (A) ← 0 – (A)
NEGW A
1
NEGW ear
NEGW eam
2
2
0
word (ear) ← 0 – (ear)
2+ 3+ (a) 2× (c) word (eam) ← 0 – (eam)
LH AH
I
S
T
N
Z
V
C
RMW
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
For an explanation of “(a)”, “(b)” and “(c)” and refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17
Mnemonic
ABS
A
ABSW A
ABSL A
Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions]
#
~
B
Operation
2
2
2
2
2
4
0
0
0
byte (A) ← absolute value (A)
word (A) ← absolute value (A)
long (A) ← absolute value (A)
Table 18
Mnemonic
#
~
B
NRML A, R0
2
*
0
LH AH
I
S
T
N
Z
V
C
RMW
Z
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
Normalize Instructions (Long Word) [1 Instruction]
Operation
long (A) ← Shifts to the position at
which “1” was set first
byte (R0) ← current shift count
LH AH
–
–
I
S
T
N
Z
V
C
RMW
–
–
*
–
–
–
–
–
* : 5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases.
57
MB90F244
Table 19
Mnemonic
Shift Instructions (Byte/Word/Long Word) [27 Instructions]
#
~
B
RORC A
ROLC A
2
2
2
2
0
0
RORC
RORC
ROLC
ROLC
ear
eam
ear
eam
2
2
0
2+ 3+ (a) 2× (b)
2
2
0
2+ 3+ (a) 2× (b)
ASR
LSR
LSL
A, R0
A, R0
A, R0
2
2
2
*1
*1
*1
ASR
LSR
LSL
A, #imm8 3
A, #imm8 3
A, #imm8 3
Operation
LH AH
I
S
T
N
Z
V
C
RMW
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
*
*
*
*
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*3
*3
*3
0
0
0
byte (A) ← Arithmetic right barrel shift (A, imm8)
byte (A) ← Logical right barrel shift (A, imm8)
byte (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
LSRW A/SHRW A 1
LSLW A/SHLW A 1
2
2
2
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
* *
* R
– *
*
*
*
–
–
–
*
*
*
–
–
–
2
2
2
*1
*1
*1
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0) –
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A, #imm8 3
LSRW A, #imm8 3
LSLW A, #imm8 3
*3
*3
*3
0
0
0
word (A) ← Arithmetic right barrel shift (A, imm8)
word (A) ← Logical right barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
0
0
0
long (A) ← Arithmetic right shift (A, R0)
–
long (A) ← Logical right barrel shift (A, R0) –
long (A) ← Logical left barrel shift (A, R0) –
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
A, #imm8 3
A, #imm8 3
A, #imm8 3
*4
*4
*4
0
0
0
long (A) ← Arithmetic right shift (A, imm8) –
long (A) ← Logical right barrel shift (A, imm8) –
long (A) ← Logical left barrel shift (A, imm8) –
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A
ASRW A, R0
LSRW A, R0
LSLW A, R0
ASRL
LSRL
LSLL
1
word (A) ← Logical right barrel shift (A, R0) –
word (A) ← Logical left barrel shift (A, R0) –
word (A) ← Logical left barrel shift (A, imm8)
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1:
*2:
*3:
*4:
58
3 when R0 is 0, 3 + (R0) in all other cases.
3 when R0 is 0, 4 + (R0) in all other cases.
3 when imm8 is 0, 3 + (imm8) in all other cases.
3 when imm8 is 0, 4 + (imm8) in all other cases.
MB90F244
Table 20
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
#
~
B
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
*
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
3
2
2+
2
2+
4
2
2
3
4+ (a)
3
4+ (a)
3
0
0
0
(c)
0
(d)
0
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
CALL
CALL
CALL
CALLV
CALLP
@ear *4
2
@eam *4 2+
addr16 *5 3
1
#vct4 *5
2
@ear *6
4
(c)
5+ (a) 2× (c)
5
(c)
5
2× (c)
7
2× (c)
CALLP @eam *6
2+
8+ (a)
*2
CALLP addr24 *7
4
7
2× (c)
Branch 1 Instructions [31 Instructions]
Operation
LH AH
I
S
T
N
Z
V
C
RMW
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
( (V) xor (N) ) or (Z) = 1
( (V) xor (N) ) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call linstruction
word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr 0 to 15,
(PCB) ← addr 16 to 23
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(a)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
*7:
3 when branching, 2 when not branching.
3 × (c) + (b)
Read (word) branch address.
W: Save (word) to stack; R: Read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: Read (long word) branch address.
Save (long word) to stack.
59
MB90F244
Table 21
Mnemonic
#
~
B
CBNE A, #imm8, rel 3
CWBNE A, #imm16, rel 4
1
0
0
4
4+
5
5+
*
*1
*1
*3
*1
*3
CBNE
CBNE
CWBNE
CWBNE
ear, #imm8, rel
eam, #imm8, rel
ear, #imm16, rel
eam, #imm16, rel
DBNZ
ear, rel
3
*4
DBNZ
eam, rel
3+
*2
DWBNZ ear, rel
3
*4
DWBNZ eam, rel
3+
INT
#vct8
INT
addr16
INTP
addr24
INT9
RETI
RETIQ *6
2
3
4
1
1
2
LINK
2
#imm8
*2
14
12
13
14
9
11
6
1
1
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
2× (b) Branch when byte (ear) =
(eam) – 1, and (eam) ≠ 0
0 Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
*
S
S
S
S
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
–
–
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retrieve old
frame pointer from stack.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
(b)
0
(c)
0
8× (c)
6× (c)
6× (c)
8× (c)
6× (c)
*5
(c)
4
5
RET *7
RETP *8
LH AH
–
–
(c)
1
Operation
Branch when byte (A) ≠ imm8
Branch when byte (A) ≠ imm16
5
UNLINK
Branch 2 Instructions [20 Instructions]
(c)
(d)
For an explanation of “(b)”, “(c)” and “(d)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
4 when branching, 3 when not branching
5 when branching, 4 when not branching
5 + (a) when branching, 4 + (a) when not branching
6 + (a) when branching, 5 + (a) when not branching
3 × (b) + 2 × (c) when an interrupt request is generated, 6 × (c) when returning from the interrupt.
High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the
instruction branches to the interrupt vector without performing stack operations when the interrupt is generated.
*7: Return from stack (word)
*8: Return from stack (long word)
60
MB90F244
Table 22
Mnemonic
Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
#
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
PUSHW
PUSHW
PUSHW
PUSHW
A
AH
PS
rlst
1
1
1
2
3
3
3
*3
(c)
(c)
(c)
*4
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
3
*2
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)) , (SP) ← (SP)
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
JCTX
@A
1
9
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8 2
CCR, #imm8 2
3
3
0
0
byte (CCR) ← (CCR) and imm8 –
–
byte (CCR) ← (CCR) or imm8
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
2
2
0
0
byte (RP) ← imm8
byte (ILM) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6× (c) Context switch instruction
MOV RP, #imm8
MOV ILM, #imm8
2
2
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
2
3
2+ 2+ (a)
2
2
2+ 1+ (a)
0
0
0
0
word (RWi) ← ear
word (RWi) ← eam
word(A) ← ear
word (A) ← eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
word (SP) ← ext (imm8)
word (SP) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
A, brgl
brg2, A
MOV
brg2, #imm8
2
2
3
*1
1
2
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
byte (brg2) ← imm8
Z
–
–
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
No operation
Prefix code for the common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW SPCU, #imm16 4
MOVW SPCL, #imm16 4
0
0
0
0
word (SPCU) ← (imm16)
word (SPCL) ← (imm16)
Stack check operation enable
Stack check operation disable
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
byte (A) ← position of “1” bit in word (A)
byte (A) ← position of “1” bit in word (A) × 2
byte (A) ← position of “1” bit in word (A) × 4
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
SETSPC
CLRSPC
2
2
2
2
2
2
BTSCN A
BTSCNSA
BTSCNDA
2
2
2
*5
*6
*7
Prefix code for AD space access
Prefix code for DT space access
Prefix code for PC space access
Prefix code for SP space access
Prefix code for no flag change
For an explanation of “(a)” and “(c)”, refer to Tables 4 and 5.
*1: PCB, ADB, SSB, USB, and SPB: 1 cycle
DTB: 2 cycles
DPR: 3 cycles
*2: 3 + 4 × (pop count)
*3: 3 + 4 × (push count)
*4:
*5:
*6:
*7:
Pop count × (c), or push count × (c)
3 when AL is 0, 5 when AL is not 0.
4 when AL is 0, 6 when AL is not 0.
5 when AL is 0, 7 when AL is not 0.
61
MB90F244
Table 23
Bit Manipulation Instructions [21 Instructions]
Mnemonic
#
~
B
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
3
3
3
(b)
(b)
(b)
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
4
4
4
SETB
SETB
SETB
dir:bp
addr16:bp
io:bp
3
4
3
CLRB
CLRB
CLRB
dir:bp
addr16:bp
io:bp
BBC
BBC
BBC
Operation
LH AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
4
4
4
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
3
4
3
4
4
4
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
BBS
BBS
BBS
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS
addr16:bp, rel
5
*2
2× (b)
Branch when (addr16:bp) b = 1, bit = 1
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*3
*4
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
WBTC io:bp
3
*3
*4
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
For an explanation of “(b)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate Number of
Actual Cycles.”
*1:
*2:
*3:
*4:
62
5 when branching, 4 when not branching
7 when condition is satisfied, 6 when not satisfied
Undefined count
Until condition is satisfied
MB90F244
Table 24
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
#
~
B
1
1
1
1
1
1
3
2
1
2
1
2
0
0
0
0
0
0
Operation
byte (A) 0 to 7 ← → (A) 8 to 15
word (AH) ← → (AL)
Byte code extension
Word code extension
Byte zero extension
Word zero extension
Table 25
LH AH
I
S
T
N
Z
V
C
RMW
–
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
S
T
N
Z
V
C
RMW
–
*
–
X
–
Z
String Instructions [10 Instructions]
Mnemonic
#
~
B
MOVS/MOVSI
MOVSD
2
2
*2
*2
*3 Byte transfer @AH+ ← @AL+, counter = RW0 –
*3 Byte transfer @AH– ← @AL–, counter = RW0 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*4 Byte retrieval @AH+ – AL, counter = RW0
*4 Byte retrieval @AH– – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILS/FILSI
2 5m +3 *5 Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI
2
2
*2
*2
*6 Word transfer @AH+ ← @AL+, counter = RW0
*6 Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQD
2
2
*1
*1
*7 Word retrieval @AH+ – AL, counter = RW0
*7 Word retrieval @AH– – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILSW/FILSWI
2 5m +3 *8 Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSWD
SCWEQ/SCWEQI
Operation
LH AH
m: RW0 value (counter value)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
3 when RW0 is 0, 2 + 6 × (RW0) for count out, and 6n + 4 when match occurs
4 when RW0 is 0, 2 + 6 × (RW0) in any other case
(b) × (RW0)
(b) × n
(b) × (RW0)
(c) × (RW0)
(c) × n
(c) × (RW0)
63
MB90F244
Table 26
Mnemonic
MOVM
MOVM
MOVM
MOVM
MOVMW
MOVMW
MOVMW
MOVMW
MOVM
MOVM
MOVM
MOVM
MOVMW
MOVMW
MOVMW
MOVMW
MOVM
@A, @RLi, #imm8
@A, eam, #imm8
addr16, @RLi, #imm8
addr16, eam, #imm8
@A, @RLi, #imm8
@A, eam, #imm8
addr16, @RLi, #imm8
addr16, eam, #imm8
@RLi, @A, #imm8
eam, @A, #imm8
@RLi, addr16, #imm8
eam, addr16, #imm8
@RLi, @A, #imm8
eam, @A, #imm8
@RLi, addr16, #imm8
eam, addr16, #imm8
bnk : addr16, *5
bnk : addr16, #imm8
MOVMW bnk : addr16, *5
bnk : addr16, #imm8
#
Multiple Data Transfer Instructions [18 Instructions]
~
B
1
3
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
7
*
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*
*3
*3
*3
*4
*4
*4
*4
*3
*3
*3
*3
*4
*4
*4
*4
*3
7
*1
*4
Operation
Multiple data trasfer byte ((A)) ← ((RLi))
Multiple data trasfer byte ((A)) ← (eam)
Multiple data trasfer byte (addr16) ← ((RLi))
Multiple data trasfer byte (addr16) ← (eam)
Multiple data trasfer word ((A)) ← ((RLi))
Multiple data trasfer word ((A)) ← (eam)
Multiple data trasfer word (addr16) ← ((RLi))
Multiple data trasfer word (addr16) ← (eam)
Multiple data trasfer byte ((RLi)) ← ((A))
Multiple data trasfer byte (eam) ← ((A))
Multiple data transfer byte ((RLi)) ← (addr16)
Multiple data transfer byte (eam) ← (addr16)
Multiple data trasfer word ((RLi)) ← ((A))
Multiple data trasfer word (eam) ← ((A))
Multiple data transfer word ((RLi)) ← (addr16)
Multiple data transfer word (eam) ← (addr16)
Multiple data transfer
byte (bnk:addr16) ← (bnk:addr16)
Multiple data transfer
word (bnk:addr16) ← (bnk:addr16)
LH AH
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1: 5 + imm8 × 5, 256 times when imm8 is zero.
*2: 5 + imm8 × 5 + (a), 256 times when imm8 is zero.
*3: Number of transfers × (b) × 2
*4: Number of transfers × (c) × 2
*5: The bank register specified by “bnk” is the same as for the MOVS instruction.
64
I
MB90F244
■ ORDERING IMFORMATION
Part number
MB90F244PFT-G
Package
Remarks
80-pin Plastic TQFP
(FPT-80P-M15)
65
MB90F244
■ PACKAGE DIMENSIONS
80-pin Plastic TQFP
(FPT-80P-M15)
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
+0.05
60
0.145 −0.03
+.002
.006 −.001
41
61
40
80
21
Details of "A" part
1.20(.047)MAX
Mounting height
20
1
0.50(.020)
TYP
+0.05
0.22 −0.04
+.002
.009 −.002
0.08(.003)
"A"
0˚~8˚
M
0.10±0.05(.004±.002)
(Stand off height)
0.25(.010)
0.45/0.75
(.018/.0295)
0.08(.003)
C
66
1997 FUJITSU LIMITED F80028S-1C-1
Dimensions in mm (inches)
MB90F244
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
http://www.fmap.com.sg/
F9807
 FUJITSU LIMITED Printed in Japan
67