FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16507-1E
32-bit Proprietary Microcontroller
CMOS
FR60Lite MB91260B Series
MB91263B/MB91F264B
■ DESCRIPTION
The MB91260B series is a 32-bit RISC microcontroller designed by Fujitsu for embedded control applications
which require high-speed processing.
The CPU is used the FR family and the compatibility of FR60Lite.
■ FEATURES
• FR60Lite CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method)
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
• Memory-to-memory transfer, bit handling, barrel shift instructions, etc : Instructions suitable for embedded
applications
• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
(Continued)
■ PACKAGES
100-pin plastic QFP
100-pin plastic LQFP
(FTP-100P-M06)
(FTP-100P-M05)
MB91260B Series
(Continued)
• Register interlock function : Facilitates coding in assembler.
• Built-in multiplier with instruction-level support
• 32 bit multiplication with sign : 5 cycles
• 16 bit multiplication with sign : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• FR family instruction compatible
• Internal peripheral functions
• Capacity of internal ROM and ROM type
MASK ROM : 128 KB (MB91263B)
FLASH ROM : 256 KB (MB91F264B)
• Capacity of internal RAM : 8 KB
• A/D converter (sequential comparison type)
• Resolution : 10 bits : 2 ch × 2 units, 8 ch × 1 unit
• Conversion time : 1.2 µs (Minimum conversion time system clock at 33 MHz)
1.35 µs (Minimum conversion time system clock at 20 MHz)
• External interrupt input : 10 ch
• Bit search module (for REALOS)
Function for searching the MSB in each word for the first 1-to-0 inverted bit position
• UART (Full-duplex double buffer) : 3 ch
Selectable parity On/Off
Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
Internal timer for dedicated baud rate (U-Timer) on each channel
External clock can be used as transfer clock
Error detection function for parity, frame and overrun errors
• 8/16-bit PPG timer : 16 ch (at 8-bit) / 8 ch (at 16-bit)
• Reload timer : 3 ch (with cascade mode, without output of reload timer 0)
• Free-run timer : 1 ch
• PWC timer : 2 ch
• Input capture : 4 ch (interface with free-run timer)
• Output compare : 6 ch (interface with free-run timer)
• Waveform generator
Various waveforms which are generated by using output compare, 16-bit PPG timer 0 and 16-bit dead timer
• SUM of products macro (simple DSP)
RAM : instruction RAM
256 × 16-bit
XRAM
64 × 16-bit
YRAM
64 × 16-bit
Execution of 1 cycle product addition (16-bit × 16-bit + 40 bits)
Operation results are extracted rounded from 40 to 16 bits
• DMAC (DMA Controller) : 5 ch
Operation of transfer and activation by internal peripheral interrupts and software
• Watchdog timer
• Low Power Consumption Mode
Sleep/stop function
• Package : QFP-100, LQFP-100
• Technology : CMOS 0.35 µm
• Power supply : 1-power supply [Vcc = 4.0 V to 5.5 V]
2
MB91260B Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P22/SCK0
P21/SOT0
P20/SIN0
P17
P16/PPG15
X0
X1
VSS
VCC
P15/PPG14
P14/PPG13
P13/PPG12
P12/PPG11
P11/PPG10
P10/PPG9
P07/PPG8
P06/PPG7
P05/PPG6
P04/PPG5
P03/PPG4
(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P02/PPG3
P01/PPG2
P00/PPG1
INIT
MD0
MD1
MD2
NMI
P77/ADTG2
P76/ADTG1
P75/ADTG0
P74/PWI1
VSS
VCC
P73/PWI0
P72/DTTI
P71/TOT2
P70/TOT1
P63/INT9
P62/INT8
P61/IC3
P60/IC2
P37/IC1
P36/IC0
P35/RTO5
P34/RTO4
P33/RTO3
P32/RTO2
P31/RTO1
P30/RTO0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PE1/AN11
PE0/AN10
AVRH2
ACC
AVCC
AVRH1
AVSS
PD1/AN9
PD0/AN8
AVRH0
PC7/AN7
PC6/AN6
PC5/AN5
PC4/AN4
PC3/AN3
PC2/AN2
PC1/AN1
PC0/AN0
VCC
VSS
P23/SIN1
P24/SOT1
P25/SCK1
P26/INT6
P27/INT7
P50
P51/TIN0
P52/TIN1
P53/TIN2
P54/INT0
P55/INT1
P56/INT2
P57/INT3
PG0/CKI/INT4
PG1/PPG0/INT5
PG2
VCC
VSS
C
PG3/SIN2
PG4/SOT2
PG5/SCK2
P40
P41
P42
P43
P44
P45
P46
P47
(FPT-100-M06)
(Continued)
3
MB91260B Series
(Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P24/SOT1
P23/SIN1
P22/SCK0
P21/SOT0
P20/SIN0
P17
P16/PPG15
X0
X1
VSS
VCC
P15/PPG14
P14/PPG13
P13/PPG12
P12/PPG11
P11/PPG10
P10/PPG9
P07/PPG8
P06/PPG7
P05/PPG6
P04/PPG5
P03/PPG4
P02/PPG3
P01/PPG2
P00/PPG1
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P45
P46
P47
PE1/AN11
PE0/AN10
AVRH2
ACC
AVCC
AVRH1
AVSS
PD1/AN9
PD0/AN8
AVRH0
PC7/AN7
PC6/AN6
PC5/AN5
PC4/AN4
PC3/AN3
PC2/AN2
PC1/AN1
PC0/AN0
VCC
VSS
P30/RTO0
P31/RTO1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P25/SCK1
P26/INT6
P27/INT7
P50
P51/TIN0
P52/TIN1
P53/TIN2
P54/INT0
P55/INT1
P56/INT2
P57/INT3
PG0/CKI/INT4
PG1/PPG0/INT5
PG2
VCC
VSS
C
PG3/SIN2
PG4/SOT2
PG5/SCK2
P40
P41
P42
P43
P44
(FPT-100-M05)
4
INIT
MD0
MD1
MD2
NMI
P77/ADTG2
P76/ADTG1
P75/ADTG0
P74/PWI1
VSS
VCC
P73/PWI0
P72/DTTI
P71/TOT2
P70/TOT1
P63/INT9
P62/INT8
P61/IC3
P60/IC2
P37/IC1
P36/IC0
P35/RTO5
P34/RTO4
P33/RTO3
P32/RTO2
MB91260B Series
■ PIN DESCRIPTION
Pin no.
Pin Circuit
QFP LQFP name type
SIN1
1
99
D
SOT1
100
D
P24
SCK1
3
4
5
1
D
8
UART1 clock input/output terminal.
This function becomes valid when clock input/output is set to enabled.
INT6
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
E
P26
General purpose input/output port.
This function is always valid.
INT7
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
3
E
General purpose input/output port.
This function is always valid.
P50
C
General purpose input/output port.
C
External trigger input terminal of reload timer 0.
When use the terminal as trigger input, set the corresponding data
direction resister (DDR) to input.
TIN0
7
General purpose input/output port.
This function becomes valid when data output of UART1 is set to disabled.
General purpose input/output port.
This function becomes valid when clock input/output is set to disabled.
2
4
UART1 data output terminal.
This function becomes valid when data output of UART1 is set to enabled.
P25
P27
6
UART1 data input terminal.
When use the terminal as data input of UART1, set the corresponding data
direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
P23
2
Description
5
P51
General purpose input/output port.
This function is always valid.
TIN1
External trigger input terminal of reload timer 1.
When use the terminal as external trigger input, set the corresponding data
direction resister (DDR) to input.
6
C
P52
General purpose input/output port.
This function is always valid.
(Continued)
5
MB91260B Series
Pin no.
Pin
Circuit
type
QFP LQFP name
TIN2
9
10
11
12
13
14
7
C
External trigger input terminal of reload timer 2.
When use the terminal as external trigger input, set the corresponding data
direction resister (DDR) to input.
P53
General purpose input/output port.
This function is always valid.
INT0
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
8
E
P54
General purpose input/output port.
This function is always valid.
INT1
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
9
E
P55
General purpose input/output port.
This function is always valid.
INT2
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
10
E
P56
General purpose input/output port.
This function is always valid.
INT3
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
11
12
Description
E
P57
General purpose input/output port.
This function is always valid.
CKI
External clock input terminal for free-run timer.
When use the terminal as external clock input of free-run timer, set the
corresponding data direction resister (DDR) to input.
INT4
PG0
E
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
(Continued)
6
MB91260B Series
Pin no.
Pin Circuit
QFP LQFP name type
Output terminal of PPG timer 0.
This function becomes valid when output of PPG timer 0 is set to enabled.
PPG0
15
13
INT5
E
14
PG2
C
General purpose input/output port.
D
UART2 data input terminal.
When use the terminal as data input of UART2, set the corresponding data
direction resister (DDR) to input.
SIN2
20
18
General purpose input/output port.
This function is always valid.
PG3
SOT2
21
19
D
PG4
SCK2
22
20
External interrupt input terminal.
When use the terminal as external input, output of PPG timer 0 is set to disabled,
and set the corresponding data direction resister (DDR) to input.
General purpose input/output port.
This function becomes valid when output of PPG temer 0 is set to disabled.
PG1
16
Description
D
PG5
UART2 data output terminal.
This function becomes valid when data output of UART2 is set to enabled.
General purpose input/output port.
This function becomes valid when data output of UART2 is set to disabled.
UART2 clock input/output terminal.
This function becomes valid when clock input/output of UART2 is set to enabled.
General purpose input/output port.
This function becomes valid when clock input/output of UART2 is set to disabled.
23
21
P40
C
General purpose input/output port.
24
22
P41
C
General purpose input/output port.
25
23
P42
C
General purpose input/output port.
26
24
P43
C
General purpose input/output port.
27
25
P44
C
General purpose input/output port.
28
26
P45
C
General purpose input/output port.
29
27
P46
C
General purpose input/output port.
30
28
P47
C
General purpose input/output port.
G
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR2 resister to
analog input.
AN11
31
29
PE1
General purpose input/output port.
This function becomes valid when set the corresponding AICR2 resister to port.
(Continued)
7
MB91260B Series
Pin no.
Pin Circuit
QFP LQFP name type
AN10
32
38
39
41
42
43
44
45
30
G
Description
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR2 resister to
analog input.
PE0
General purpose input/output port.
This function becomes valid when set the corresponding AICR2 resister to port.
AN9
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR1 resister to
analog input.
36
G
PD1
General purpose input/output port.
This function becomes valid when set the corresponding AICR1 resister to port.
AN8
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR1 resister to
analog input.
37
G
PD0
General purpose input/output port.
This function becomes valid when set the corresponding AICR1 resister to port.
AN7
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
39
G
PC7
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
AN6
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
40
G
PC6
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
AN5
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
41
G
PC5
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
AN4
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
42
G
PC4
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
AN3
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
43
G
PC3
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
(Continued)
8
MB91260B Series
Pin no.
Pin
Circuit
type
QFP LQFP name
AN2
46
47
48
51
44
G
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
AN1
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
45
G
PC1
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
AN0
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
46
G
PC0
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
RTO0
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
49
J
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
RTO1
50
J
RTO2
51
J
RTO3
52
J
P33
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P32
54
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P31
53
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
PC2
P30
52
Description
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
(Continued)
9
MB91260B Series
Pin no.
Pin Circuit
QFP LQFP name type
RTO4
55
53
J
RTO5
57
58
59
60
61
62
54
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P34
56
Description
J
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
P35
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
IC0
Trigger input terminal of input capture 0.
When use the terminal as trigger input of input capture, set the corresponding data
direction resister (DDR) to input.
55
D
P36
General purpose input/output port.
This function is always valid.
IC1
Trigger input terminal of input capture 1.
When use the terminal as trigger input of input capture, set the corresponding data
direction resister (DDR) to input.
56
D
P37
General purpose input/output port.
This function is always valid.
IC2
Trigger input terminal of input capture 2.
When use the terminal as trigger input of input capture, set the corresponding data
direction resister (DDR) to input.
57
D
P60
General purpose input/output port.
This function is always valid.
IC3
Trigger input terminal of input capture 3.
When use the terminal as trigger input of input capture, set the corresponding data
direction resister (DDR) to input.
58
D
P61
General purpose input/output port.
This function is always valid.
INT8
External interrupt input terminal.
When use the terminal as external input, set the corresponding data direction
resister (DDR) to input.
59
E
P62
General purpose input/output port.
This function is always valid.
INT9
External interrupt input terminal.
When use the terminal as external input, set the corresponding data direction
resister (DDR) to input.
60
E
P63
General purpose input/output port.
This function is always valid.
(Continued)
10
MB91260B Series
Pin no.
QFP LQFP
Pin
name
Circuit
type
TOT1
63
64
65
61
C
General purpose input/output port.
This function becomes valid when reload timer output is set to disabled.
TOT2
Output terminal of reload timer 2.
This function becomes valid when reload timer output is set to enabled.
62
C
P71
General purpose input/output port.
This function becomes valid when reload timer output is set to disabled.
DTTI
Outputcontrol input terminal of waveform generator output terminal RTO0 to
RTO5 of multi-function timer.
This function becomes valid when DTTI input is set to enabled by waveform
generator of multi-function timer.
63
D
General purpose input/output port.
This function is always valid.
PWI0
64
D
PWI1
67
D
ADTG0
68
C
ADTG1
69
C
ADTG2
70
C
71
NMI
External trigger input terminal of A/D converter 2.
When use the external trigger as activation factor of A/D convertor, set the
corresponding data direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
P77
73
External trigger input terminal of A/D converter 1.
When use the external trigger as activation factor of A/D convertor, set the
corresponding data direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
P76
72
External trigger input terminal of A/D converter 0.
When use the external trigger as activation factor of A/D convertor, set the
corresponding data direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
P75
71
Pulse width counter input terminal of PWC timer 1.
This function becomes valid when pulse width counter input of PWC timer 1 is
set to enabled.
General purpose input/output port.
This function is always valid.
P74
70
Pulse width counter input terminal of PWC timer 0.
This function becomes valid when pulse width counter input of PWC timer 0 is
set to enabled.
General purpose input/output port.
This function is always valid.
P73
69
Output terminal of reload timer 1.
This function becomes valid when reload timer output is set to enabled.
P70
P72
66
Description
H
NMI (Non Maskable Interrupt) input terminal.
(Continued)
11
MB91260B Series
Pin no.
QFP
Pin Circuit
LQFP name type
Description
74
72
MD2
K
Mode terminal 2.
Set operating mode. Connect to VCC or VSS.
75
73
MD1
K
Mode terminal 1.
Set operating mode. Connect to VCC or VSS.
76
74
MD0
K
Mode terminal 0.
Set operating mode. Connect to VCC or VSS.
77
75
INIT
I
External reset input terminal.
PPG1
78
79
80
81
82
83
84
76
C
Output terminal of PPG timer 1.
This function becomes valid when output of PPG timer 1 is set to enabled.
P00
General purpose input/output port.
This function becomes valid when output of PPG timer 1 is set to disabled.
PPG2
Output terminal of PPG timer 2.
This function becomes valid when output of PPG timer 2 is set to enabled.
77
C
P01
General purpose input/output port.
This function becomes valid when output of PPG timer 2 is set to disabled.
PPG3
Output terminal of PPG timer 3.
This function becomes valid when output of PPG timer 3 is set to enabled.
78
C
P02
General purpose input/output port.
This function becomes valid when output of PPG timer 3 is set to disabled.
PPG4
Output terminal of PPG timer 4.
This function becomes valid when output of PPG timer 4 is set to enabled.
79
C
P03
General purpose input/output port.
This function becomes valid when output of PPG timer 4 is set to disabled.
PPG5
Output terminal of PPG timer 5.
This function becomes valid when output of PPG timer 5 is set to enabled.
80
C
P04
General purpose input/output port.
This function becomes valid when output of PPG timer 5 is set to disabled.
PPG6
Output terminal of PPG timer 6.
This function becomes valid when output of PPG timer 6 is set to enabled.
81
C
P05
General purpose input/output port.
This function becomes valid when output of PPG timer 6 is set to disabled.
PPG7
Output terminal of PPG timer 7.
This function becomes valid when output of PPG timer 7 is set to enabled.
82
C
P06
General purpose input/output port.
This function becomes valid when output of PPG timer 7 is set to disabled.
(Continued)
12
MB91260B Series
Pin no.
QFP
LQFP
Pin
name
Circuit
type
PPG8
85
86
87
88
89
90
91
83
C
Description
Output terminal of PPG timer 8.
This function becomes valid when output of PPG timer 8 is set to enabled.
P07
General purpose input/output port.
This function becomes valid when output of PPG timer 8 is set to disabled.
PPG9
Output terminal of PPG timer 9.
This function becomes valid when output of PPG timer 9 is set to enabled.
84
C
P10
General purpose input/output port.
This function becomes valid when output of PPG timer 9 is set to disabled.
PPG10
Output terminal of PPG timer 10.
This function becomes valid when output of PPG timer 10 is set to enabled.
85
C
P11
General purpose input/output port.
This function becomes valid when output of PPG timer 10 is set to disabled.
PPG11
Output terminal of PPG timer 11.
This function becomes valid when output of PPG timer 11 is set to enabled.
86
C
P12
General purpose input/output port.
This function becomes valid when output of PPG timer 11 is set to disabled.
PPG12
Output terminal of PPG timer 12.
This function becomes valid when output of PPG timer 12 is set to enabled.
87
C
P13
General purpose input/output port.
This function becomes valid when output of PPG timer 12 is set to disabled.
PPG13
Output terminal of PPG timer 13.
This function becomes valid when output of PPG timer 13 is set to enabled.
88
C
P14
General purpose input/output port.
This function becomes valid when output of PPG timer 13 is set to disabled.
PPG14
Output terminal of PPG timer 14.
This function becomes valid when output of PPG timer 14 is set to enabled.
89
C
P15
General purpose input/output port.
This function becomes valid when output of PPG timer 14 is set to disabled.
94
92
X1
A
Main clock oscillation output terminal.
95
93
X0
A
Main clock oscillation input terminal.
PPG15
96
94
C
P16
97
95
P17
96
P20
General purpose input/output port.
This function becomes valid when output of PPG timer 15 is set to disabled.
C
General purpose input/output port.
D
UART0 data input terminal.
When use the terminal as data input of UART0, set the corresponding data
direction resister (DDR) to input.
SIN0
98
Output terminal of PPG timer 15.
This function becomes valid when output of PPG timer 15 is set to enabled.
General purpose input/output port.
This function is always valid.
(Continued)
13
MB91260B Series
(Continued)
Pin no.
QFP
Pin Circuit
LQFP name type
SOT0
99
97
D
P21
SCK0
100
98
D
P22
Description
UART0 data output terminal.
This function becomes valid when data output of UART0 is set to enabled.
General purpose input/output port.
This function becomes valid when data output of UART0 is set to disabled.
UART0 clock input/output terminal.
This function becomes valid when clock input/output of UART0 is set to enabled.
General purpose input/output port.
This function becomes valid when clock input/output of UART0 is set to disabled.
• Power supply and GND pins
Pin no.
14
Pin name
Description
QFP
LQFP
18, 50, 68, 93
16, 48, 66, 91
Vss
GND pins.
Apply equal potential to all of the pins.
17, 49, 67, 92
15, 47, 65, 90
Vcc
Power supply pin.
Apply equal potential to all of the pins.
35
33
AVcc
33
31
AVRH2
Analog reference power supply pin for A/D converter 2.
36
34
AVRH1
Analog reference power supply pin for A/D converter 1.
40
38
AVRH0
Analog reference power supply pin for A/D converter 0.
37
35
AVss
19
17
C
34
32
ACC
Analog power supply pin for A/D converter.
Analog GND pin for A/D converter.
Condencer connection pin for internal regulator.
Condencer connection pin for analog.
MB91260B Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
X1
Clock input
A
• Oscillation circuit
• Oscillation feedback resistance :
approx. 1 MΩ
X0
Standby control
P-ch
Pull-up control
• CMOS level output
• CMOS level input.
Digital output
• With standby control
• With Pull-up control
• Pull-up resistance value =
approx. 50 kΩ (Typ)
P-ch
C
Digital output
R
N-ch
• IOL = 4 mA
Digital input
Standby control
Pull-up control
P-ch
Digital output
P-ch
D
Digital output
R
N-ch
• CMOS level output
• CMOS level hysteresis input.
• With standby control
• With Pull-up control
• Pull-up resistance value =
approx. 50 kΩ (Typ)
• IOL = 4 mA
Digital input
Standby control
(Continued)
15
MB91260B Series
Type
Circuit type
P-ch
Remarks
Pull-up control
• CMOS level output
• CMOS level hysteresis input.
Digital output
• Without standby control
• With Pull-up control
• Pull-up resistance value =
approx. 50 kΩ (Typ)
P-ch
E
Digital output
N-ch
R
• IOL = 4 mA
Digital input
Digital output
P-ch
Digital output
G
N-ch
R
Digital input
• Analog/CMOS level input/output pin
• CMOS level output
• CMOS level input.
(attached with standby control)
• Analog input
(Analog input is enabled when AICR’s
corresponding bit is set to “1”.)
• IOL = 4 mA
Standby control
Analog input
• CMOS level hysteresis input.
• Without standby control
P-ch
H
R
N-ch
Digital input
(Continued)
16
MB91260B Series
(Continued)
Type
Circuit type
Remarks
• CMOS level hysteresis input.
P-ch
• With pull-up resistor
• Pull-up resistance value =
approx. 50 kΩ (Typ)
P-ch
I
• Without standby control
R
N-ch
Digital input
• CMOS level output
• CMOS level hysteresis input.
Digital output
• With standby control
P-ch
Digital output
J
R
• IOL = 12 mA
N-ch
Digital input
Standby control
• CMOS level input.
• Without standby control
P-ch
K
R
N-ch
Digital input
17
MB91260B Series
■ HANDLING DEVICES
• Preventing Latchup
Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output
pin or if an above-rating voltage is applied between VCC and VSS.
A latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an
element. When you use a CMOS IC, be very careful not to exceed the maximum rating.
• Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor.
• About power supply pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However you must connect the pins to external a same potential
power supply and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of
strobe signals caused by the rise in the ground level, and to conform to the total current rating.
The power pins should be connected to VCC and VSS of this device at the lowest possible impedance from the
current supply source.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near
this device.
• About Crystal oscillator circuit
Noise near the X0 and X1 pin may cause the device to malfunction.
Design the circuit board so that X0 and X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0 and XI pins surrounded by ground plane
because stable operation can be expected with such a layout.
• Mode pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS.
To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low.
• Operation at start-up
Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up.
Also, in order to provide a delay while the oscillator circuit stabilize immediately after start-up, maintain the "L"
level input to the INIT pin for the required stabilization wait time.
(For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)
• About oscillation input at power on
When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.
18
MB91260B Series
• Caution operation during PLL clock mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for this device, the device
may continue to operate at the free-run frequency of the PLL’s internal self-oscillating oscillator circuit.
Performance of this operation, however, cannot be guaranteed.
• External clock
When external clock is selected, the opposite phase clock to X0 pin must be supplied to X1 pin simultaneously.
If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H" output. So,
when STOP mode is specified, approximately 1 kΩ of resistance should be added externally to avoid the conclift
of output.
The following figure shows using an external clock.
X0
X1
MB91260B series
Using an external clock
• C pin
A bypass capacitor of approximately 0.1 µF should be connected the C pin for built-in regulator.
C
MB91260B series
0.1 µF
VSS
GND
• ACC pin
A capacitor of approximately 0.1 µF should be inserted between the ACC pin and the AVcc pin as this product
has built-in A/D convertor.
ACC
MB91260B series
0.1 µF
AVSS
19
MB91260B Series
• Clock control block
Take the oscillation stabilization wait time during Low level input to the INIT pin.
• Switch shared port function
To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR).
• Low Power Consumption Mode
(1) To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR:
or time-base counter control register) and be sure to use the following seaquence
(LDI
#value_of_standby, R0)
: Value_of standby is write data to STCR.
(LDI
#_STCR, R12)
: _STCR is address (481H) of STCR.
STB
R0, @R12
: Writing to standby control register (STCR)
LDUB
@R12, R0
: STCR read for synchronous standby
LDUB
@R12, R0
: Dummy re-read of STCR
NOP
: NOP × 5 for arrangement of timing
NOP
NOP
NOP
NOP
In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after
the standby returns.
(2) Please do not do the following when the monitor debugger is used.
• Break point setting for above instruction lines
• Step execution for above instruction lines
• Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.
1. The following operations are performed when the instruction followed by a DIV0U/DIV0S instruction results
in : (a) acceptance of a user interrupt or NMI, (b) step execution, or (c) a break at a data event or emulator menu.
(1) The D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).
2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger even has occurred.
(1) The PS register is updated in advance.
(2) An EIT handling routine (user interrupt, NMI) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1).
20
MB91260B Series
• Watch dog timer
The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time.
The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from
being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on
operating programs until it resets the CPU.
As an exception, the watchdog timer defers a reset timing automatically under the condition in which the CPU
stops program execution.
21
MB91260B Series
■ NOTE ON DEBUGGER
• Step execution of RETI command
If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed
repeatedly after step execution.
This will prevent the main routine and low-interrupt-level programs from being executed.
Do not execute step of RETI instruction for escape.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine
no longer needs debugging.
• Operand break
Do not apply a data event break to access to the area containing the address of a system stack pointer.
• Execution in an unused area of FLASH memory
Accidentally executing an instruction in an unused area of FLASH memory (with data placed at 0XFFFF) prevents
breaks from being accepted.
To prevent this, the code event address mask function of the debugger should be used to cause a break when
accessing an instruction in an unused area.
• Power-on debugging
All of the following three conditions must be satisfied when the power supply is turned off by power-on debugging.
(1) The time for the user power to fall from 0.9 VCC to 0.5 VCC is 25 µs or longer.
Note : In a dual-power system, VCC indicates the external I/O power supply voltage.
(2) CPU operating frequency must be higher than 1 MHz.
(3) During execution of user program
• Interrupt handler for NMI request (tool)
Add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor
flag to be set only in response to a break request from the ICE is set, for example, by an adverse effect of noise
to the DSU pin while the ICE is not connected. Enable to use the ICE while adding this program.
Additional location
Next interrupt handler
Interrupt source
: NMI request (tool)
Interrupt number
: #13 (decimal) , 0DH (hexa decimal)
Offset
: 3C8H
Address TBR is default
: 000FFFC8H
Additional program
STM
(R0, R1)
LDI
#B00H, R0;
LDI
#0, R1
STB
R1, @R0
LDM
(R0, R1)
RETI
22
: B00H is the address of DSU break factor register.
: Clear the break factor register.
MB91260B Series
■ BLOCK DIAGRAM
FR60 Lite CPU core
32
32
DMAC 5 ch
Bit search
SUM of products macro
Bus converter
ROM 128 KB/
FLASH 256 KB
RAM 8 KB
X0, X1
MD0 ~ MD2
INIT
32
32 ↔ 16
Adapter
Clock
control
16
Interrupt
controller
INT0 ~ INT9
NMI
10 ch
External interrupt
SCK0 ~ SCK2
3 ch
reload timer
2 ch
PWC timer
SIN0 ~ SIN2
SOT0 ~ SOT2
Port I/F
PORT
TIN0 ~ TIN2
TOT1, TOT2
PWI0, PWI1
3 ch
UART
8 ch
8/16 PPG timer
PPG0 ~ PPG15
3 ch
U timer
AVCC
Multi-function timer
ADTG0
AN0 ~ AN7
AVRH0
8 ch input
8/10 bit A/D-0
ADTG1
AVRH1
AN8, AN9
ADTG2
AVRH2
AN10, AN11
Free-run timer 1 ch
CKI
2 ch input
8/10 bit A/D-1
Input capture 4 ch
IC0 ~ IC3
2 ch input
8/10 bit A/D-2
Waveform generator
Output compare 6 ch
RTO0 ~ RTO5
DTTI
23
MB91260B Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The size of directly addressable areas depends on the data size to be being accessed as follows.
→ byte data access
→ half word data access
→ word data access
: 000-0FFH
: 000-1FFH
: 000-3FFH
2. Memory Map
MB91263B
MB91F264B
Single chip mode
Single chip mode
0000 0000H
0000 0000H
I/O
Direct
addressing area
0000 0400H
I/O
0001 0000H
Access
disallowed
0003 E000H
Internal RAM
8 KB
0004 0000H
Refer to I/O Map
0001 0000H
I/O
Refer to I/O Map
0003 E000H
Access
disallowed
Internal RAM
8 KB
0004 0000H
Access
disallowed
000E 0000H
000C 0000H
Internal RAM
256 KB
0010 0000H
Internal RAM
128 KB
Access
disallowed
Access
disallowed
FFFF FFFFH
Direct
addressing area
0000 0400H
Access
disallowed
0010 0000H
I/O
FFFF FFFFH
Each mode is set depending on the mode vector fetched after the INIT signal is nagated.
(Refer to MODE SETTINGS for mode setting.)
24
MB91260B Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Setting is prohibited other than that shown in the following table.
Mode Pins
Reset vector access
area
Mode name
MD2
MD1
MD0
0
0
0
Internal ROM mode vector
1
0
0
Flash serial write mode
Remarks
Internal
2. Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.
After an operation mode has been set in the mode register, the device operates in the operation mode.
The mode data is set by all reset source. User programs cannot set data to the mode register.
<Details of mode data description>
31
30
29
28
27
26
25
24
0
0
0
0
0
1
1
1
Operation mode setting bits
[bit31-24] Reserved bit
Be sure to set this bit to “00000111”.
Operation is not guaranteed when any value other than “00000111” is set.
3. Note
Mode data set in the mode vector must be placed as byte data at 0X000FFFF8.
Use the highest byte from bit 31 to bit 24 for placement as the FR family uses the big endian method for byte
endian.
31
Incorrect 0x000FFFF8
Correct
0x000FFFF8
0x000FFFFC
24 23
16 15
8 7
0
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
Reset Vector
25
MB91260B Series
■ I/O MAP
This shows the location of the various peripheral resource registers in the memory space.
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]B
XXXXXXXX
PDR1 [R/W]B
XXXXXXXX
PDR2 [R/W]B
XXXXXXXX
PDR3 [R/W]B
XXXXXXXX
Block
Port data register
Read/write attribute, Access unit
(B : byte, H : half word, W : word)
Initial value after a reset
Register name (First-column register at address 4n; second-column
register at address 4n + 2)
Location of left-most register (When using word access, the register in
column 1 is in the MSB side of the data.)
Note : Initial values of register bits are represented as follows :
“1”
: Initial Value : “ 1 ”
“0”
: Initial Value : “ 0 ”
“X”
: Initial Value : “ undefined ”
“-”
: No physical register at this location
26
MB91260B Series
Address
Register
+0
+1
+2
+3
000000H
PDR0 [R/W] B
XXXXXXXX
PDR1 [R/W] B
XXXXXXXX
PDR2 [R/W] B
XXXXXXXX
PDR3 [R/W] B
XXXXXXXX
000004H
PDR4 [R/W] B
XXXXXXXX
PDR5 [R/W] B
XXXXXXXX
PDR6 [R/W] B
----XXXX
PDR7 [R/W] B
XXXXXXXX
000008H
Port data register
00000CH
PDRC [R/W] B
XXXXXXXX
PDRD [R/W] B
------XX
PDRE [R/W] B
------XX
000010H
PDRG [R/W] B
--XXXXXX
000014H
to
00003CH
000040H
EIRR0 [R/W] B, H, W
00000000
ENIR0 [R/W] B, H, W
00000000
000044H
DICR [R/W] B, H, W
-------0
HRCL [R/W, R]
B, H, W
0--11111
Reserved
ELVR0 [R/W] B, H, W
00000000 00000000
000048H
TMRLR0 [W] H, W
XXXXXXXX XXXXXXXX
TMR0 [R] H, W
XXXXXXXX XXXXXXXX
00004CH
TMCSR0 [R/W, R] B, H, W
---00000 00000000
000050H
TMRLR1 [W] H, W
XXXXXXXX XXXXXXXX
TMR1 [R] H, W
XXXXXXXX XXXXXXXX
000054H
TMCSR1 [R/W, R] B, H, W
---00000 00000000
000058H
TMRLR2 [W] H, W
XXXXXXXX XXXXXXXX
TMR2 [R] H, W
XXXXXXXX XXXXXXXX
TMCSR2 [R/W, R] B, H, W
---00000 00000000
00005CH
000060H
000064H
000068H
00006CH
000070H
000074H
SSR0 [R/W, R] B, H, W
00001000
SIDR0 [R]/SODR0[W]
SCR0 [R/W] B, H, W SMR0 [R/W, W] B, H, W
B, H, W
00000100
00--0-0XXXXXXXX
UTIM0 [R] H / UTIMR0 [W] H
00000000 00000000
SSR1 [R/W, R] B, H, W
00001000
SSR2 [R/W, R] B, H, W
00001000
DRCL0 [W] B
--------
SIDR1 [R]/SODR1[W]
SCR1 [R/W] B, H, W
B, H, W
00000100
XXXXXXXX
UTIM1 [R] H / UTIMR1 [W] H
00000000 00000000
DRCL1 [W] B
--------
SIDR2 [R]/SODR2[W]
SCR2 [R/W] B, H, W
B, H, W
00000100
XXXXXXXX
UTIM2 [R] H / UTIMR2 [W] H
00000000 00000000
Block
DRCL2 [W] B
--------
External interrupt
(INT0 to INT7)
Delay interrupt/
Hold request
Reload
timer 0
Reload
timer 1
Reload
timer 2
UART0
UTIMC0 [R/W] B
0--00001
U-timer 0
SMR1 [R/W] B, H, W
00--0-0-
UART1
UTIMC1 [R/W] B
0--00001
U-timer 1
SMR2 [R/W] B, H, W
00--0-0-
UART2
UTIMC2 [R/W] B
0--00001
U-timer 2
(Continued)
27
MB91260B Series
Address
Register
+0
+1
000078H
ADCH0 [R/W] B, H, W
XX000000
ADMD0 [R/W] B, H, W
00001111
00007CH
ADCS0 [R/W, W] B, H, W
00000X00
000080H
ADCH1 [R/W] B, H, W
XXXX0XX0
ADMD1 [R/W] B, H, W
00001111
000084H
ADCS1 [R/W, W] B, H, W
00000X00
000088H
ADCH2 [R/W] B, H, W
XXXX0XX0
ADMD2 [R/W] B, H, W
00001111
00008CH
ADCS2 [R/W, W] B, H, W
00000X00
+2
+3
ADCD01 [R] B, H, W ADCD00 [R] B, H, W
XXXXXXXX
XXXXXXXX
AICR0 [R/W] B, H, W
00000000
ADCD11 [R] B, H, W ADCD10 [R] B, H, W
XXXXXXXX
XXXXXXXX
AICR1 [R/W] B, H, W
------00
ADCD21 [R] B, H, W ADCD20 [R] B, H, W
XXXXXXXX
XXXXXXXX
AICR2 [R/W] B, H, W
------00
000090H
OCCPBH0, OCCPBL0[W]/
OCCPH0, OCCPL0[R] H, W
00000000 00000000
OCCPBH1, OCCPBL1[W]/
OCCPH1, OCCPL1 [R] H, W
00000000 00000000
000094H
OCCPBH2, OCCPBL2[W]/
OCCPH2, OCCPL2 [R] H, W
00000000 00000000
OCCPBH3, OCCPBL3[W]/
OCCPH3, OCCPL3 [R] H, W
00000000 00000000
000098H
OCCPBH4, OCCPBL4[W]/
OCCPH4, OCCPL4 [R] H, W
00000000 00000000
OCCPBH5, OCCPBL5[W]/
OCCPH5, OCCPL5 [R] H, W
00000000 00000000
00009CH
OCSH1 [R/W] B, H, W
X1100000
OCSL0 [R/W] B, H, W
00001100
OCSH3 [R/W]
B, H, W
X1100000
OCSL2 [R/W]
B, H, W
00001100
0000A0H
OCSH5 [R/W] B, H, W
X1100000
OCSL4 [R/W] B, H, W
00001100
OCMOD [R/W]
B, H, W
XX000000
0000A4H
0000A8H
CPCLRBH, CPCLRBL[W]/
CPCLRH, CPCLRL[R] H, W
11111111 11111111
TCCSH [R/W] B, H, W
00000000
TCCSL [R/W] B, H, W
01000000
TCDTH, TCDTL [R/W] H, W
00000000 00000000
ADTRGC [R/W]
B, H, W
XXXX0000
0000ACH
IPCPH0, IPCPL0 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH1, IPCPL1 [R] H, W
XXXXXXXX XXXXXXXX
0000B0H
IPCPH2, IPCPL2 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH3, IPCPL3 [R] H, W
XXXXXXXX XXXXXXXX
0000B4H
PICSH01 [W] B, H, W
000000--
PICSL01 [R/W] B, H, W
00000000
0000B8H
EIRR1 [R/W] B, H, W
------00
ENIR1 [R/W] B, H, W
------00
ICSH23 [R] B, H, W
XXXXXX00
Block
A/D
converter 0/
AICR0
A/D
converter 1/
AICR1
A/D
converter 2/
AICR2
OCU
free-run
timer
ICU
ICSL23 [R/W]
B, H, W
00000000
ELVR1 [R/W] B, H, W
-------- ----0000
External interrupt
(INT8, INT9)
(Continued)
28
MB91260B Series
Address
Register
+0
+1
0000BCH
TMRRH0, TMRRL0 [R/W] H, W
XXXXXXXX XXXXXXXX
0000C0H
TMRRH2, TMRRL2 [R/W] H, W
XXXXXXXX XXXXXXXX
+2
Block
+3
TMRRH1, TMRRL1 [R/W] H, W
XXXXXXXX XXXXXXXX
Waveform
generator
0000C4H
DTCR0 [R/W] B, H, W
00000000
DTCR1 [R/W] B, H, W
00000000
DTCR2 [R/W] B, H, W
00000000
0000C8H
SIGCR1 [R/W] B, H, W
10000000
SIGCR2 [R/W] B, H, W
XXXXXXX1
0000CCH
ADCOMP0 [R/W] H, W
00000000 00000000
0000D0H
ADCOMP2 [R/W] H, W
00000000 00000000
0000D4H
to
0000DCH
ADCOMP1 [R/W] H, W
00000000 00000000
ADCOMPC [R/W] B, H, W
XXXXX000
Reserved
0000E0H
PWCSR0 [R/W, R] B, H, W
00000000 00000000
PWCR0 [R] H, W
00000000 00000000
0000E4H
PWCSR1 [R/W, R] B, H, W
00000000 00000000
PWCR1 [R] H, W
00000000 00000000
0000E8H
PDIVR0 [R/W] B, H, W
XXXXX000
0000ECH
to
000FCH
PWC
PDIVR1 [R/W] B, H, W
XXXXX000
Reserved
000100H
PRLH0 [R/W] B, H, W
XXXXXXXX
PRLL0 [R/W] B, H, W
XXXXXXXX
PRLH1 [R/W] B, H, W
XXXXXXXX
PRLL1 [R/W] B, H, W
XXXXXXXX
000104H
PRLH2 [R/W] B, H, W
XXXXXXXX
PRLL2 [R/W] B, H, W
XXXXXXXX
PRLH3 [R/W] B, H, W
XXXXXXXX
PRLL3 [R/W] B, H, W
XXXXXXXX
000108H
PPGC0 [R/W] B, H, W
0000000X
PPGC1 [R/W] B, H, W
0000000X
PPGC2 [R/W] B, H, W
0000000X
PPGC3 [R/W] B, H, W
0000000X
00010CH
PRLH4 [R/W] B, H, W
XXXXXXXX
PRLL4 [R/W] B, H, W
XXXXXXXX
PRLH5 [R/W] B, H, W
XXXXXXXX
PRLL5 [R/W] B, H, W
XXXXXXXX
000110H
PRLH6 [R/W] B, H, W
XXXXXXXX
PRLL6 [R/W] B, H, W
XXXXXXXX
PRLH7 [R/W] B, H, W
XXXXXXXX
PRLL7 [R/W] B, H, W
XXXXXXXX
000114H
PPGC4 [R/W] B, H, W
0000000X
PPGC5 [R/W] B, H, W
0000000X
PPGC6 [R/W] B, H,
W0000000X
PPGC7 [R/W] B, H, W
0000000X
000118H
PRLH8 [R/W] B, H, W
XXXXXXXX
PRLL8 [R/W] B, H, W
XXXXXXXX
PRLH9 [R/W] B, H, W
XXXXXXXX
PRLL9 [R/W] B, H, W
XXXXXXXX
00011CH
PRLH10 [R/W] B, H, W PRLL10 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
PRLH11 [R/W]
B, H, W
XXXXXXXX
PRLL11 [R/W] B, H, W
XXXXXXXX
000120H
PPGC8 [R/W] B, H, W
0000000X
PPGC10 [R/W] B, H, W
0000000X
PPGC11 [R/W] B, H, W
0000000X
PPGC9 [R/W] B, H, W
0000000X
A/D
COMP
PPG
(Continued)
29
MB91260B Series
Address
Register
+0
+1
+2
+3
000124H
PRLH12 [R/W] B, H, W PRLL12 [R/W] B, H, W PRLH13 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PRLL13 [R/W] B, H, W
XXXXXXXX
000128H
PRLH14 [R/W] B, H, W PRLL14 [R/W] B, H, W PRLH15 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PRLL15 [R/W] B, H, W
XXXXXXXX
00012CH
PPGC12 [R/W] B, H, W PPGC13 [R/W] B, H, W PPGC14 [R/W] B, H, W PPGC15 [R/W] B, H, W
0000000X
0000000X
0000000X
0000000X
000130H
TRG [R/W] B, H, W
00000000 00000000
GATEC [R/W] B, H, W
XXXXXX00
000134H
REVC [R/W] B, H, W
00000000 00000000
Block
PPG
000138H
to
0001FCH
000200H
DMACA0 [R/W] B, H, W *1
00000000 00000000 00000000 00000000
000204H
DMACB0 [R/W] B, H, W
00000000 00000000 00000000 00000000
000208H
DMACA1 [R/W] B, H, W*1
00000000 00000000 00000000 00000000
00020CH
DMACB1 [R/W] B, H, W
00000000 00000000 00000000 00000000
000210H
DMACA2 [R/W] B, H, W *1
00000000 00000000 00000000 00000000
000214H
DMACB2 [R/W] B, H, W
00000000 00000000 00000000 00000000
000218H
DMACA3 [R/W] B, H, W *1
00000000 00000000 00000000 00000000
00021CH
DMACB3 [R/W] B, H, W
00000000 00000000 00000000 00000000
000220H
DMACA4 [R/W] B, H, W *1
00000000 00000000 00000000 00000000
000224H
DMACB4 [R/W] B, H, W
00000000 00000000 00000000 00000000
000228H
to
00023CH
Reserved
000240H
DMACR [R/W] B
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
000244H
to
000398H
Reserved
Reserved
DMAC
(Continued)
30
MB91260B Series
Address
Register
+0
+1
+2
+3
00039CH
0003A0H
DSP-PC [R/W]
XXXXXXXX
DSP-CSR [R/W, R, W]
00000000
DSP-LY [R/W]
XXXXXXXX XXXXXXXX
0003A4H
DSP-OT0 [R]
XXXXXXXX XXXXXXXX
DSP-OT1 [R]
XXXXXXXX XXXXXXXX
0003A8H
DSP-OT2 [R]
XXXXXXXX XXXXXXXX
DSP-OT3 [R]
XXXXXXXX XXXXXXXX
0003ACH
0003B0H
DSP-OT4 [R]
XXXXXXXX XXXXXXXX
DSP-OT5 [R]
XXXXXXXX XXXXXXXX
0003B4H
DSP-OT6 [R]
XXXXXXXX XXXXXXXX
DSP-OT7 [R]
XXXXXXXX XXXXXXXX
0003B8H
to
0003ECH
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Sum of
products
Reserved
Bit search
000400H
DDR0 [R/W] B
00000000
DDR1 [R/W] B
00000000
DDR2 [R/W] B
00000000
DDR3 [R/W] B
00000000
000404H
DDR4 [R/W] B
00000000
DDR5 [R/W] B
00000000
DDR6 [R/W] B
----0000
DDR7 [R/W] B
00000000
000408H
00040CH
DDRC [R/W] B
00000000
DDRD [R/W] B
------00
DDRE [R/W] B
------00
000410H
DDRG [R/W] B
--000000
000414H
to
00041CH
Block
Data
direction
register
Reserved
000420H
PFR0 [R/W] B
00000000
PFR1 [R/W] B
-0000000
PFR2 [R/W] B
--00-00-
000424H
PFR7 [R/W] B
------00
000428H
00042CH
000430H
PFRG [R/W] B
--00--0-
Port
function
register
(Continued)
31
MB91260B Series
Address
Register
+0
+1
+2
+3
Block
000434H
to
00043CH
000440H
ICR00 [R/W, R] B, H, W ICR01 [R/W, R] B, H, W ICR02 [R/W, R] B, H, W ICR03 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000444H
ICR04 [R/W, R] B, H, W ICR05 [R/W, R] B, H, W ICR06 [R/W, R] B, H, W ICR07 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000448H
ICR08 [R/W, R] B, H, W ICR09 [R/W, R] B, H, W ICR10 [R/W, R] B, H, W ICR11 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
00044CH
ICR12 [R/W, R] B, H, W ICR13 [R/W, R] B, H, W ICR14 [R/W, R] B, H, W ICR15 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000450H
ICR16 [R/W, R] B, H, W ICR17 [R/W, R] B, H, W ICR18 [R/W, R] B, H, W ICR19 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000454H
ICR20 [R/W, R] B, H, W ICR21 [R/W, R] B, H, W ICR22 [R/W, R] B, H, W ICR23 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000458H
ICR24 [R/W, R] B, H, W ICR25 [R/W, R] B, H, W ICR26 [R/W, R] B, H, W ICR27 [R/W, R] B, H, W controller
----1111
----1111
----1111
----1111
00045CH
ICR28 [R/W, R] B, H, W ICR29 [R/W, R] B, H, W ICR30 [R/W, R] B, H, W ICR31 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000460H
ICR32 [R/W, R] B, H, W ICR33 [R/W, R] B, H, W ICR34 [R/W, R] B, H, W ICR35 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000464H
ICR36 [R/W, R] B, H, W ICR37 [R/W, R] B, H, W ICR38 [R/W, R] B, H, W ICR39 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000468H
ICR40 [R/W, R] B, H, W ICR41 [R/W, R] B, H, W ICR42 [R/W, R] B, H, W ICR43 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
00046CH
ICR44 [R/W, R] B, H, W ICR45 [R/W, R] B, H, W ICR46 [R/W, R] B, H, W ICR47 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000470H
to
00047CH
Reserved
Reserved
000480H
RSRR [R/W] B, H, W
10000000
STCR [R/W] B, H, W
00110011
TBCR [R/W] B, H, W
00XXXX00
CTBR [W] B, H, W
XXXXXXXX
000484H
CLKR [R/W] B, H, W
00000000
WPR [W] B, H, W
XXXXXXXX
DIVR0 [R/W] B, H, W
00000011
DIVR1 [R/W] B, H, W
00000000
000488H
to
0005FCH
Interrupt
Clock
control
unit
Reserved
000600H
PCR0 [R/W] B
00000000
PCR1 [R/W] B
00000000
PCR2 [R/W] B
00000000
PCR3 [R/W] B
00------
000604H
PCR4 [R/W] B
00000000
PCR5 [R/W] B
00000000
PCR6 [R/W] B
----0000
PCR7 [R/W] B
00000000
000608H
00060CH
Pull-up
Control
(Continued)
32
MB91260B Series
Address
000610H
Register
+0
+1
+2
+3
PCRG [R/W] B
--000000
000614H
to
000FFCH
001000H
DMASA0 [R/W] W
00000000 00000000 00000000 00000000
001004H
DMADA0 [R/W] W
00000000 00000000 00000000 00000000
001008H
DMASA1 [R/W] W
00000000 00000000 00000000 00000000
00100CH
DMADA1 [R/W] W
00000000 00000000 00000000 00000000
001010H
DMASA2 [R/W] W
00000000 00000000 00000000 00000000
001014H
DMADA2 [R/W] W
00000000 00000000 00000000 00000000
001018H
DMASA3 [R/W] W
00000000 00000000 00000000 00000000
00101CH
DMADA3 [R/W] W
00000000 00000000 00000000 00000000
001020H
DMASA4 [R/W] W
00000000 00000000 00000000 00000000
001024H
DMADA4 [R/W] W
00000000 00000000 00000000 00000000
001028H
to
006FFCH
DMAC
Reserved
FLCR [R/W]
0110X000
007004H
FLWC [R/W]
00000011*2
007008H
00700CH
007010H
Pull-up
Control
Reserved
007000H
007014H
to
00BFFCH
Block
FLASH
Reserved
(Continued)
33
MB91260B Series
(Continued)
Address
Register
+0
+1
+2
00C000H
to
00C07CH
X-RAM (coefficient RAM) [R/W]
64 × 16 bit
00C080H
to
00C0FCH
Y-RAM (variable RAM) [R/W]
64 × 16 bit
00C100H
to
00C2FCH
I-RAM (instruction RAM) [R/W]
256 × 16 bit
00C300H
to
00FFFCH
+3
*1 : The lower 16 bits (DTC[15: 0]) of DMACA0 to DMACA4 cannot be accessed in bytes.
*2 : The initial value of 1FLWC (7004H) is “00010011B” on EVA tool.
Writing “00000011B” on the evaluation model has no effect on its operation.
Notes : • Do not excute Read Modify Write instructions on registers having a write-only bit.
• Data is undefined in reseved or (-) area.
34
Block
Sum of
products
Reserved
MB91260B Series
■ INTERRUPT VECTOR
Interrupt number
10
16
Interrupt
level
Reset
0
00
3FCH
000FFFFCH
Mode vector
1
01
3F8H
000FFFF8H
System reserved
2
02
3F4H
000FFFF4H
System reserved
3
03
3F0H
000FFFF0H
System reserved
4
04
3ECH
000FFFECH
System reserved
5
05
3E8H
000FFFE8H
System reserved
6
06
3E4H
000FFFE4H
Coprocessor absent trap
7
07
3E0H
000FFFE0H
Coprocessor error trap
8
08
3DCH
000FFFDCH
INTE instruction
9
09
3D8H
000FFFD8H
Instruction break exception
10
0A
3D4H
000FFFD4H
Operand break trap
11
0B
3D0H
000FFFD0H
Step trace trap
12
0C
3CCH
000FFFCCH
NMI request (tool)
13
0D
3C8H
000FFFC8H
Undefined instruction exception
14
0E
3C4H
000FFFC4H
NMI request
15
0F
15 (FH) fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
6
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
7
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1
25
19
ICR09
398H
000FFF98H
9
Reload timer 2
26
1A
ICR10
394H
000FFF94H
10
UART0(Reception completed)
27
1B
ICR11
390H
000FFF90H
0
UART0 (RX completed)
28
1C
ICR12
38CH
000FFF8CH
3
DTTI
29
1D
ICR13
388H
000FFF88H
DMAC0 (end, error)
30
1E
ICR14
384H
000FFF84H
DMAC1 (end, error)
31
1F
ICR15
380H
000FFF80H
DMAC2/3/4 (end, error)
32
20
ICR16
37CH
000FFF7CH
Interrupt source
Offset
TBR default
address
RN
(Continued)
35
MB91260B Series
Interrupt number
10
16
Interrupt
level
Offset
TBR default
address
RN
UART1(Reception completed)
33
21
ICR17
378H
000FFF78H
1
UART1 (RX completed)
34
22
ICR18
374H
000FFF74H
4
UART2 (Reception completed)
35
23
ICR19
370H
000FFF70H
2
UART2 (RX completed)
36
24
ICR20
36CH
000FFF6CH
5
SUM of products macro
37
25
ICR21
368H
000FFF68H
PPG0
38
26
ICR22
364H
000FFF64H
PPG1
39
27
ICR23
360H
000FFF60H
PPG2/3
40
28
ICR24
35CH
000FFF5CH
PPG4/5/6/7
41
29
ICR25
358H
000FFF58H
PPG8/9/10/11/12/13/14/15
42
2A
ICR26
354H
000FFF54H
External interrupt 8/9
43
2B
ICR27
350H
000FFF50H
Waveform0 (under flow)
44
2C
ICR28
34CH
000FFF4CH
Waveform1 (under flow)
45
2D
ICR29
348H
000FFF48H
Waveform2 (under flow)
46
2E
ICR30
344H
000FFF44H
Timebase timer overflow
47
2F
ICR31
340H
000FFF40H
Free-run timer (Compare clear)
48
30
ICR32
33CH
000FFF3CH
Free-run timer (zero detection)
49
31
ICR33
338H
000FFF38H
A/D0
50
32
ICR34
334H
000FFF34H
A/D1
51
33
ICR35
330H
000FFF30H
A/D2
52
34
ICR36
32CH
000FFF2CH
PWC0 (measurment completed)
53
35
ICR37
328H
000FFF28H
PWC1 (measurment completed)
54
36
ICR38
324H
000FFF24H
PWC0 (overflow)
55
37
ICR39
320H
000FFF20H
PWC1 (overflow)
56
38
ICR40
31CH
000FFF1CH
ICU0 (capture)
57
39
ICR41
318H
000FFF18H
ICU1 (capture)
58
3A
ICR42
314H
000FFF14H
ICU2/3 (capture)
59
3B
ICR43
310H
000FFF10H
OCU0/1 (match)
60
3C
ICR44
30CH
000FFF0CH
OCU2/3 (match)
61
3D
ICR45
308H
000FFF08H
OCU4/5 (match)
62
3E
ICR46
304H
000FFF04H
Delay interrupt source bit
63
3F
ICR47
300H
000FFF00H
System reserved (Used by REALOS)
64
40
2FCH
000FFEFCH
System reserved (Used by REALOS)
65
41
2F8H
000FFEF8H
Interrupt source
(Continued)
36
MB91260B Series
(Continued)
Interrupt number
10
16
Interrupt
level
Offset
TBR default
address
RN
System reserved
66
42
2F4H
000FFEF4H
System reserved
67
43
2F0H
000FFEF0H
System reserved
68
44
2ECH
000FFEECH
System reserved
69
45
2E8H
000FFEE8H
System reserved
70
46
2E4H
000FFEE4H
System reserved
71
47
2E0H
000FFEE0H
System reserved
72
48
2DCH
000FFEDCH
System reserved
73
49
2D8H
000FFED8H
System reserved
74
4A
2D4H
000FFED4H
System reserved
75
4B
2D0H
000FFED0H
System reserved
76
4C
2CCH
000FFECCH
System reserved
77
4D
2C8H
000FFEC8H
System reserved
78
4E
2C4H
000FFEC4H
System reserved
79
4F
2C0H
000FFEC0H
Used by INT instruction
80
to
255
50
to
FF
2BCH
to
000H
000FFEBCH
to
000FFC00H
Interrupt source
37
MB91260B Series
■ PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows.
• Input enabled
• Indicates that the input function can be used.
• Input 0 fixed
• Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released.
• Output Hi-Z
• Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving.
• Output is maintained.
• Indicates the output in the output state existing immediately before this mode is established.
• If the device enters this mode with an internal output peripheral operating or while serving as an output port,
the output is performed by the internal peripheral or the port output is maintained, respectively.
• State existing immediately before is maintained.
• When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.
38
MB91260B Series
• List of pin status (single chip mode)
Pin no.
Pin name Function
QFP
LQFP
1
99
P23
SIN1
2
100
P24
SOT1
3
1
P25
SCK1
4, 5
2, 3
P26, P27
INT6, INT7
6 to 9
4 to 7
P50 to P53
Ports
10
8
P54
INT0
11
9
P55
INT1
12
10
P56
INT2
13
11
P57
INT3
14
12
PG0
CKI/INT4
15
13
PG1
16
14
PG2
20
18
PG3
21
19
PG4
SOT2
22
20
PG5
SCK2
23 to 30 21 to 28 P40 to P47
INIT = H*2
At Stop mode
Hi-Z = 0
Hi-Z = 1
Retention
Retention
of the
of the
Output Hi-Z/
immediately immediately Input 0 fixed
prior state
prior state
Input
enabled
Input
enabled
Input
enabled
Retention
Retention
of the
of the
Output Hi-Z/
immediately immediately Input 0 fixed
prior state
prior state
Input
enabled
Input
enabled
Input
enabled
Ports
29, 30
PE1, PE0
AN11,
AN10
38, 39
36, 37
PD1, PD0
AN9, AN8
PC7 to
PC0
AN7 to AN0
51 to 56 49 to 54 P30 to P35
INIT = L*1
At sleep
mode
PPG0/INT5 Output Hi-Z/ Output Hi-Z/
Input
Input
Ports
disabled
disabled
SIN2
31, 32
41 to 48 39 to 46
At initializing
Retention
Retention
of the
of the
Output Hi-Z/
immediately immediately Input 0 fixed
prior state
prior state
RTO0 to
RTO5
57, 58
55, 56
P36, P37
IC0, IC1
59, 60
57, 58
P60, P61
IC2, IC3
61, 62
59, 60
P62, P63
INT8, INT9
Input
enabled
Input
enabled
Input
enabled
(Continued)
39
MB91260B Series
(Continued)
P : Selection of general purpose port, F : Selection of specified function
At initializing
Pin no.
At sleep
Pin
Function
mode
name
QFP LQFP
INIT = L*1
INIT = H*2
63, 64 61, 62 P70, P71
At Stop mode
Hi-Z = 0
TOT1,
TOT2
65
63
P72
DTTI
66
64
P73
PWI0
69
67
P74
PWI1
70
68
P75
ADTG0
71
69
P76
ADTG1
72
70
P77
ADTG2
73
71
NMI
NMI
78
76
P00
PPG1
79
77
P01
PPG2
80
78
P02
PPG3
81
79
P03
PPG4
82
80
P04
PPG5
83
81
P05
PPG6
84
82
P06
PPG7
85
83
P07
PPG8
86
84
P10
PPG9
87
85
P11
PPG10
88
86
P12
PPG11
89
87
P13
PPG12
90
88
P14
PPG13
91
89
P15
PPG14
96
94
P16
PPG15
97
95
P17
Ports
98
96
P20
SIN0
99
97
P21
SOT0
100
98
P22
SCK0
Retention
Retention
Output Hi-Z/ Output Hi-Z/
of the
of the
Output Hi-Z/
input disabled input disabled immediately immediately Input 0 fixed
prior state
prior state
Input enabled Input enabled
Input
enabled
Input
enabled
Input
enabled
Retention
Retention
Output Hi-Z/
output Hi-Z/
of the
of the
Ouptut Hi-Z/
input disabled input disabled immediately immediately input 0 fixed
prior state
prior state
*1 : INIT = L : Indicates the pin status with INIT remaining at the “L” level.
*2 : INIT = H : Indicates the pin status existing immediately after INIT transition from “L” to “H” level.
40
Hi-Z = 1
MB91260B Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
(VSS = AVSS = 0 V)
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.5
VSS + 6.0
V
Analog power supply voltage
AVCC
VSS − 0.5
VSS + 6.0
V
*1
Analog reference voltage
AVRH
VSS − 0.5
VSS + 6.0
V
*1
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Analog pin input voltage
VIA
VSS − 0.3
AVcc + 0.3
V
Output voltage
VO
VSS − 0.3
VCC + 0.3
V
L level maximum output current
IOL
10
mA
*2
L level average output current
IOLAV
8
mA
*3
L level total maximum output
current
ΣIOL
100
mA
ΣIOLAV
50
mA
*4
IOH
− 10
mA
*2
H level average output current
IOHAV
−4
mA
*3
H level total maximum output
current
ΣIOH
− 50
mA
ΣIOHAV
− 20
mA
Power supply voltage
L level total average output
current
H level maximum output
current
H level total average output
current
600
Power consumption
PD
600
FLASH product
mW
Storage temperature
− 40
+ 105
°C
MASK product (at single chip
operating)
− 40
+ 85
°C
FLASH product (at single chip
operating)
− 55
125
°C
Ta
Tstg
MASK product Ta ≤ + 85 °C
MASK product Ta ≤ + 105 °C *5
360
Operating temperature
*4
*1 : Be careful not to exceed VCC + 0.3 V, for example, when the power is turned on.
Be careful not to let AVCC exceed VCC, for example, when the power is turned on.
*2 : The maximum output current is the peak value for a single pin.
*3 : The average output current is the average current for a single pin over a period of 100 ms.
*4 : The total average output current is the average current for all pins over a period of 100 ms.
*5 : For use at Ta = +105 °C, lower the operating frequency to reduce power consumption.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
41
MB91260B Series
2. Recommended Operating Conditions
Parameter
Symbol
(Vss = AVss = 0 V)
Value
Min
Max
Unit
Remarks
Power supply voltage
VCC
4.0
5.5
V
Analog power supply
voltage
AVCC
VSS + 4.0
VSS + 5.5
V
AVRH0
AVSS
AVCC
V
For A/D converter 0
AVRH1
AVSS
AVCC
V
For A/D converter 1
AVRH2
AVSS
AVCC
V
For A/D converter 2
− 40
+ 105
°C
MASK product (at single chip
operation)
− 40
+ 85
°C
FLASH product (at single chip
operation)
Analog reference voltage
Operating temperature
Ta
At normal operating
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
42
MB91260B Series
3. DC Characteristics
Parameter
"H" level input
voltage
Input Low
Voltage
"H" level output
voltage
Output Low
Voltage
Input leak current
Sym
bol
Pin
Conditions
VIH
Other than hysteresis input pin
VIHS
Unit Remarks
Typ
Max
0.8 × Vcc
Vcc
V
Hysteresis input
pin
Vcc − 0.4
Vcc
V
VIL
Other than hysteresis input pin
Vss
0.2 × Vcc
V
VILS
Hysteresis input
pin
Vss
Vss + 0.4
V
VOH
Other than port 30 VCC = 5.0 V,
to 35
IOH = 4.0 mA
Vcc − 0.5
V
VCC = 5.0 V,
IOH = 8.0 mA
Vcc − 0.7
V
Other than port 30 VCC = 5.0 V,
to 35
IOL = 4.0 mA
0.4
V
VCC = 5.0 V,
IOL = 12 mA
0.6
V
VCC = 5.0 V,
VSS ≤ VI ≤ VCC
−5
5
µA
50
kΩ
VCC
VCC = 5.0 V, 33 MHz
90
100
mA
ICCS VCC
VCC = 5.0 V, 33 MHz
60
80
mA At SLEEP
ICCH VCC
VCC = 5.0 V,
Ta = + 25 °C
300
µA
10
pF
VOH2 Port 30 to 35
VOL
VOL2 Port 30 to 35
ILI
ICC
Input
capacitance
Value
Min
Pullup resistance RPULL
Power supply
current
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
CIN
INIT,
Pull-up pin
Other than VCC,
VSS, AVCC, AVSS,
AVRH0, 1, 2
At STOP
43
MB91260B Series
4. FLASH MEMORY write/erase characteristics
Parameter
Conditions
Sector erase time
Unit
Remarks
Min
Typ
Max
Ta = + 25 °C,
Vcc = 5.0 V
1
15
s
Not including time for internal
writing before deletion.
Chip erase time
Ta = + 25 °C,
Vcc = 5.0 V
10
s
Not including time for internal
writing before deletion.
Byte write time
Ta = + 25 °C,
Vcc = 5.0 V
8
3,600
µs
Not including system-level
overhead time.
Chip write time
Ta = + 25 °C,
Vcc = 5.0 V
2.1
s
Not including system-level
overhead time.
10,000
Cycle
Erase/write cycle
44
Value
MB91260B Series
5. AC Characteristics
(1) Clock Timing Ratings
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Sym
bol
Pin
fC
X0
X1
Clock cycle time
tC
X0
X1
Internal operating
clock frequency
fCP
Parameter
Clock frequency
Internal operating
clock cycle time
fCPP
tCP
tCPP
Conditions
Value
Unit
Remarks
Min
Typ
Max
3.6
12
MHz
83.3
278
ns
When 4.125 MHz is 2.06*
input as the X0
2.06*
clock frequency and
×8 multiplication is 30.3
set for the PLL of
the oscillator circuit. 30.3
33
MHz CPU
33
MHz Peripheral
485*
ns
CPU
485*
ns
Peripheral
For using the PLL within
the self-oscillation enabled
range, set the multiplier for
the internal clock not to let
the operating frequency
exceed 33 MHz.
* : The values assume a gear cycle of 1/16.
• Conditions for measuring the clock timing ratings
tC
0.8 VCC
0.2 VCC
Output pin
C = 50 pF
PWL
PWH
tCF
tCR
45
MB91260B Series
• Operation Assurance Range
Power supply
VCC (V)
5.5
4.0
0 0.25
33
fCP / fCPP
(MHz)
Internal clock
• Internal clock setting range
(MHz)
CPU (CLKB) :
Internal clock
33
Peripheral (CLKP) :
16.5
Oscillation input clock fC = 4.192 MHz
(PLL multiplied by 8)
4.125
8:8
4:4
1:1
CPU : Divided ratio for
peripherals.
Notes : • Oscillation stabilization time of PLL > 600 µs
• The internal clock gear setting should be within the value shown in clock timing ratings table.
46
MB91260B Series
(2) Reset Input
Parameter
Init input time
(at power-on and STOP mode)
Init input time
(other than the above)
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Symbol
tINTL
Pin
INIT
Value
Conditions
Unit
Min
Max
Oscillation time of
oscillator + tC × 10
ns
tC × 10
ns
Remarks
tINTL
INIT
0.2 VCC
47
MB91260B Series
(3) UART Timing
Parameter
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Symbol
Pin
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
Conditions
Unit Remarks
Min
Max
SCK0 to SCK2
8 tCYCP
ns
tSLOV
SCK0 to SCK2,
SOT0 to SOT2
− 80
80
ns
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK2,
SIN0 to SIN2
100
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to SCK2,
SIN0 to SIN2
60
ns
Serial clock H pulse width
tSHSL
SCK0 to SCK2
4 tCYCP
ns
Serial clock L pulse width
tSLSH
SCK0 to SCK2
4 tCYCP
ns
SCK ↓ → SOT delay time
tSLOV
SCK0 to SCK2,
SOT0 to SOT2
150
ns
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK2,
SIN0 to SIN2
60
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to SCK2,
SIN0 to SIN2
60
ns
Internal shift
clock mode
External
shift clock
mode
Notes : • There are the AC ratings for CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
48
Value
MB91260B Series
• Internal shift clock mode
tSCYC
SCK0 to SCK2
VOH
VOL
VOL
tSLOV
VOH
VOL
SOT0 to SOT2
tIVSH
tSHIX
VOH
VOL
SIN0 to SIN2
VOH
VOL
• External shift clock mode
tSLSH
tSHSL
VOH
SCK0 to SCK2
VOL
VOL
VOL
tSLOV
SOT0 to SOT2
VOH
VOL
tIVSH
SIN0 to SIN2
VOH
VOL
tSHIX
VOH
VOL
49
MB91260B Series
(4) Free-run Timer Clock, PWC Input and Reload Timer Trigger Timing
Parameter
Symbol
Pin
Conditions
Input pulse width
tTIWH
tTIWL
CKI
PWI0, PWI1
TIN0 to TIN2
Value
Min
Max
4 tCYCP
Note : tCYCP indicates the peripheral clock cycle time.
tTIWH
50
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
tTIWL
Unit
ns
Remarks
MB91260B Series
(5) Trigger Input Timing
Parameter
Input capture
trigger input
A/D activation trigger input
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Symbol
Pin
Conditions
tINP
IC0 to IC3
tATGX
ADTG0 to
ADTG2
Value
Unit
Min
Max
5 tCYCP
ns
5 tCYCP
ns
Remarks
Note : tCYCP indicates the peripheral clock cycle time.
tATGX, tINP
IC0 to IC3
ADTG0 to ADTG2
51
MB91260B Series
6. Electrical Characteristics for the A/D Converter
Symbol
Pin
Resolution
Total error*1
Parameter
(VCC = AVcc = 5.0 V, VSS = AVSS = 0 V)
Value
Unit
Min
Typ
Max
10
bit
−4
4
LSB
Linearity error*
− 3.5
3.5
LSB
Differential linearity
error*1
−3
3
LSB
Zero transition voltage*1
VOT
AN0 to
AN11
Full transition voltage*1
VFST
AN0 to
AN11
AVRH −
5.5
AVRH −
1.5
AVRH +
2.5
LSB
Conversion time
1.2*2
µS
Analog port
Input current
IAIN
AN0 to
AN11
10
µA
Analog input voltage
VAIN
AN0 to
AN11
AVss
AVRH
V
Reference voltage
AVRHn
AVss
AVcc
V
Analog power supply
current
(analog + digital)
IA
2
100
1
100
µA
reference power supply
current
(between AVRH and
AVSS)
IAH*3
Remarks
At AVRHn*4 = 5.0 V
AVss − 3.5 AVss + 0.5 AVss + 4.5 LSB
AVcc
IR
AVRHn
IRH*3
mA Per 1 unit
µA
Per 1 unit
Per 1 unit
mA AVRHn*4 = 5.0 V,
at AVss = 0 V
Analog input capacitance
10
pF
Inter-channel disparity
AN0 to
AN11
4
LSB
per 1 unit
at STOP
*1 : Measured in the CPU sleep state
*2 : Vcc = AVcc = 5.0 V, machine clock at 33 MHz
*3 : The current when the CPU is in stop mode and the A/D converter is not operating (at Vcc = AVcc = AVRHn = 5.0 V)
*4: AVRHn = AVRH0, AVRH1, AVRH2
Note : The above does not guarantee the inter-unit accuracy.
Set the output impedance of the external circuit ≤ 2 kΩ.
52
MB91260B Series
Definition of A/D Converter Terms
• Resolution : Analog variation that is recognized by an A/D converter.
• Linearity error : Zero transition point (00 0000 0000 ←→ 00 0000 0001) and full-scale transition point.
Difference between the line connected (11 1111 1110 ←→ 11 1111 1111) and actual conversion characteristics.
• Differential linearity error : Deviation of input voltage, that is required for changing output code by 1 LSB, from
an ideal value.
• Total error : This error indicates the difference between actual and ideal values, including the zero transition
error/full-scale transition error/linearity error.
Total error
3FF
Digital output
1.5 LSB'
Actual conversion
characteristics
3FE
3FD
{1 LSB' (N − 1) + 0.5 LSB'}
004
VNT
(measurement value)
003
Actual conversion
characteristics
002
Ideal characteristics
001
0.5 LSB'
AVSS
AVRH
Analog input
1LSB’
(Ideal value)
=
AVRH − AVSS
1024
[V] Total error of digital output N
=
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1 LSB’
VOT’
(Ideal value)
= AVSS + 0.5 LSB’ [V]
VFST’
(Ideal value)
= AVRH − 1.5 LSB’ [V] VNT : A voltage at which digital output transitions from (N + 1) to N.
(Continued)
53
MB91260B Series
(Continued)
Linearity error
3FF
Actual conversion
characteristics
{1 LSB (N − 1) + VOT}
3FD
Actual conversion
characteristics
N+1
Ideal
characteristics
VFST
(measurement
value)
004
VNT
003
(measurement value)
002
Actual conversion
characteristics
Ideal characteristics
Digital output
3FE
Digital output
Differential linear error
N
N−1
VFST
(measurement
value)
VNT
(measurement value)
N−2
001
Actual conversion
characteristics
V0T (measurement Value)
AVSS
AVSS
AVRH
AVRH
Analog input
Analog input
Linearity error in digital output N =
Differential linearity error in digital output
=
N
1 LSB
=
VNT − { 1 LSB × (N − 1) + VOT }
1 LSB
V (N + 1) T − VNT
1 LSB
VFST − VOT
1022
[V]
VOT : A voltage at which digital output transitions from 000H to 001H.
VFST : A voltage at which digital output transitions from 3FEH to 3FFH .
54
−1
[LSB]
[LSB]
MB91260B Series
■ EXAMPLE CHARACTERISTICS
“L” Level Output Voltage vs.
“H” Level Output Voltage vs.
Power Supply Voltage
Power Supply Voltage
6
400
5
350
300
VOL (mV)
VOH (V)
4
3
2
250
200
150
1
100
50
0
4.0
4.5
5.0
5.5
0
4.0
VCC (V)
4.5
5.0
5.5
VCC (V)
Pull-up Resistor vs. Power Supply Voltage
Power Supply Current vs. Power Supply Voltage
80
100
70
90
80
70
ICC (mA)
50
40
30
60
50
40
30
20
20
10
10
0
4.0
4.5
5.0
0
4.0
5.5
VCC (V)
4.5
5.0
5.5
VCC (V)
Power Supply Current vs. Internal Operation Frequency (MB91263)
100
90
80
70
ICC (mA)
R (kΩ)
60
60
4.0 V
4.5 V
5.0 V
5.5 V
50
40
30
20
10
0
15
20
25
30
35
Internal operation frequency [MHz]
(Continued)
55
MB91260B Series
(Continued)
Power Supply Current (at sleep) vs.
Power Supply Voltageage
Power Supply Current (at stop) vs.
Power Supply Voltage
100
80
90
70
80
70
ICCH (µA)
ICCS (mA)
60
50
40
60
50
40
30
30
20
20
10
10
0
4.0
4.5
5.0
0
4.0
5.5
4.5
VCC (V)
2
1.0
1.5
0.8
1
5.5
A/D Conversion Block Per 1 Unit (33 MHz)
Reference Voltage Supplying Current vs.
Power Supply Voltage
IR (mA)
IA (mA)
A/D Conversion Block Per 1 Unit (33 MHz)
Analog Power Supply Current vs.
Power Supply Voltage
5.0
VCC (V)
0.6
0.4
0.5
0.2
0
4.0
4.5
5.0
VCC (V)
56
5.5
0.0
4.0
4.5
5.0
VCC (V)
5.5
MB91260B Series
■ ORDERING INFORMATION
Part number
MB91F264BPF-G
MB91F264BPF-G-E1
MB91F264BPFV-G
MB91F264BPFV-G-E1
MB91263BPF-G-xxx-BND
MB91263BPF-G-xxx-BNDE1
MB91263BPFV-G-xxx-BND
MB91263BPFV-G-xxx-BNDE1
Package
Remarks
100-pin plastic QFP
(FPT-100P-M06)
Lead-free Package
100-pin plastic LQFP
(FPT-100P-M05)
Lead-free Package
100-pin plastic QFP
(FPT-100P-M06)
Lead-free Package
100-pin plastic LQFP
(FPT-100P-M05)
Lead-free Package
57
MB91260B Series
■ PACKAGE DIMENSION
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100 - pin plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches)
Note: The values in parentheses are reference values.
(Continued)
58
MB91260B Series
(Continued)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100-pin plastic LQFP
(FPT-100P-M05)
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches)
Note: The values in parentheses are reference values.
59
MB91260B Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0401
FUJITSU LIMITED Printed in Japan