TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 D Controlled Baseline D D D D D D D D – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 2-A Low-Dropout Voltage Regulator Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V Fixed Output and Adjustable Versions Open Drain Power-On Reset With 100-ms Delay (TPS752xx) Open Drain Power-Good (PG) Status Output (TPS754xx) Dropout Voltage Typically 210 mV at 2 A (TPS75233) † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over the specified temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. D Ultralow 75-µA Typical Quiescent Current D Fast Transient Response D 2% Tolerance Over Specified Conditions D D for Fixed-Output Versions 20-Pin TSSOP (PWP) PowerPAD Package Thermal Shutdown Protection PWP PACKAGE (TOP VIEW) GND/HEATSINK NC IN IN EN RESETor PG‡ FB/SENSE OUTPUT OUTPUT GND/HEATSINK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND/HEATSINK NC NC GND NC NC NC NC NC GND/HEATSINK NC – No internal connection ‡ PG is on the TPS754xx and RESET is on the TPS752xx description The TPS752xx and TPS754xx are low dropout regulators with integrated power-on reset and power good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233, TPS75433). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. TPS752xx and TPS754xx are designed to have fast transient response for larger load current changes. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV at an output current of 2 A for the TPS75x33) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C. The RESET (SVS, POR, or power on reset) output of the TPS752xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 TPS75x33 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE TPS75x33 LOAD TRANSIENT RESPONSE ∆ VO – Change in Output Voltage – mV 300 IO = 2 A 200 IO = 1.5 A 150 I O – Output Current – A VDO – Dropout Voltage – mV 250 100 IO = 0.5 A 50 0 –40 10 60 110 160 TJ – Junction Temperature – °C IL=2 A CL=100 µF (Tantalum) VO=3.3 V 50 0 –50 –100 –150 2 1 0 0 1 2 3 4 5 6 t – Time – ms 7 8 9 10 description (continued) The TPS754xx has a power good terminal (PG) as an active high, open drain output, which can be used to implement a power-on reset or a low-battery indicator. The TPS752xx or the TPS754xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS752xx and the TPS754xx families are available in 20 pin TSSOP (PWP) packages. AVAILABLE OPTIONS/ORDERING INFORMATION† TJ – 40°C 40 C to 125 125°C C TSSOP (PWP) OUTPUT VOLTAGE (TYP) RESET 3.3 V TPS75233QPWPEP 2.5 V TPS75225QPWPEP 1.8 V TPS75218QPWPEP 1.5 V TPS75215QPWPEP PG TPS75433QPWPEP‡ TPS75425QPWPEP‡ TPS75418QPWPEP‡ TPS75415QPWPEP‡ Adjustable 1.5 V to 5 V TPS75201QPWPEP TPS75401QPWPEP‡ † The TPS75x01 is programmable using an external resistor divider (see application information). The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS75201QPWPREP) to indicate tape and reel. ‡ Product preview 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 3 VI PG or RESET SENSE IN 4 IN OUT 0.22 µF 5 EN OUT 6 PG or RESET Output 7 8 VO 9 + GND CO † 47 µF 17 † See application information section for capacitor selection details. Figure 1. Typical Application Configuration (For Fixed Output Options) functional block diagram—adjustable version IN EN PG or RESET _ + OUT + _ 100 ms Delay (for RESET Option) Vref = 1.1834 V R1 FB R2 GND External to the device POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 functional block diagram—fixed-voltage version IN EN PG or RESET _ + OUT + _ SENSE 100 ms Delay (for RESET Option) R1 Vref = 1.1834 V R2 GND Terminal Functions (TPS752xx) TERMINAL NAME NO. I/O DESCRIPTION EN 5 I Enable Input FB/SENSE 7 I Feedback input voltage for adjustable device (sense input for fixed-voltage option) GND 17 GND/HEATSINK Regulator ground 1, 10, 11, 20 IN 3, 4 NC 2, 12, 13, 14, 15, 16, 18, 19 OUTPUT RESET Ground/heatsink I Input voltage No connection 8, 9 O Regulated output voltage 6 O Reset output Terminal Functions (TPS754xx) TERMINAL NAME EN NO. I/O DESCRIPTION 5 I Enable Input FB/SENSE 7 I Feedback input voltage for adjustable device (sense input for fixed-voltage option) GND 17 Regulator ground 1, 10, 11, 20 Ground/heatsink GND/HEATSINK IN 3, 4 NC 2, 12, 13, 14, 15, 16, 18, 19 OUTPUT PG 4 I Input voltage No connection 8, 9 O Regulated output voltage 6 O Power good output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 TPS752xx RESET timing diagram VI Vres (see Note A) Vres t VO VIT +(see Note B) Threshold Voltage VIT –(see Note B) VIT +(see Note B) Less than 5% of the output voltage VIT –(see Note B) t RESET Output Output Undefined ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ 100 ms Delay 100 ms Delay ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Output Undefined t NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 TPS754xx PG timing diagram VI VPG (see Note A) VPG t VO VIT +(see Note B) VIT +(see Note B) Threshold Voltage VIT –(see Note B) VIT –(see Note B) t PG Output Output Undefined ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Output Undefined t NOTES: A. VPG is the minimum input voltage for a valid PG. The symbol VPG is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT –Trip voltage is typically 17% lower than the output voltage (83%VO) VIT– to VIT+ is the hysteresis voltage. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 absolute maximum ratings over operating junction temperature range (unless otherwise noted)Ĕ Input voltage range‡, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 5.5 V Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V Maximum RESET voltage (TPS752xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Maximum PG voltage (TPS754xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Output voltage, VO (OUTPUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURES PACKAGE PWP§ PWP¶ AIR FLOW (CFM) TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 0 2.9 W 23.5 mW/°C 1.9 W 1.5 W 300 4.3 W 34.6 mW/°C 2.8 W 2.2 W 0 3W 23.8 mW/°C 1.9 W 1.5 W 300 7.2 W 57.9 mW/°C 4.6 W 3.8 W § This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in × 5-in PCB, 1 oz. copper, 2-in × 2-in coverage (4 in2). ¶ This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in × 2-in PCB, 1 oz. copper with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002. recommended operating conditions MIN MAX Input voltage, VI# 2.7 5 V Output voltage range, VO 1.5 5 V 0 2.0 A Output current, IO UNIT Operating virtual junction temperature, TJ – 40 125 °C # To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 electrical characteristics over recommended operating junction temperature range (TJ = –40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 47 µF (unless otherwise noted) PARAMETER TEST CONDITIONS Adjustable Voltage 1.5 V ≤ VO ≤ 5 V, MIN TJ = 25°C MAX UNIT VO 1.5 V ≤ VO ≤ 5 V 0.98VO 1 5 V Output 1.5 TJ = 25°C, 2.7 V < VIN < 5 V 2.7 V < VIN < 5 V 1 8 V Output 1.8 TJ = 25°C, 2.8 V < VIN < 5 V 2.8 V < VIN < 5 V 2 5 V Output 2.5 TJ = 25°C, 3.5 V < VIN < 5 V 3.5 V < VIN < 5 V 3 3 V Output 3.3 TJ = 25°C, 4.3 V < VIN < 5 V 4.3 V < VIN < 5 V See Note 3 Quiescent current (GND current) (see Note 1) TJ = 25°C, See Note 3 Output Out ut voltage line regulation (∆VO/VO) (see Notes 1 and 2) VO + 1 V < VI ≤ 5 V, VO + 1 V < VI < 5 V TJ = 25°C, Out ut voltage Output (see Notes 1 and 3) TYP 1.02VO 1.5 1.470 1.530 1.8 1.764 1.836 V 2.5 2.450 2.550 3.3 3.234 3.366 75 125 µA A 0.01 0.1 Load regulation (see Note 3) %/V 1 mV Output noise voltage BW = 300 Hz to 50 kHz, VO = 1.5 V CO = 100 µF, TJ = 25°C 60 µVrms Output current Limit VO = 0 V 3.3 Thermal shutdown junction temperature EN = VI, Standby current TJ = 25°C, TPS75x01 FB = 1.5 V °C 1 µA –1 High level enable input voltage 1 µA 0.7 f = 100 Hz, TJ = 25°C, CO = 100 µF, See Note 1, IO = 2 A Minimum input voltage for valid RESET IO(RESET) = 300µA, V(RESET) ≤ 0.8 V Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, Leakage current V(RESET) = 5 V 60 1 92 0.15 NOTES: 1. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 5V. 2. If VO ≤ 1.8 V then Vimin = 2.7 V, Vimax = 5 V: Line Reg. (mV) + ǒ%ńVǓ V O Line Reg. (mV) + ǒ%ńVǓ ǒVimax * 2.7 VǓ 100 If VO ≥ 2.5 V then Vimin = VO + 1 V, Vimax = 5 V: V O 1000 ǒVimax * ǒVO ) 1 VǓǓ 100 3. IO = 1 mA to 2 A POST OFFICE BOX 655303 1.3 V 98 %VO %VO 0.4 1 100 • DALLAS, TEXAS 75265 1000 V dB 0.5 IO(RESET) = 1 mA RESET time-out delay 8 µA V Low level enable input voltage Reset (TPS752xx) 10 2 Power supply ripple rejection (see Note 2) A 150 EN = VI FB input current 4.5 V µA ms TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 electrical characteristics over recommended operating junction temperature range (TJ = –40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 47 µF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Trip threshold voltage IO(PG) = 300 µA VO decreasing Hysteresis voltage Measured at VO Output low voltage IO(PG) = 1 mA V(PG) = 5.5 V Minimum input voltage for valid PG PG (TPS754xx) Leakage current Input current (EN) MIN V(PG) ≤ 0.8 V TYP MAX 1.1 1.3 V 86 %VO %VO 0.4 V 1 µA 1 µA 1 µA 80 0.5 0.15 EN = VI –1 EN = 0 V –1 High level EN input voltage 0 2 V Low level EN input voltage Dropout Dro out voltage (3.3 V Output) Out ut) (see Note 4) 0.7 IO = 2 A, TJ = 25°C VI = 3.2 V, UNIT V 210 mV IO = 2 A, VI = 3.2 V 400 NOTE 4: IN voltage equals VO(Typ) – 100 mV; TPS75x15, TPS75x18 and TPS75x25 dropout voltage limited by input voltage range limitations (i.e., TPS75x33 input voltage needs to drop to 3.2 V for purpose of this test). Table of Graphs FIGURE VO Zo VDO vs Output current 2, 3 vs Junction temperature 4, 5, Ground current vs Junction temperature 6 Power supply ripple rejection vs Frequency 7 Output spectral noise density vs Frequency 8 Output impedance vs Frequency 9 vs Input voltage 10 vs Junction temperature 11 Output voltage Dropout voltage Input voltage (min) vs Output voltage Line transient response Load transient response VO 12 13, 15 14, 16 Output voltage vs Time Equivalent series resistance (ESR) vs Output current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 19, 20 9 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 TYPICAL CHARACTERISTICS TPS75x33 TPS75x15 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 3.305 1.503 VI = 4.3 V TJ = 25°C VI = 2.7 V TJ = 25°C 1.502 VO VO – Output Voltage – V VO – Output Voltage – V 3.303 VO 3.301 3.299 1.501 1.5 1.499 3.297 1.498 3.295 0 500 1500 1000 1.497 2000 0 IO – Output Current – mA 500 1000 1500 2000 IO – Output Current – mA Figure 2 Figure 3 TPS75x15 TPS75x33 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 3.37 1.53 3.35 1.52 VO – Output Voltage – V VO – Output Voltage – V 1 mA 3.33 1 mA 3.31 3.29 2A 3.27 1.50 1.49 0 50 100 150 1.47 –40 TJ – Junction Temperature – °C Figure 4 10 2A 1.48 3.25 3.23 –50 1.51 POST OFFICE BOX 655303 10 60 110 TJ – Junction Temperature – °C Figure 5 • DALLAS, TEXAS 75265 160 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 TYPICAL CHARACTERISTICS TPS75xxx TPS75x33 GROUND CURRENT vs JUNCTION TEMPERATURE POWER SUPPLY RIPPLE REJECTION vs FREQUENCY 90 PSRR – Power Supply Ripple Rejection – dB 85 100 VI = 5 V IO = 2 A Ground Current – µ A 80 75 70 65 60 55 50 –40 10 60 110 90 70 60 50 40 VI = 4.3 V CO = 100 µF IO = 2 A TJ = 25°C 30 20 10 0 160 VI = 4.3 V CO = 100 µF IO = 1 mA TJ = 25°C 80 10 100 TJ – Junction Temperature – °C TPS75x33 TPS75x33 OUTPUT IMPEDANCE vs FREQUENCY 1M 10M 101 VI = 4.3 V VO = 3.3 V CO = 100 µF TJ = 25°C CO = 100 µF IO = 1 mA Zo – Output Impedance – Ω Vn – Voltage Noise – nV/ Hz 100k OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 2 1.6 10k Figure 7 Figure 6 1.8 1k f – Frequency – Hz 1.4 1.2 IO = 2 A 1 0.8 0.6 1 10–1 CO = 100 µF IO = 2 A 0.4 0.2 0 10 IO = 1 mA 100 1k f – Frequency – Hz 10k 50k 10–2 10 100 1K 10K 100K f – Frequency – Hz 1M 10M Figure 9 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 TYPICAL CHARACTERISTICS TPS75x01 TPS75x33 DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 350 300 IO = 2 A 250 TJ = 125°C VDO – Dropout Voltage – mV VDO – Dropout Voltage – mV 300 250 TJ = 25°C 200 150 TJ = –40°C 100 IO = 2 A 200 IO = 1.5 A 150 100 IO = 0.5 A 50 50 0 2.5 3 3.5 4 VI – Input Voltage – V 4.5 0 –40 5 10 60 160 110 TJ – Junction Temperature – °C Figure 11 Figure 10 INPUT VOLTAGE (MIN) vs OUTPUT VOLTAGE TPS75x15 LINE TRANSIENT RESPONSE ∆ VO – Change in Output Voltage – mV 4 TA = 25°C TA = 125°C 3 TA = –40°C 2.7 2 1.5 IO=2 A CO=100 µF VO=1.5 V 100 0 1.75 2 2.25 2.5 2.75 3 VO – Output Voltage – V 3.25 3.5 4 3 0 0.1 Figure 12 12 dv + 1 V µs dt –100 VI – Input Voltage – V VI – Input Voltage (Min) – V IO = 2 A 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t – Time – ms Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.9 1 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 TPS75x15 TPS75x33 LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE ∆ VO – Change in Output Voltage – mV ∆ VO – Change in Output Voltage – mV TYPICAL CHARACTERISTICS IL=2 A CL=100 µF (Tantalum) VO=1.5 V 50 0 –50 dv + 1 V µs dt 100 0 –100 VI – Input Voltage – V –100 I O – Output Current – A IO=2 A CO=100 µF VO=3.3 V –150 2 1 5.3 4.3 0 0 1 2 3 4 5 6 t – Time – ms 7 8 9 0 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t – Time – ms 0.9 1 Figure 15 Figure 14 TPS75x33 OUTPUT VOLTAGE vs TIME (STARTUP) TPS75x33 VO – Output Voltage – V IO=2 A CO=100 µF (Tantalum) VO=3.3 V 50 0 –50 –100 Enable Voltage – V I O – Output Current – A ∆ VO – Change in Output Voltage – mV LOAD TRANSIENT RESPONSE –150 2 1 VI = 4.3 V TJ = 25°C 3.3 0 4.3 0 0 0 1 2 3 4 5 6 t – Time – ms 7 8 9 10 0 Figure 16 0.2 0.4 0.6 t – Time – ms 0.8 1 Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 TYPICAL CHARACTERISTICS To Load IN VI OUT + EN CO RL GND ESR Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options) TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 Vo = 3.3 V Co = 100 µF VI = 4.3 V TJ = 25°C ESR – Equivalent series restance – Ω ESR – Equivalent series restance – Ω 10 1 Region of Stability 0.1 0.05 Vo = 3.3 V Co = 47 µF VI = 4.3 V TJ = 25°C 1 Region of Stability 0.1 Region of Instability Region of Instability 0.01 0.01 0 0.5 1 1.5 2 0 IO – Output Current – A 0.5 1 1.5 2 IO – Output Current – A Figure 19 Figure 20 † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 APPLICATION INFORMATION The TPS752xx or TPS754xx families include four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V and 3.3 V), and an adjustable regulator, the TPS75x01 (adjustable from 1.5 V to 5 V). minimum load requirements The TPS752xx and TPS754xx families are stable even at no load; no minimum load is required for operation. pin functions enable (EN) The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in shutdown mode. When EN goes to logic low, then the device will be enabled. power good (PG) (TPS752xx) The PG terminal is an open drain, active high output that indicates the status of VO (output of the LDO). When VO reaches 83% of the regulated voltage, PG will go to a high impedance state. It will go to a low-impedance state when VO falls below 83% (i.e. over load condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor. sense (SENSE) The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE terminal and VO to filter noise is not recommended because it may cause the regulator to oscillate. feedback (FB) FB is an input terminal used for the adjustable-output options and must be connected to an external feedback resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and VO to filter noise is not recommended because it may cause the regulator to oscillate. reset (RESET) (TPS754xx) The RESET terminal is an open drain, active low output that indicates the status of VO. When VO reaches 95% of the regulated voltage, RESET will go to a low-impedance state after a 100-ms delay. RESET will go to a high-impedance state when VO is below 95% of the regulated voltage. The open-drain output of the RESET terminal requires a pullup resistor. GND/HEATSINK All GND/HEATSINK terminals are connected directly to the mount pad for thermal-enhanced operation. These terminals could be connected to GND or left floating. input capacitor For a typical application, an input bypass capacitor (0.22 µF – 1 µF) is recommended for device stability. This capacitor should be as close to the input pins as possible. For fast transient condition where droop at the input of the LDO may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The size of this capacitor is dependant on the output current and response time of the main power supply, as well as the distance to the load (LDO). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 APPLICATION INFORMATION output capacitor As with most LDO regulators, the TPS752xx and TPS754xx require an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 µF and the ESR (equivalent series resistance) must be between 100 mΩ and 10 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described in this section. Larger capacitors provide a wider range of stability and better load transient response. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines. ESR and transient response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while LDO amplifier is responding. In most applications, one capacitor is used to support both functions. Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any capacitor can therefore be drawn as shown in Figure 21. RESR LESL C Figure 21. ESR and ESL 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 APPLICATION INFORMATION In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application focuses mainly on the parasitic resistance ESR. Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage. IO LDO + VESR RESR – VI RLOAD VO CO Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(CO) = VO). This means no current is flowing into the CO branch. If IO suddenly increases (transient condition), the following occurs: D The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 24). Therefore, capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR. This voltage is shown as VESR in Figure 23. D When CO is conducting current to the load, initial voltage at the load will be VO = V(CO) – VESR. Due to the discharge of CO, the output voltage VO will drop continuously until the response time t1 of the LDO is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 24. The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn: D The higher the ESR, the larger the droop at the beginning of load transient. D The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO response period. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 APPLICATION INFORMATION conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. IO VO 1 2 ESR 1 3 ESR 2 ESR 3 t1 t2 Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of VO at a Load Step From Low-to-High Output Current 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 APPLICATION INFORMATION programming the TPS75x01 adjustable LDO regulator The output voltage of the TPS75x01 adjustable regulator is programmed using an external resistor divider as shown in Figure 24. The output voltage is calculated using: V O +V ǒ1 ) R1 Ǔ R2 ref (1) Where: Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 µA and then calculate R1 using: R1 + ǒ V V Ǔ O *1 ref (2) R2 OUTPUT VOLTAGE PROGRAMMING GUIDE TPS75x01 VI 0.22 µF RESET/ PG IN 250 kΩ ≥2V ≤ 0.7 V RESET or PG Output EN OUT VO R1 FB/SENSE GND CO OUTPUT VOLTAGE R1 R2 UNIT 2.5 V 33.2 30.1 kΩ 3.3 V 53.6 30.1 kΩ 3.6 V 61.9 30.1 kΩ NOTE: To reduce noise and prevent oscillation, R1 and R2 need to be as close as possible to the FB/SENSE terminal. R2 Figure 24. TPS75x01 Adjustable LDO Regulator Programming POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 APPLICATION INFORMATION regulator protection The TPS752xx and TPS754xx PMOS-pass transistors has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS752xx and TPS754xx also feature internal current limiting and thermal protection. During normal operation, the TPS752xx and TPS754xx limit output current to approximately 3.3 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P T max * T A + J D(max) R qJA (3) Where: TJmax is the maximum allowable junction temperature RθJA is the thermal resistance junction-to-ambient for the package, i.e., 34.6°C/W for the 20-terminal PWP with no airflow (see Table 1). TA is the ambient temperature. The regulator dissipation is calculated using: P D ǒ Ǔ + V *V I O I (4) O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 THERMAL INFORMATION thermally enhanced TSSOP-20 (PWP – PowerPad) The thermally enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see Figure 25(c)] to provide an effective thermal contact between the IC and the PWB. Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, suffer from several shortcomings: they do not address the very low profile requirements (< 2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages require power-dissipation derating that severely limits the usable range of many high-performance analog circuits. The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal performance comparable to much larger power packages. The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 25. Views of Thermally Enhanced PWP Package Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface), which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference Figure 27(a), 8 cm2 of copper heat sink and natural convection). Increasing the heat-sink size increases the power dissipation range for the component. The power dissipation limit can be further improved by adding airflow to a PWB/IC assembly (see Figures 26 and 27). The line drawn at 0.3 cm2 in Figures 26 and 27 indicates performance at the minimum recommended heat-sink size, illustrated in Figure 29. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 THERMAL INFORMATION thermally enhanced TSSOP-20 (PWP – PowerPad) (continued) The thermal pad is directly connected to the substrate of the IC, which for the TPS752xxQPWPEP and TPS754xxQPWPEP series is a secondary electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary electrical connection for a given terminal which is not always ground. The PWP package provides up to 16 independent leads that can be used as inputs and outputs (Note: leads 1, 10, 11, and 20 are internally connected to the thermal pad and the IC substrate). THERMAL RESISTANCE vs COPPER HEAT-SINK AREA 150 Natural Convection R θ JA – Thermal Resistance – ° C/W 125 50 ft/min 100 ft/min 100 150 ft/min 200 ft/min 75 50 250 ft/min 300 ft/min 25 0 0.3 1 2 3 4 5 Copper Heat-Sink Area – cm2 Figure 26 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 7 8 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 THERMAL INFORMATION thermally enhanced TSSOP-20 (PWP – PowerPad) (continued) 3.5 3.5 TA = 55°C 300 ft/min PD – Power Dissipation Limit – W 3 150 ft/min 2.5 2 Natural Convection 1.5 1 0.5 0 3 300 ft/min 2.5 2 150 ft/min 1.5 Natural Convection 1 0.5 0 0.3 2 4 6 0 8 Copper Heat-Sink Size – cm2 0 0.3 2 4 6 8 Copper Heat-Sink Size – cm2 (a) (b) 3.5 TA = 105°C 3 PD – Power Dissipation Limit – W PD – Power Dissipation Limit – W TA = 25°C 2.5 2 1.5 150 ft/min 300 ft/min 1 Natural Convection 0.5 0 0 0.3 2 4 6 8 Copper Heat-Sink Size – cm2 (c) Figure 27. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 THERMAL INFORMATION thermally enhanced TSSOP-20 (PWP – PowerPad) (continued) Figure 28 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board configuration was used in the thermal experiments that generated the power ratings shown in Figure 26 and Figure 27. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RθJA for this assembly is illustrated in Figure 26 as a function of heat-sink area. A family of curves is included to illustrate the effect of airflow introduced into the system. Heat-Sink Area 1 oz Copper Board thickness Board size Board material Copper trace/heat sink Exposed pad mounting 62 mils 3.2 in. × 3.2 in. FR4 1 oz 63/67 tin/lead solder Figure 28. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package From Figure 26, RθJA for a PWB assembly can be determined and used to calculate the maximum power-dissipation limit for the component/PWB assembly, with the equation: P D(max) + T max * T J A R qJA(system) (5) Where: TJmax is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended operating limit) and TA is the ambient temperature. PD(max) should then be applied to the internal power dissipated by the TPS75233QPWPEP regulator. The equation for calculating total internal power dissipation of the TPS75233QPWPEP is: P D(total) ǒ Ǔ + V *V I O I O )V I I (6) Q Since the quiescent current of the TPS75233QPWPEP is very low, the second term is negligible, further simplifying the equation to: P D(total) ǒ Ǔ + V *V I O I (7) O For the case where TA = 55°C, airflow = 200 ft /min, copper heat-sink area = 4 cm2, the maximum power-dissipation limit can be calculated. First, from Figure 26, we find the system RθJA is 50°C/W; therefore, the maximum power-dissipation limit is: P 24 D(max) + T max * T ° J A + 125 °C * 55 C + 1.4 W °CńW R 50 qJA(system) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 (8) TPS75201-EP, TPS75215-EP, TPS75218-EP, TPS75225-EP, TPS75233-EP WITH RESET TPS75401-EP, ’75415-EP, ’75418-EP, ’75425-EP, ’75433-EP WITH POWER GOOD FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS SGLS165 – APRIL 2003 THERMAL INFORMATION thermally enhanced TSSOP-20 (PWP – PowerPad) (continued) If the system implements a TPS75233QPWPEP regulator, where VI = 5 V and IO = 800 mA, the internal power dissipation is: P D(total) ǒ Ǔ + V *V I O I O + (5 * 3.3) 0.8 + 1.36 W (9) Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters. mounting information The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted. Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data included in Figures 26 and 27 is for soldered connections with voiding between 20% and 50%. The thermal analysis shows no significant difference resulting from the variation in voiding percentage. Figure 29 shows the solder-mask land pattern for the PWP package. The minimum recommended heatsink area is also illustrated. This is simply a copper plane under the body extent of the package, including metal routed under terminals 1, 10, 11, and 20. Minimum Recommended Heat-Sink Area Location of Exposed Thermal Pad on PWP Package Figure 29. PWP Package Land Pattern POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 MECHANICAL DATA MHTS001D – JANUARY 1995 – REVISED MAY 1999 PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE 20 PINS SHOWN 0,30 0,19 0,65 20 0,10 M 11 Thermal Pad (See Note D) 4,50 4,30 0,15 NOM 6,60 6,20 Gage Plane 1 10 0,25 A 0°–ā8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 14 16 20 24 28 A MAX 5,10 5,10 6,60 7,90 9,80 A MIN 4,90 4,90 6,40 7,70 9,60 DIM 4073225/F 10/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. 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