HD49323AF-01 CDS/AGC & 10-bit A/D Converter ADE-207-262A (Z) 2nd Edition Apr. 1999 Description The HD49323AF-01 is a CMOS IC that provides CCD-AGC analog processing (CDS/AGC) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip. Functions • • • • • • • • • Correlated Double Sampling AGC Sample hold Offset compensation Serial interface control 10-bit ADC 3 V single operation (2.7 V to 3.6 V) Power dissipation: 198 mW (Typ) Maximum frequency: 20 MHz (Min) Features • Good suppression of CCD output low-frequency noise is achieved through the use of S/H type correlated double sampling. • A high S/N ratio is achieved through the use of a AGC type amplifier, and high sensitivity is provided by a wide cover range. • An auto offset circuit provides compensation of output DC offset voltage fluctuations due to variations in AGC amplifier gain. • AGC, standby mode, offset control, etc., is possible via a serial interface. • High precision is provided by a 10-bit-resolution A/D converter. • Version of Hitachi’s previous-generation HD49322BF with improved functions and performance, including in particular an approximately 3.0 dB improvement in S/N. HD49323AF-01 NC BIAS VRT VRM VRB AVDD AVSS TESTC TESTY CDSIN AVDD AVSS Pin Arrangement 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 21 40 20 41 42 19 43 18 44 17 16 45 46 15 14 47 48 13 1 2 3 4 5 6 7 8 9 10 11 12 PBLK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 NC AVSS AVDD NC NC AVDD AVSS CS SCK SDATA DVDD DVSS DVSS (Top view) 2 VRM2 CLP NC AVDD AVSS SPSIG SPBLK OBP ADCLK DVDD DVSS OE HD49323AF-01 Pin Description Pin No. Symbol Description I/O Analog(A) or Digital(D) 1 PBLK Pre-blanking pin I D 2 D0 Digital output (LSB) O D 3 to 10 D1 to D8 Digital output O D 11 D9 Digital output (MSB) O D 12 NC No connection pin — — 13 OE Digital output enable control pin I D 14 DV SS Digital ground (0 V) — D 15 DV DD Digital power supply (3 V) Connect off-chip in common with AVDD. — D 16 ADCLK ADC conversion clock input pin I D 17 OBP Optical black pulse input pin I D 18 SPBLK Black level sampling clock input pin I D 19 SPSIG Signal level sampling clock input pin I D 20 AVSS Analog ground (0 V) — A 21 AVDD Analog power supply (3 V) Connect off-chip in common with DV DD. — A 22 NC No connection pin — — 23 CLP Clamp voltage pin Connect a 0.22 µF or more capacitor between CLP and AVSS . — A 24 VRM2 Reference voltage pin (for CCD offset cancel) — A 25 AVSS Analog ground (0 V) — A 26 AVDD Analog power supply (3 V) Connect off-chip in common with DV DD. — A 27 CDSIN CDS input pin I A 28 TESTY Test input pin-Y I A 29 TESTC Test input pin-C I A 30 AVSS Analog ground (0 V) — A 31 AVDD Analog power supply (3 V) Connect off-chip in common with DV DD. — A 32 VRB Reference voltage pin 3 Connect a 0.1 µF ceramic capacitor between VRB and AVSS. — A 33 VRM Reference voltage pin 2 Connect a 0.1 µF ceramic capacitor between VRM and AVSS . — A 34 VRT Reference voltage pin 1 Connect a 0.1 µF ceramic capacitor between VRT and AVSS . — A 3 HD49323AF-01 Pin Description (cont) Pin No. Symbol Description I/O Analog(A) or Digital(D) 35 BIAS Internal bias pin Connect a 24 kΩ resistor between BIAS and AV SS . — A 36 NC No connection pin — — 37 AVSS Analog ground (0 V) — A 38 AVDD Analog power supply (3 V) Connect off-chip in common with DV DD. — A 39, 40 NC No connection pin — — 41 AVDD Analog power supply (3 V) Connect off-chip in common with DV DD. — A 42 AVSS Analog ground (0 V) — A 43 CS Serial interface control input pin I D 44 SCK Serial clock input pin I D 45 SDATA Serial data input pin I D 46 DV DD Digital power supply (3 V) Connect off-chip in common with AVDD. — D 47, 48 DV SS Digital ground (0 V) — D 4 HD49323AF-01 Input/Output Equivalent Circuit Pin Name Digital output Equivalent Circuit D0 to D9 DVDD DIN Digital output STBY or OE Digital input Analog input ADCLK OBP SPBLK SPSIG CS SCK SDATA PBLK OE Digital input *1 70kΩ (Typ) CDSIN Connected to VRM internally CDSIN Reference voltage input Clamp VRT VRM VRB VRM2 + − CLP VRT VRM VRM2 VRB AVDD + − Connected to VRM internally CLP Internal bias BIAS AVDD BIAS Note: 1. Applies to OE and PBLK. 5 HD49323AF-01 18 19 CDS 11 OE 11 D9 10bit ADC AGC CLP 23 10 D8 8 D6 7 D5 6 D4 5 D3 4 D2 35 17 PBLK 2 D0 BIAS AVSS DVDD SCK AVDD OBP CS 44 45 43 SDATA 17 9 D7 3 D1 Bias ganerator Serial interface DVSS Clamp circuit 6 VRB Gain select Output latch circuit VRM2 27 VRM 16 34 33 32 TESTC 27 TESTY 27 CDSIN 27 VRT ADCLK SPSIG SPBLK Block Diagram HD49323AF-01 Internal Functions Functional Description • CDS (Correlated Double Sampling) circuit • AGC gain selection (11-bit digital control) *1 AGC gain can be set in the range 0 dB to 34.7 dB on the (+) side, and –3.3 dB to 0 dB on the (–) side by means of 11-bit serial data. • Automatic offset adjustment is possible for the IC’s offsets (CDS, AGC, ADC) by means of serial data control at power-on.*1 • Digital output enable function • Pre-blanking function Digital output can be fixed at 32 LSB • CDS offset cancel function Note: 1. Serial data control Operating Description Figure 1 shows CDS/AGC +ADC function block. TESTC TESTY CDSIN Gain select CDS AGC 10bit ADC Serial interface SPBLK SPSIG CS D0 to D9 Offset cancel SCK SDATA ADCLK Figure 1 CDS/AGC +ADC Function Block 1. CDS (Correlated Double Sampling) Circuit The CCD imaging element alternately outputs a black level (A-period signal) and a signal including the black level (B-period signal). The CDS circuit extracts the differential voltage between the black level and the signal including the black level (see figure 4). Black level sampling is performed at the rising edge of the SPBLK pulse, and signal level sampling is performed at the rising edge of the SPSIG pulse. This sequence of operations extracts the differential voltage between the black level and the signal including the black level, and supplies this to the nextstage AGC circuit. 2. Feed back clamp function The clamp level is set by means of 5-bit serial data. The setting range is 32 LSB to 56 LSB, in 1 LSB steps. A serial data value of 0 gives a 32 LSB setting, and a value of 24 gives a 56 LSB setting. 7 HD49323AF-01 3. AGC Circuit The AGC gain is set by means of 11-bit serial data. The setting range is –3.3 dB to 34.7 dB. Details of the data are given in the following section. The (–) side gain setting uses setting codes –81 to 0 in 0.0039-multiple steps, and the (+) side gain setting uses setting codes 0 to 1023 in 0.034 dB steps. • Detailed specifications of HD49323AF-01 AGC gain setting codes (1) To improve S/N, the AD input dynamic range has been extended to 1.4 V from the 1.0 V of the HD49322BF. (2) There are two AGC gain ranges: (+) side 0 to 34.7 dB linear gain amp. (0.034 dB/step), and (–) side 0 to –3.3 dB “multiple” linear gain amp. (0.0039 multiple/step). Input CDS AGC Range Typ 1.4V Output 0V = 0 code 0.7V = 511 code 1.4V = 1023 code ADC Considering the case where AGC gain is set so that the ADC output code is 511 when a 150 mV signal is input: The HD49322BF AGC gain setting is (code 511)/150 mV multiple = 500 mV/150 mV multiple The HD49323AF-01 AGC gain setting is (code 511)/150 mV multiple = 700 mV/150 mV multiple Table 1 AGC Gain (+) Setting Code Table Code 0 1 2 3 ⋅ ⋅ ⋅ 510 511 512 513 ⋅ ⋅ ⋅ 1020 1021 1022 1023 BIN (D10 to D0) 000 0000 0000 000 0000 0001 000 0000 0010 000 0000 0011 dB 0.000 0.034 0.068 0.102 001 001 010 010 1111 1111 0000 0000 1110 1111 0000 0001 17.34 17.37 17.41 17.44 011 011 011 011 1111 1111 1111 1111 1100 1101 1110 1111 34.68 34.71 34.75 34.78 Table 2 AGC Gain (−) Setting Code Table Code 0 −1 −2 −3 ⋅ ⋅ ⋅ −30 −31 −32 −33 ⋅ ⋅ ⋅ −78 −79 −80 −81 BIN (D10 to D0) Multiple dB 0.000 000 0000 0000 1.000 111 1111 1111 0.996 −0.034 111 1111 1110 0.992 −0.068 111 1111 1101 0.988 −0.102 111 111 111 111 1110 1110 1110 1101 0010 0001 0000 1111 0.883 0.879 0.875 0.871 −1.083 −1.121 −1.160 −1.199 111 111 111 111 1011 1011 1011 1010 0010 0001 0000 1111 0.695 0.691 0.688 0.684 −3.156 −3.205 −3.255 −3.304 4. Offset cancel circuit When power is turned on, offset voltages generated by CDS, AGC, ADC, and other circuits by means of serial data control are canceled. (Refer to page 24 (Operating Sequence at Power-On).) 8 HD49323AF-01 5. Digital output enable function When the OE pin is driven high, digital output goes to the high-Z state. OE Pin Digital Output High High-Z state Low (or Open, GND) Output enable 6. Pre-blanking function When the PBLK pin is driven high, digital output is fixed at 32 LSB. However, this is valid only when the OE pin and serial data output mode settings (LINV, MINV, TEST, STBY) are low. PBLK Pin Digital Output High Fixed at 32 LSB Low (or Open, GND) Active 7. CCD offset cancel function This function cancels the offset voltage (VOFCCD) during the optical black period of the CCD imaging element. The definition of the CCD offset voltage (VOFCCD) is given below. • The difference between the black level sampling voltage and signal level sampling voltage during the OBP period is designated V OFCCD. This value is positive when (signal level sampling voltage) > (black level sampling voltage). Input signal for one pixel (during OBP period) CDS input VOFCCD (at +) VOFCCD (at −) Black level sampling point Signal level sampling point Figure 2 Black Level Signal Level Difference during OBP Period Table 3 Serial Data Settings VOFCCD Cancel Function When Used When Not Used Serial data settings VOFCON bit set to 1 VOFD0—3 (4 bits) set VOFCON bit cleared to 0 9 HD49323AF-01 • Determining serial set data VOFD0—3 (1) Provisional setting Serial data VOFD0—3 settings are made according to the value of VOFCCD as shown in table 4. (2) Actual setting The set data is adjusted so that the CLP pin (pin 23) voltage is closest to 1/2 AVDD when AGC gain is set to the maximum. The data obtained in (2) is used as the serial set data. Table 4 VOFCCD Serial Setting Data Correspondence Table (For Reference) VOFCCD Serial Setting Data (mV) VOFD3 VOFD2 VOFD1 VOFD0 –110 0 0 1 0 –90 0 0 1 1 –70 0 1 0 0 –50 0 1 0 1 –30 0 1 1 0 –10 0 1 1 1 +10 1 0 0 0 +30 1 0 0 1 +50 1 0 1 0 +70 1 0 1 1 +90 1 1 0 0 +110 1 1 0 1 10 HD49323AF-01 Timing Chart Figure 3 shows the output timing. • Sampling timing chart 0 1 CDSIN 2 3 4 5 6 N N+1 N+2 N+3 N+4 N+5 N−5 N−4 N−3 N−2 N−1 N N+6 SPBLK SPSIG ADCLK D0 to D9 Figure 3 Output Timing • The ADC output signals (D0 to D9) are output at the rising edge of ADCLK. • The pipeline delay is 5 clocks. • Regarding OBP H period OBP > 12fs Note: The phase of OBP is for a low setting of the serial data OBP INV bit. 11 HD49323AF-01 Details of Timing Specifications Details of Timing Specifications Details of the timing specifications are shown in figure 4, and the timing specifications are summarized in table 5. • Serial data SP INV bit "Lo" setting A period CDS input SPBLK B period (1) (2) 1.4V (6)-1 SPSIG 1.4V ADCLK 1.4V (3) (5) (6)-2 (4) (7) (8) • Serial data SP INV bit "Hi" setting A period CDS input SPBLK B period (1) (2) (3) 1.4V (6)-1 SPSIG 1.4V ADCLK 1.4V (7) (5) (6)-2 (4) (8) Figure 4 Details of Timing Specifications 12 HD49323AF-01 Table 5 Each Timing Specifications No. Timing Symbol Min Typ Max Unit Note (1) Black level signal read-in time t CDS1 0 5 10 ns 1 (2) SPBLK “Lo” period t CDS2 11 1/4fADCLK Typ × 1.2 ns 2 (3) Signal level read-in time t CDS3 0 5 10 ns 1 (4) SPSIG “Lo” period t CDS4 11 1/4fADCLK Typ × 1.2 ns 2 (5) SPBLK rise to SPSIG rise t CDS5 20 1/2fADCLK Typ × 1.15 ns 2 (6)-1 ADCLK rise to SPBLK rise t CDS6-1 25 — — ns 2 (6)-2 SPSIG rise to ADCLK rise t CDS6-2 0 ns 2 ADCLK tWH Min / tWL Min t CDS7, 8 22 ns (7), (8) Note: 1. Negative when data before the rising edge of SPBLK/SPSIG is sampled, and positive when data after the rising edge is sampled. 2. The polarity of SPBLK and SPSIG is for a low setting of the serial data SP INV bit. − SPBLK SPSIG + 1.4V Detailed Timing Specifications for Digital Output Enable Control Detailed timing specifications in the case of digital output enable control are shown in figure 5. When the OE pin is high, output disable mode is entered and output goes to the high-Z state. 1.4V × OE DVDD 3.0V tLZ, tZL measurement load DVDD DVDD 2kΩ DVDD/2 Digital output (D0 to D9) tLZ 10pF VOL tZL DVSS VOH DVDD/2 tHZ tZH tHZ, tZH measurement load DVSS 10pF DVSS 2kΩ DVSS Figure 5 Detailed Timing Specifications for Digital Output Enable Control 13 HD49323AF-01 Detailed Timing Specifications for Pre-Blanking Detailed timing specifications for pre-blanking are shown in figure 6. When the PBLK pin is high, digital output is fixed at 32 LSB. However, the OE pin and serial data output mode settings (LINV, MINV, TEST, STBY) take precedence. 1.4V × PBLK VOH Digital output (D0 to D9) tPBLK tPBLK Figure 6 Detailed Timing Specifications for Pre-Blanking 14 VOL DVDD 3.0V HD49323AF-01 Output Code Table Table 6 Function Table Digital Output OE STBY TEST LINV MINV PBLK D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X Hi-Z H H X X X X Hi-Z L L L L L L Table 7 as follows L H L In the table 7 below, D9 is inverted H L L In the table 7 below, D8 to D0 are inverted H H L In the table 7 below, D9 to D0 are inverted L L H L L L L H L L L L L H L L X L H L H L H L H L H L H X H H L H L H L H L H H L X L L H L H L H L H L H H X H L H L H L H L H L Output Code Table … … … … … 511 512 L H H L H L H L H L H L H L H L H L H L … … … … D0 Input Level L →0V H L H … D1 L L H H … D2 L L L L … D3 L L L L … D4 L L L L … D5 L L L L … D6 L L L L … D7 L L L L … D8 L L L L … D9 L L L L … 0 1 2 3 … Output Pin Output Step code … Table 7 Pre-blanking Test mode 1. STBY, TEST, LINV, and MINV mode setting is performed by means of serial data. 2. OE and PBLK mode setting is performed by means of external input pins. 3. Pre-blanking mode is enabled when the PBLK pin is high and all other pins are low. … Note: Operation Mode Output Hi-Z Low power standby Normal operation 1020 1021 1022 1023 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L H H L H L H →0.7V →1.4V 15 HD49323AF-01 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Power supply voltage VDD(max) 6.0 V Power dissipation PD(max) 400 mW Analog input voltage VIN(max) –0.3 to AVDD +0.3 V Digital input voltage VI(max) –0.3 to 6.0 V Operating temperature Topr –10 to +85 °C Storage temperature Tstg –55 to +125 °C Note: 16 1. VDD indicates AVDD and DVDD. 2. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter, the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation. HD49323AF-01 Electrical Characteristics (Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, REXT = 24 kΩ) Item Symbol Min Typ Max Unit Test Conditions Power supply voltage range VDD 2.70 3.00 3.60 V fCLK = 20 MHz Conversion fCLK max 20 — — MHz frequency fCLK min — — 5.5 MHz Digital input voltage VIH DVDD 2.0 × 3.0 — 5.0 V 5V amplitude input possible VIL 0 — DVDD 0.8 × 3.0 V Digital input pins except CS, SCK, and SDATA VIH2 DVDD 2.25 × 3.0 — 5.0 V 5V amplitude input possible VIL2 0 — DVDD 0.6 × 3.0 V CS, SCK, SDATA Digital output VOH DVDD –0.5 — — V IOH = –2 mA voltage VOL — — 0.5 V IOL = +2 mA Digital input current IIH — — 50 µA VIH = 5.0 V Digital input pins except PBLK and OE IIH2 — — 250 µA VIH = 5.0 V PBLK, OE IIL –50 — — µA VIL = 0 V Digital output IOZH — — 50 µA VOH = VDD current IOZL –50 — — µA VOL = 0 V ADC resolution RES 10 10 10 bit ADC integration linearity error INL — 4 10 LSBp-p fCLK = 20 MHz ADC differentiation DNL+ — 0.3 0.8 LSB fCLK = 20 MHz linearity error DNL– –0.8 –0.3 — LSB Digital output delay time tPD — — 35 ns Digital output hold time tHOLD 10 — — ns Note: Remarks *1 CL = 10 pF 1. DNL calculate the difference of linearity error between next two codes. 17 HD49323AF-01 Electrical Characteristics (Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, REXT = 24 kΩ) (cont) Item Symbol Min Typ Max Unit Test Conditions Sleep current ISLP –100 0 100 µA Digital input pins fixed at 0 V, output pins open Standby current ISTBY — 8 12 mA Digital input pins fixed at 0 V ADC Input range VINp-p — (1.4) — V Digital output Hi-Z tHZ — — 100 ns RL = 2 kΩ delay time tLZ — — 100 ns CL = 10 pF tZH — — 100 ns tZL — — 100 ns Digital output PBLK delay time tPBLK — — 100 ns CL = 10 pF *3 Quiescent current IDD1 — 66 78 mA fCLK = 20 MHz CDSIN use Timing specification (1) tCDS1 0 5 10 ns Timing specification (2) tCDS2 11 1/4fADCLK Typ × 1.2 ns Timing specification (3) tCDS3 0 5 10 ns Timing specification (4) tCDS4 11 1/4fADCLK Typ × 1.2 ns Timing specification (5) tCDS5 20 1/2fADCLK Typ × 1.15 ns Timing specification (6-1) tCDS6-1 25 — — ns Timing specification (6-2) tCDS6-2 0 — — ns Timing specification (7) tCDS7 22 — — ns Timing specification (8) tCDS8 22 — — ns Input current IINCDS –60 — 10 µA Clamp level CLP(00) — (32) — LSB CLP(16) — (48) — LSB CLP(24) — (56) — LSB Note: 18 2. Items in parentheses are reference values. 3. Refer to page 12 (Details of Timing Specifications). 4. This is not transition current, but static current. Remarks *2 *3 *3 fCLK = 20 MHz, Black/signal level difference = 1 V, gain = 0 dB *4 *2 HD49323AF-01 Electrical Characteristics (Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, REXT = 24 kΩ) (cont) Item Symbol Min Typ Max Unit AGC gain(–) AGC(–081) –5.3 –3.3 –1.3 dB AGC(0000) –2.0 0 2.0 dB AGC(0000) –2.0 0 2.0 dB AGC(0128) 2.4 4.4 6.4 dB AGC(0256) 6.7 8.7 10.7 dB AGC(0384) 11.1 13.1 15.1 dB AGC(0512) 15.4 17.4 19.4 dB AGC(0640) 19.8 21.8 23.8 dB AGC(0768) 24.1 26.1 28.1 dB AGC(0896) 28.5 30.5 32.5 dB AGC(1023) 32.3 34.8 37.8 dB AGC gain(+) Test Conditions Remarks 19 HD49323AF-01 Serial Interface Specification CS SDATA latched at rise of SCK *1 tINT1 fSCK tINT2 *2, 3 SCK tsu SDATA Data fixed at rise of CS tho DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Note: 1. SDATA is latched at the rise of SCK. 2. Input 16 SCK clocks while CS is low. If the number of clocks is more or less than 16, the data will be invalid. 3. If data transmission is aborted, the data is invalid. Figure 7 Serial Interface Specification 20 HD49323AF-01 Table 8 Serial Data Functions Table Resister 0 Resister 1 Resister 2 Resister 3 DI 00 (LSB) Lo Hi Lo Hi DI 01 Lo Lo Hi Hi DI 02 AGC Gain setting (LSB) SP INV SPSIG/SPBLK inversion DI 03 AGC Gain setting OBP INV Lo→Negative input Hi→Positive input Clamp level adjustment Lo→fCLK>10MHz Hi→fCLK<10MHz Clamp level adjustment Clamp level adjustment (LSB) DI 04 AGC Gain setting CIF DI 05 AGC Gain setting 3 VOFCON Lo→OFF * Hi→ON Clamp level adjustment DI 06 AGC Gain setting VOFD0 (LSB) CCD offset voltage setting Clamp level adjustment (MSB) DI 07 AGC Gain setting VOFD1 CCD offset voltage setting Test mode *2 DI 08 AGC Gain setting VOFD2 CCD offset voltage setting Low DI 09 AGC Gain setting VOFD3 (MSB) CCD offset voltage setting Low DI 10 AGC Gain setting Output mode setting (LINV) Low DI 11 AGC Gain setting Output mode setting (MINV) High DI 12 AGC Gain setting (MSB) Output mode setting (TEST) Low DI 13 Test mode Low setting *2 RESET Lo→Reset mode Hi→Normal operation mode High DI 14 Test mode Low setting *2 OFRST Lo→Normal operation mode Hi→Offset cancel mode High DI 15 (MSB) Output mode setting (STBY) *1 SLP Lo→Normal operation mode Hi→Sleep mode *1 Low Test mode *2 Use prohibited ALL Low High Notes: 1. STBY: Reference voltage generation circuit is in the operational state. SLP: All circuits are in the sleep state. 2. Test mode is used for IC testing, and so cannot be used. Register 2 test mode should be set in accordance with the specification at the right of the column. For other registers, the setting should only be made in the all-low state. 3. Setting of VOFCON : Lo→CCD offset cancel function OFF : Hi→CCD offset cancel function ON Timing Specifications Min Max fSCK 3MHz 50ns tINT1, 2 tsu 50ns tho 50ns • OBP polarity OBP INV setting = Lo Negative H period OBP > 12fs H period OBP INV setting = Hi Positive OBP > 12fs 21 HD49323AF-01 Notice for Use 1. Careful handling is necessary to prevent damage due to static electricity. 2. This product has been developed for consumer applications, and should not be used in non-consumer applications. 3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be inserted between the ground and power supply. 4. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter, the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation. 5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure below. Analog +3.0V Digital +3.0V Noise filter AVDD DVDD HD49323AF-01 AVSS DVSS Noise filter DVDD Example of noise filter AVDD HD49323AF-01 DVSS 100µH 0.01µF 0.01µF AVSS 6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system set grounds, connect to the analog system. 7. When V DD is specified in the delivery specification, this indicates AVDD and DVDD . 8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be used as power supply ground pins or left open to prevent crosstalk in adjacent analog pins. 9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of bending than Fe-type lead material, careful handling is necessary. 10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as solder dipping cannot be used. 11. Depending on the mounting state, picture quality (crosscut noise, wave pattern, etc.) will be dependent upon the timing of the SPBLK, SPSIG, and ADCLK signals. Check the mounting state thoroughly before use. 12. Serial communication should not be performed during the effective video period, since this will result in degraded picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the HD49323AF-01. If ports are to be shared with another IC, picture quality should first be thoroughly checked. 13. At power-on, automatic adjustment of the offset voltage generated from CDS, AGC, ADC, etc., must be implemented in accordance with the power-on operating sequence (see page 24). 22 HD49323AF-01 14. If the phase difference between the black level sampling voltage and the signal level sampling voltage during the CCD imaging element optical black period (the CCD offset voltage) is ±30 mV or greater, the CCD offset cancel function (page 9, item 7, CCD Offset Cancel Function) must be implemented. The CCD offset voltage variation after implementation of the CCD offset cancel function should be within ±20 mV. 15. The CDSIN pin is clamped at VRM (≅ AVDD/2) during operation. The IC may suffer permanent damage if used with a pin voltage in the range –0.3 V to AV DD + 0.3 V. Careful attention must therefore be paid to the input signals. 23 HD49323AF-01 Operating Sequence at Power-On Must be stabilized within operating power supply voltage range VDD 0ms 0ms 0ms or or or 1V(16ms) more more more or more RESET 4V(64ms) or more 0ms or more (2) RESET = "Hi" (1) RESET = "Lo" OFRST (4) OFRST = "Hi" HD49323AF data transfer (5) OFRST = "Lo" (6) Data transfer (3) Data transfer 0ms or more SPBLK TG and SPSIG Camera DSP ADCLK control start OBP etc. Note: 1. RESET and OFRST both use serial data transmission. 2. Stable input of SPBLK, SPSIG, ADCLK, and OBP is assumed before RESET is transmitted. 3. Numbers in parentheses in the figure show the order of transfer. Figure 8 Operating Sequence at Power-On Serial data transmission contents are shown in table 9. “X” indicates data for which the clock polarity, clamp level, etc., can be selected. See page 21 (table 8, Serial Data Functions Table) for the purpose of the data. Table 9 Serial Data Order of Transfer (1) RESET = "Lo" (2) RESET = "Hi" (3) Data transfer Wait (4) OFRST = "Hi" Wait (5) OFRST = "Lo" (6) Data transfer 24 a) b) c) d) MSB 15 14 0 0 0 0 0 0 1 1 e) 0 f) 0 g) 0 LSB 01 00 Remarks 0 1 0 1 0 1 1 0 1 V (16 ms) or more 1 1 0 0 0 X X X X X X X X 0 1 4 V (64 ms) or more 0 1 0 0 0 X X X X X X X X 0 1 X X X X X X X X X X X X X 0 0 13 0 1 1 1 12 0 0 0 0 11 0 0 0 1 Serial Data 10 09 08 07 0 0 0 0 0 0 0 0 0 X X X 0 0 0 0 (DI) 06 05 0 0 0 0 X X X X 04 0 0 X X 03 0 0 X X 02 0 0 X X HD49323AF-01 Example of Recommended External Circuit • CDS/AGC function is used (OE control and pre-blanking function are not used) C7 1.0 R1 R2 R3 R4 220 220 220 220 from Timing generator C6 C5 C4 C3 C2 C1 0.1 15p 15p 15p 15p 0.1 + − from CCD out VRM2 CLP NC AVDD AVSS SPSIG SPBLK OBP ADCLK DVDD DVSS OE 24 23 22 21 20 19 18 17 16 15 14 13 C8 0.1 25 AVSS 26 AVDD NC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PBLK 27 CDSIN C9 1/16 28 TESTY 29 TESTC C12 0.1 30 AVSS 31 AVDD C13 0.1 32 VRB C14 0.1 33 VRM C15 0.1 34 VRT HA49323AF-01 (CDS/AGC/ADC) 36 NC R5 24k AVSS AVDD NC NC AVDD AVSS CS SCK SDATA DVDD DVSS DVSS 35 BIAS 12 11 10 9 8 6 5 4 3 2 1 L2 47µ 37 38 39 40 41 42 43 44 45 46 47 48 C17 47/6 Analog 3.0V L1 47µ C21 47/6 C18 0.1 C19 0.1 to Camera signal processor 7 C20 0.1 Digital 3.0V GND Serial data input 25 HD49323AF-01 Package Dimensions Preliminary Unit: mm 24 48 13 12 0.75 0.10 *Dimension including the plating thickness Base material dimension 26 M 1.40 1.70 Max 0.08 *0.17 ± 0.05 0.15 ± 0.04 1 *0.21 ± 0.05 0.19 ± 0.04 0.5 37 0.13 +0.09 −0.05 9.0 ± 0.2 9.0 ± 0.2 7.0 36 25 1.00 0.75 0° − 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) FP-48C Conforms 0.2 g HD49323AF-01 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 27