HITACHI HD74ALVCH16260

HD74ALVCH16260
12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
ADE-205-135B (Z)
3rd. Edition
December 1999
Description
The HD74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two
separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical
applications include multiplexing and / or demultiplexing of address and data information in
microprocessor or bus interface applications. This device is also useful in memory interleaving
applications. Three 12-bit I / O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and /
or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and / or data
information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is
transparent. When the latch enable input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high. Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@V CC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16260
Function Table
Inputs
Output A
1B
2B
SEL
LE1B
LE2B
OEA
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
A0 *1
X
H
L
X
H
L
H
X
L
L
X
H
L
L
X
X
L
X
L
L
A0 *1
X
X
X
X
X
H
Z
B-to-A (OEB = H)
Inputs
Outputs
A
LEA1B
LEA2B
OE1B
OE2B
1B
2B
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
2B0 *1
L
H
L
L
L
L
2B0 *1
H
L
H
L
L
1B0 *1
H
L
1B0
*1
L
*1
2B0 *1
L
L
H
L
X
L
L
L
L
1B0
X
X
X
H
H
Z
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
A-to-B (OEA = H)
H : High level
L : Low level
X : Immaterial
Z : High impedance
Note: 1. Output level before the indicated steady state input conditions were established.
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HD74ALVCH16260
Pin Arrangement
OEA 1
56 OE2B
LE1B 2
55 LEA2B
2B3 3
54 2B4
GND 4
53 GND
2B2 5
52 2B5
2B1 6
VCC 7
51 2B6
A1 8
49 2B7
A2 9
48 2B8
A3 10
47 2B9
50 VCC
GND 11
46 GND
A4 12
45 2B10
A5 13
44 2B11
A6 14
43 2B12
A7 15
42 1B12
A8 16
41 1B11
A9 17
40 1B10
GND 18
39 GND
A10 19
38 1B9
A11 20
37 1B8
A12 21
36 1B7
VCC 22
35 VCC
1B1 23
34 1B6
1B2 24
33 1B5
GND 25
32 GND
1B3 26
31 1B4
LE2B 27
30 LEA1B
SEL 28
29 OE1B
(Top view)
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HD74ALVCH16260
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1, 2
Symbol
Ratings
Unit
VCC
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
–0.5 to VCC +0.5
Output voltage
*1, 2
Conditions
Except I/O ports
I/O ports
VO
–0.5 to VCC +0.5
V
Input clamp current
I IK
–50
mA
VI < 0
Output clamp current
I OK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
VCC, GND current / pin
I CC or IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air) *3
PT
1
W
Storage temperature
Tstg
–65 to 150
°C
Notes:
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High level output current
I OH
—
–12
mA
—
–12
VCC = 2.7 V
—
–24
VCC = 3.0 V
—
12
—
12
VCC = 2.7 V
—
24
VCC = 3.0 V
Low level output current
I OL
mA
Input transition rise or fall rate
∆t / ∆v
0
10
ns / V
Operating temperature
Ta
–40
85
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
4
Conditions
VCC = 2.3 V
VCC = 2.3 V
HD74ALVCH16260
Logic Diagram
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1
2
27
30
55
56
29
1
28
C1
8
G1
1
1
1D
23
1B1
C1
1D
6
2B1
C1
1D
C1
1D
To eleven other channels
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HD74ALVCH16260
Electrical Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V) *1
Input voltage
VIH
VIL
Output voltage
VOH
Min
Max
Unit
2.3 to 2.7
1.7
—
V
2.7 to 3.6
2.0
—
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
I OH = –100 µA
Min to Max VCC–0.2
—
2.3
2.0
—
I OH = –6 mA, VIH = 1.7 V
2.3
1.7
—
I OH = –12 mA, VIH = 1.7 V
2.7
2.2
—
I OH = –12 mA, VIH = 2.0 V
3.0
2.4
—
I OH = –12 mA, VIH = 2.0 V
3.0
2.0
—
I OH = –24 mA, VIH = 2.0 V
Min to Max —
0.2
I OL = 100 µA
2.3
—
0.4
I OL = 6 mA, VIL = 0.7 V
2.3
—
0.7
I OL = 12 mA, VIL = 0.7 V
2.7
—
0.4
I OL = 12 mA, VIL = 0.8 V
3.0
—
0.55
I OL = 24 mA, VIL = 0.8 V
I IN
3.6
—
±5
I IN (hold)
2.3
45
—
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
3.6
—
±500
VIN = 0 to 3.6 V
I OZ
3.6
—
±10
µA
VOUT = VCC or GND
Quiescent supply current I CC
3.6
—
40
µA
VIN = VCC or GND
3.0 to 3.6
—
750
µA
VIN = one input at (VCC–0.6) V,
other inputs at V CC or GND
VOL
Input current
Off state output current
*2
∆I CC
V
Test Conditions
µA
VIN = VCC or GND
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2. For I/O ports, the parameter I OZ includes the input leakage current.
6
HD74ALVCH16260
Switching Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V)
Min
Typ
Max
Unit
2.5±0.2
150
—
—
MHz
2.7
150
—
—
3.3±0.3
150
—
—
t PLH
2.5±0.2
1.2
—
5.6
t PHL
2.7
—
—
5.1
3.3±0.3
1.2
—
4.3
2.5±0.2
1.0
—
6.2
2.7
—
—
5.2
3.3±0.3
1.0
—
4.4
2.5±0.2
1.2
—
6.9
2.7
—
—
6.6
3.3±0.3
1.1
—
5.6
t ZH
2.5±0.2
1.0
—
6.7
t ZL
2.7
—
—
6.4
3.3±0.3
1.0
—
5.4
t HZ
2.5±0.2
1.7
—
5.7
t LZ
2.7
—
—
5.0
3.3±0.3
1.3
—
4.6
2.5±0.2
1.4
—
—
2.7
1.1
—
—
3.3±0.3
1.1
—
—
2.5±0.2
1.6
—
—
2.7
1.9
—
—
3.3±0.3
1.5
—
—
2.5±0.2
3.3
—
—
2.7
3.3
—
—
3.3±0.3
3.3
—
—
Maximum clock frequency f max
Propagation delay time
Output enable time
Output disable time
Setup time
Hold time
Pulse width
t su
th
tw
FROM
(Input)
TO
(Output)
A or B
B or A
LE
A or B
SEL
A
ns
OE
A or B
ns
OE
A or B
ns
ns
ns
ns
Input capacitance
CIN
3.3
—
3.5
—
pF
Control inputs
Output capacitance
CIN / O
3.3
—
9.0
—
pF
A or B ports
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HD74ALVCH16260
• Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
C L = 50 pF
500 Ω
Load Circuit for Outputs
Symbol
t PLH / t PHL
t su / t h / t w
t ZH/ t HZ
t ZL / t LZ
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
OPEN
OPEN
GND
GND
4.6 V
6.0 V
Note: 1. C L includes probe and jig capacitance.
8
HD74ALVCH16260
• Waveforms – 1
tf
tr
90 %
Input
VIH
90 %
Vref
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
• Waveforms – 2
tr
VIH
90 %
Vref
Timing Input
10 %
tsu
GND
th
VIH
Data Input
Vref
Vref
GND
tw
VIH
Input
Vref
Vref
GND
9
HD74ALVCH16260
• Waveforms – 3
Output
Control
tf
tr
VIH
90 %
90 %
Vref
Vref
10 %
t ZL
10 %
GND
t LZ
≈VOH1
Vref
Waveform - A
t ZH
Waveform - B
VOL + 0.3 V
t HZ
VOH – 0.3 V
Vref
VOL
VOH
≈VOL1
TEST
VIH
Vref
VOH1
VOL1
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
2.3 V
2.7 V
1.2 V
2.3 V
1.5 V
3.0 V
GND
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
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HD74ALVCH16260
Package Dimensions
Unit : mm
+0.3
14.00 –0.1
29
6.10 +0.3
–0.1
56
28
0.15 ± 0.05
0.08 M
0.40 Max
0.10
1.20 max
0.20 +0.1
–0.05
0.50
0.05 Min
1
8.10 ± 0.3
10° Max
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-56D
—
—
11
HD74ALVCH16260
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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