HITACHI HD74LV163A

HD74LV163A
Synchronous 4-bit Binary Counter (Synchronous Clear)
ADE-205-265B (Z)
3rd Edition
April 2000
Description
The HD74LV163A is 4-bit binary counters. All flip flops are clocked simultaneously on the low to high to
transition (positive edge) of the clock input waceform. These counters may be preset using the load input.
Presetting of all four flip flops is synchronous to the rising edge of clock. When load is held low counting
is disabled and the data on the A, B, C and D inputs is loaded into the counter on the rising edge clock. If
the load input is taken high before the positive edge of clock the count operation will be unaffected.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
HD74LV163A
Function Table
Inputs
Outputs
CLR
LOAD
ENP
ENT
CLK
QA
QB
QC
QD
L
X
X
X
↑
L
L
L
L
H
L
X
X
↑
A
B
C
D
H
H
X
L
↑
No change
H
H
L
X
↑
No change
H
H
H
H
↑
Count up
X
X
X
X
↓
No change
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
A, B, C, D: Data input
Carry = ENT • QA • QB • QC • QD
Pin Arrangement
CLR 1
16 VCC
CARRY
15 OUTPUT
CK 2
A 3
14 QA
B 4
13 QB
C 5
12 QC
D 6
11 QD
ENP 7
10 ENT
GND 8
9 LOAD
(Top view)
2
HD74LV163A
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range*
1
Output voltage range*
1, 2
Symbol
Ratings
Unit
VCC
–0.5 to 7.0
V
VI
–0.5 to 7.0
V
VO
–0.5 to VCC + 0.5
V
–0.5 to 7.0
Conditions
Output: H or L
VCC: OFF
Input clamp current
I IK
–20
mA
VI < 0
Output clamp current
I OK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±25
mA
VO = 0 to VCC
Continuous current through
VCC or GND
I CC or IGND
±50
mA
Maximum power dissipation
at Ta = 25°C (in still air)*3
PT
785
mW
500
Storage temperature
Tstg
–65 to 150
SOP
TSSOP
°C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
3
HD74LV163A
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
2.0
5.5
V
Input voltage range
VI
0
5.5
V
Output voltage range
VO
0
VCC
V
H or L
Output current
I OH
—
–50
µA
VCC = 2.0 V
—
–2
mA
VCC = 2.3 to 2.7 V
—
–6
VCC = 3.0 to 3.6 V
—
–12
VCC = 4.5 to 5.5 V
—
50
µA
VCC = 2.0 V
—
2
mA
VCC = 2.3 to 2.7 V
—
6
VCC = 3.0 to 3.6 V
—
12
VCC = 4.5 to 5.5 V
0
200
0
100
VCC = 3.0 to 3.6 V
0
20
VCC = 4.5 to 5.5 V
–40
85
I OL
Input transition rise or fall rate
Operating free-air temperature
∆t /∆v
Ta
Note: Unused or floating inputs must be held high or low.
4
ns/V
°C
Conditions
VCC = 2.3 to 2.7 V
HD74LV163A
Logic Diagram
CLK
CLR
D Q
Output
QA
CK
LOAD
Enable
Q
P
T
A
D Q
Output
QB
CK
Q
B
D Q
Data
Inputs
Output
QC
CK
Q
C
D Q
Output
QD
CK
Q
D
Carry
Output
5
HD74LV163A
Timing Diagram
CLR
LOAD
A
Data
Inputs
B
C
D
CLK
ENP
ENT
QA
Out
puts
QB
QC
QD
Carry
12
13
14
15
0
Count
Clear Preset
6
1
2
Inhibit
HD74LV163A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item
Symbol
VCC (V)*
Min
Typ
Max
Unit
Input voltage
VIH
2.0
1.5
—
—
V
2.3 to 2.7
VCC × 0.7
—
—
3.0 to 3.6
VCC × 0.7
—
—
4.5 to 5.5
VCC × 0.7
—
—
2.0
—
—
0.5
2.3 to 2.7
—
—
VCC × 0.3
3.0 to 3.6
—
—
VCC × 0.3
4.5 to 5.5
—
—
VCC × 0.3
Min to
Max
VCC – 0.1
—
—
2.3
2.0
—
—
IOL = –2 mA
3.0
2.48
—
—
IOL = –6 mA
4.5
3.8
—
—
IOL = –12 mA
Min to
Max
—
—
0.1
IOL = 50 µA
2.3
—
—
0.4
IOL = 2 mA
3.0
—
—
0.44
IOL = 6 mA
4.5
—
—
0.55
IOL = 12 mA
VIL
Output voltage
VOH
VOL
V
Test Conditions
IOL = –50 µA
Input current
IIN
0 to 5.5
—
—
±1
µA
VIN = 5.5 V or GND
Quiescent
supply current
ICC
5.5
—
—
20
µA
VIN = VCC or GND, IO = 0
Output leakage
current
IOFF
0
—
—
5
µA
VO = 5.5 V
Input
capacitance
CIN
3.3
—
1.7
—
pF
VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
7
HD74LV163A
Switching Characteristics
• VCC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
FROM
(Input)
TO
(Output)
CLK
Q
CLK
Carry
CLK
Carry
ENT
Carry
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test Conditions
Maximum
clock
frequency
fmax
50
90
—
40
—
MHz
CL = 15 pF
30
60
—
25
—
—
11.1
16.2
1.0
19.5
—
14.3
19.2
1.0
22.5
CL = 50 pF
tPLH/tPHL
—
11.5
17.0
1.0
20.5
CL = 15 pF
Count
mode
—
14.7
20.0
1.0
23.5
CL = 50 pF
tPLH/tPHL
—
13.8
20.6
1.0
24.5
CL = 15 pF
Load
—
17.0
23.6
1.0
27.5
CL = 50 pF
—
10.3
15.7
1.0
19.0
CL = 15 pF
—
14.0
18.7
1.0
22.0
CL = 50 pF
7.5
—
—
8.5
—
10.0
—
—
11.5
—
LOAD before CLK ↑
9.5
—
—
11.0
—
ENT, ENP before
CLK ↑
6.0
—
—
6.0
—
CLR before CLK ↑
1.5
—
—
1.5
—
1.5
—
—
1.5
—
7.0
—
—
7.0
—
Propagation
delay time
tPLH/tPHL
CL = 50 pF
ns
CL = 15 pF
mode
tPLH/tPHL
Setup time
Hold time
Pulse
width
8
tsu
th
tw
ns
Data before CLK ↑
ns
CLR after CLK ↑
ns
CLK H or L
HD74LV163A
Switching Characteristics (cont)
• VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
FROM
(Input)
TO
(Output)
CLK
Q
CLK
Carry
CLK
Carry
ENT
Carry
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test Conditions
Maximum
clock
frequency
tmax
80
130
—
70
—
MHz
CL = 15 pF
55
85
—
50
—
—
8.3
12.8
1.0
15.0
—
10.8
16.3
1.0
18.5
CL = 50 pF
tPLH/tPHL
—
8.7
13.6
1.0
16.0
CL = 15 pF
Count
mode
—
11.2
17.1
1.0
19.5
CL = 50 pF
tPLH/tPHL
—
11.0
17.2
1.0
20.0
CL = 15 pF
Load
mode
—
13.5
20.7
1.0
23.5
CL = 50 pF
tPLH/tPHL
—
7.5
12.3
1.0
14.5
CL = 15 pF
—
10.5
15.8
1.0
18.0
CL = 50 pF
5.5
—
—
6.5
—
8.0
—
—
9.5
—
LOAD before CLK ↑
7.5
—
—
9.0
—
ENT, ENP before
CLK ↑
4.0
—
—
4.0
—
CLR before CLK ↑
1.0
—
—
1.0
—
1.0
—
—
1.0
—
5.0
—
—
5.0
—
Propagation
delay time
Setup time
Hold time
Pulse
width
tPLH/tPHL
tsu
th
tw
CL = 50 pF
ns
ns
CL = 15 pF
Data before CLK ↑
ns
CLR after CLK ↑
ns
CLK H or L
9
HD74LV163A
Switching Characteristics (cont)
• VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
FROM
(Input)
TO
(Output)
CLK
Q
CLK
Carry
CLK
Carry
ENT
Carry
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test Conditions
Maximum
clock
frequency
tmax
135
185
—
115
—
MHz
CL = 15 pF
95
125
—
85
—
—
4.9
8.1
1.0
9.5
—
8.7
10.1
1.0
11.5
CL = 50 pF
tPLH/tPHL
—
4.9
8.1
1.0
9.5
CL = 15 pF
Count
mode
—
6.4
10.1
1.0
20.0
CL = 50 pF
tPLH/tPHL
—
6.2
10.3
1.0
12.0
CL = 15 pF
Load
mode
—
7.7
12.3
1.0
14.0
CL = 50 pF
tPLH/tPHL
—
4.9
8.1
1.0
9.5
CL = 15 pF
—
6.4
10.1
1.0
11.5
CL = 50 pF
4.5
—
—
4.5
—
5.0
—
—
6.0
—
LOAD before CLK ↑
5.0
—
—
6.0
—
ENT, ENP before
CLK ↑
3.5
—
—
3.5
—
CLR before CLK ↑
1.0
—
—
1.0
—
1.5
—
—
1.5
—
5.0
—
—
5.0
—
Propagation
delay time
Setup time
Hold time
Pulse
width
10
tPLH/tPHL
tsu
th
tw
CL = 50 pF
ns
ns
CL = 15 pF
Data before CLK ↑
ns
CLR after CLK ↑
ns
CLK H or L
HD74LV163A
Operating Characteristics
•
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test Conditions
Power
dissipation
capacitance
CPD
3.3
—
17.3
—
pF
f = 10 MHz
5.0
—
20.6
—
Test Conditions
Noise Characteristics
•
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Quiet output,
maximum
dynamic VOL
VOL (P)
3.3
—
0.3
0.8
V
Quiet output,
minimum
dynamic VOL
VOL (V)
3.3
—
–0.3
–0.8
Quiet output,
minimum
dynamic VOH
VOH (V)
3.3
—
3.0
—
High-level
dynamic
input voltage
VIH (D)
3.3
2.31
—
—
Low-level
dynamic
input voltage
VIL (D)
3.3
—
—
0.99
V
11
HD74LV163A
Test Circuit
Measurement point
CL*
Note: 1. CL includes the probe and jig capacitance.
12
HD74LV163A
Waveform
Waveform – 1
Count mode
tWL
tWH
VCC
CLK
50%
50%
GND
VOH
50%
Q, CARRY
50%
tpLH
VOL
tpHL
Waveform – 2
Preset mode
VCC
LOAD
50%
tsu
50%
th
tsu
th
GND
50%
A to D
tsu
th
VCC
CLK
50%
50%
GND
tpLH, tpHL
VOH
Q, CARRY
50%
VOL
13
HD74LV163A
Waveform – 3
Count enable mode
VCC
ENP
ENT
50%
50%
GND
tsu
th
tsu
th
VCC
CLK
50%
50%
GND
VOH
Q
VOL
Waveform – 4
Clear mode
CLR
VCC
50%
50%
GND
tsu
th
VCC
CLK
50%
GND
VOH
Q, CARRY
VOL
14
HD74LV163A
Waveform – 5
Cascade mode
(set to maximum count number)
VCC
ENT
50%
50%
GND
VOH
CARRY
50%
tpLH
50%
VOL
tpHL
Note: 1. Input waveform: PRR≤1 MHz, duty cycle 50%, t r ≤3 ns, t f ≤3 ns
Application
Cascade circuitry
H: COUNT
L: DISABLE
INPUTS
LD A
B
C
INPUTS
D
ENP
H: COUNT
L: DISABLE
ENT
LD A
B
C
INPUTS
D
ENP
CARRY
ENT
LD A
B
C
D
ENP
CARRY
ENT
CARRY
CK
CK
CK
CLR QA QB QC QD
CLR QA QB QC QD
CLR QA QB QC QD
OUTPUT
OUTPUT
to next stages
OUTPUT
CLR
CLK
15
HD74LV163A
Package Dimensions
10.06
10.5 Max
9
1
8
1.27
0.42 ± 0.08
0.40 ± 0.06
0.10 ± 0.10
0.80 Max
0.22 ± 0.05
0.20 ± 0.04
2.20 Max
5.5
16
0.20
7.80 +– 0.30
1.15
0° – 8°
0.70 ± 0.20
0.15
0.12 M
Dimension including the plating thickness
Base material dimension
16
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DA
—
Conforms
0.24 g
HD74LV163A
Unit: mm
9.9
10.3 Max
9
1
8
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
0.15
*0.22 ± 0.03
0.20 ± 0.03
1.27
0.11
0.14 +– 0.04
1.75 Max
3.95
16
0.10
6.10 +– 0.30
1.08
0° – 8°
+ 0.67
0.60 – 0.20
0.25 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DN
Conforms
Conforms
0.15 g
17
HD74LV163A
5.0
5.3 Max
9
1
8
4.40
16
0.65
0.13 M
1.10 Max
0.65 Max
0.10
Dimension including the plating thickness
Base material dimension
18
6.40 ± 0.20
0.07 +0.03
–0.04
0.20 ± 0.06
1.0
0.17 ± 0.05
0.15 ± 0.04
0.08
0.22 +– 0.07
0° – 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-16DA
—
—
0.05 g
HD74LV163A
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as in aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safe
devices, so that the equipment incorporating the Hitachi product does not cause bodily injury, fire or
other consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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Japan
: http://www.hitachi.co.jp/Sicd/index.htm
For further information write to:
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(America) Inc.
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Tel: <1> (408) 433-1990
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Copyright ' Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
19