HD74LV164A 8-bit Parallel-out Serial-in Shift Register ADE-205-266 (Z) 1st Edition March 1999 Description The HD74LV164A is 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup and hold time but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by low level at the clear input. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) HD74LV164A Function Table Inputs Outputs CLR CLK A B QA QB ... QD L X X X L L ... L H ↓ X X QA0 QB0 ... QH0 H ↑ H H H QAn ... QGn H ↑ L X L QAn ... QGn H ↑ X L L QAn ... QGn Note: H: High level L: Low level X: Immaterial ↑: Low to high transition ↓: High to low transition QAD, QB0...Q H0: Outputs remain unchanged. QAn, QBn...QGn : Data shifted from the previous stage on a positive edge at the clock input. Pin Arrangement A 1 14 VCC B 2 13 QH QA 3 12 QG QB 4 11 QF QC 5 10 QE QD 6 9 CLR GND 7 8 CLK (Top view) 2 HD74LV164A Absolute Maximum Ratings Item Supply voltage range Input voltage range* 1 Output voltage range* 1, 2 Symbol Ratings Unit VCC –0.5 to 7.0 V VI –0.5 to 7.0 V VO –0.5 to VCC + 0.5 V –0.5 to 7.0 Conditions Output: H or L VCC: OFF Input clamp current I IK –20 mA VI < 0 Output clamp current I OK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND I CC or IGND ±50 mA Maximum power dissipation at Ta = 25°C (in still air)*3 PT 785 mW 500 Storage temperature Tstg –65 to 150 SOP TSSOP °C Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. 3 HD74LV164A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC 2.0 5.5 V Input voltage range VI 0 5.5 V Output voltage range VO 0 VCC V H or L Output current I OH — –50 µA VCC = 2.0 V — –2 mA VCC = 2.3 to 2.7 V — –6 VCC = 3.0 to 3.6 V — –12 VCC = 4.5 to 5.5 V — 50 µA VCC = 2.0 V — 2 mA VCC = 2.3 to 2.7 V — 6 VCC = 3.0 to 3.6 V — 12 VCC = 4.5 to 5.5 V 0 200 0 100 VCC = 3.0 to 3.6 V 0 20 VCC = 4.5 to 5.5 V –40 85 I OL Input transition rise or fall rate Operating free-air temperature ∆t /∆v Ta Note: Unused or floating inputs must be held high or low. 4 ns/V °C Conditions VCC = 2.3 to 2.7 V HD74LV164A Logic Diagram CLK A B CLR 8 C1 1 2 C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R 1D R C1 1D R 9 3 4 5 6 QA QB QC QD 10 QE 11 QF 12 QG 13 QH Timing Diagram CLR A B CLK QA QB QC QD QE QF QG QH Clear Clear 5 HD74LV164A DC Electrical Characteristics • Ta = –40 to 85°C Item Symbol VCC (V)* Min Typ Max Unit Input voltage VIH 2.0 1.5 — — V 2.3 to 2.7 VCC × 0.7 — — 3.0 to 3.6 VCC × 0.7 — — 4.5 to 5.5 VCC × 0.7 — — 2.0 — — 0.5 2.3 to 2.7 — — VCC × 0.3 3.0 to 3.6 — — VCC × 0.3 4.5 to 5.5 — — VCC × 0.3 Min to Max VCC – 0.1 — — 2.3 2.0 — — IOL = –2 mA 3.0 2.48 — — IOL = –6 mA 4.5 3.8 — — IOL = –12 mA Min to Max — — 0.1 IOL = 50 µA 2.3 — — 0.4 IOL = 2 mA 3.0 — — 0.44 IOL = 6 mA 4.5 — — 0.55 IOL = 12 mA VIL Output voltage VOH VOL V Test Conditions IOL = –50 µA Input current IIN 0 to 5.5 — — ±1 µA VI = 5.5 V or GND Quiescent supply current ICC 5.5 — — 20 µA VI = VCC or GND, IO = 0 Output leakage current IOFF 0 — — 5 µA VI or VO = 0 V to 5.5 V Input capacitance CIN 3.3 — 2.2 — pF VI = VCC or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 6 HD74LV164A Switching Characteristics • VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Test Conditions Maximum clock frequency fmax 55 105 — 50 — MHz CL = 15 pF 45 85 — 40 — — 9.2 17.6 1.0 20.0 — 11.5 21.1 1.0 24.0 CL = 50 pF — 8.6 16.0 1.0 18.0 CL = 15 pF — 10.8 19.5 1.0 22.0 CL = 50 pF 6.5 — — 8.5 — 3.0 — — 3.0 — Propagation delay time tPLH/tPHL tPHL Setup time tsu FROM (Input) TO (Output) CLK Q CL = 50 pF ns ns CL = 15 pF CLR Data before CLK ↑ CLR inactive before CLK ↑ Hold time th –0.5 — — 0.0 — ns Data after CLK ↑ Pulse width tw 6.0 — — 6.5 — ns CLR L 6.5 — — 7.5 — CLK H or L 7 HD74LV164A Switching Characteristics (cont) • VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Test Conditions Maximum clock frequency fmax 80 155 — 65 — MHz CL = 15 pF 50 120 — 45 — — 6.4 12.8 1.0 15.0 — 8.3 16.3 1.0 18.5 CL = 50 pF — 6.0 12.8 1.0 15.0 CL = 15 pF — 7.9 16.3 1.0 18.5 CL = 50 pF 5.0 — — 6.0 — 2.5 — — 2.5 — Propagation delay time tPLH/tPHL tPHL Setup time tsu FROM (Input) TO (Output) CLK Q CL = 50 pF ns ns CL = 15 pF CLR Data before CLK ↑ CLR inactive before CLK ↑ Hold time th 0.0 — — 0.0 — ns Data after CLK ↑ Pulse width tw 5.0 — — 5.0 — ns CLR L 5.0 — — 5.0 — 8 CLK H or L HD74LV164A Switching Characteristics (cont) • VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Test Conditions Maximum clock frequency fmax 125 220 — 105 — MHz CL = 15 pF 85 165 — 75 — — 4.5 9.0 1.0 10.5 — 6.0 11.0 1.0 12.5 CL = 50 pF — 4.2 8.6 1.0 10.0 CL = 15 pF — 5.8 10.6 1.0 12.0 CL = 50 pF 45 — — 4.5 — 2.5 — — 2.5 — Propagation delay time tPLH/tPHL tPHL Setup time tsu FROM (Input) TO (Output) CLK Q CL = 50 pF ns ns CL = 15 pF CLR Data before CLK ↑ CLR inactive before CLK ↑ Hold time th 1.0 — — 1.0 — ns Data after CLK ↑ Pulse width tw 5.0 — — 5.0 — ns CLR L 5.0 — — 5.0 — CLK H or L 9 HD74LV164A Operating Characteristics • CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 — 48.1 — pF f = 10 MHz 5.0 — 47.5 — Test Conditions Noise Characteristics • CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Quiet output, maximum dynamic VOL VOL (P) 3.3 — 0.3 0.8 V Quiet output, minimum dynamic VOL VOL (V) 3.3 — –0.2 –0.8 Quiet output, minimum dynamic VOH VOH (V) 3.3 — 3.1 — High-level dynamic input voltage VIH (D) 3.3 2.31 — — Low-level dynamic inout voltage VIL (D) 3.3 — — 0.99 10 V HD74LV164A Test Circuit Measurement point CL* Note: C L includes the probe and jig capacitance. 11 HD74LV164A Waveform • Waveform – 1 tr Timing input 10% t su tf 90% 50% VCC 90% 50% VCC th VCC 10% 0V VCC Data input 50% VCC 50% VCC 0V tw VCC Input 50% VCC 50% VCC 0V • Waveform – 2 tr Input 10% tf 90% 50 % VCC 90% 50% VCC VCC 10 % t PHL t PLH 0V VOH In phase output 50% VCC 50% VCC VOL t PHL t PLH VOH Out of phase output 50% VCC 50% VCC VOL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns 2. The output are measured one at a time with one transition per measurement. 12 HD74LV164A Package Dimensions 10.06 10.5 Max 9 1 8 1.27 0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max 0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g 13 HD74LV164A Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° + 0.67 0.60 – 0.20 0.25 M *Dimension including the plating thickness Base material dimension 14 Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g HD74LV164A 5.0 5.3 Max 9 1 8 4.40 16 0.65 0.13 M 1.10 Max 0.65 Max 0.10 Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 0.17 ± 0.05 0.15 ± 0.04 0.08 0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-16DA — — 0.05 g 15 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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