HM51W4405BS Series 1,048,576-word × 4-bit Dynamic Random Access Memory ADE-203-686A (Z) Rev. 1.0 Nov. 29, 1996 Description The Hitachi HM51W4405BS Series is a CMOS dynamic RAM organized 1,048,576-word × 4-bit. HM51W4405BS Series has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51W4405BS Series offers Extended Data Out (EDO) Page Mode as a high speed access mode. It has the package variations of standard 26-pin plastic SOJ. Features • Single 3.3 V (±0.3 V) (HM51W4405BS-7) • Single 3.3 V (+0.3 V/–0.15 V) (HM51W4405BS-6R) • High speed Access time: 60/70 ns (max) • Low power dissipation Active mode: 288/252 mW (max) Standby mode: 7.2 mW (max) • EDO page mode capability • 1024 refresh cycles : 16 ms • 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Ordering Information Type No. Access time Package HM51W4405BS-6R HM51W4405BS-7 60 ns 70 ns 300-mil 26-pin plastic SOJ (CP-26/20D) Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Pin Arrangement HM51W4405BS Series I/O1 1 26 VSS I/O2 2 25 I/O4 WE 3 24 I/O3 RAS 4 23 CAS A9 5 22 OE A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 V CC 14 A4 13 (Top view) Pin Description Pin name Function A0 to A9 Address input • Row/Refresh: A0 to A9 • Column: A0 to A9 I/O1 to I/O4 Data-in/Data-out RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Row Address Buffer Row Driver 256 k Memory Array Mat OE Control Circuit 256 k Memory Array Mat WE Control Circuit I/O Bus & Column Decoder CAS Control Circuit 256 k Memory Array Mat OE I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat I/O Bus & Column Decoder WE 256 k Memory Array Mat Row Driver 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat CAS 256 k Memory Array Mat Row Row Driver Driver I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat Row Row Driver Driver 256 k Memory Array Mat Row Driver I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat RAS Control Circuit 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat RAS 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat HM51W4405BS Series Block Diagram I/O1 I/O2 I/O3 I/O4 I/O1 Buffer I/O2 Buffer I/O3 Buffer I/O4 Buffer Row Decoder & Peripheral Circuit Row Row Driver Driver Row Driver Row Row Driver Driver Row Driver Column Address Buffer Address A0–A9 3 HM51W4405BS Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –0.5 to +4.6 V Supply voltage relative to VSS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VSS 0 0 0 V • (HM51W4405BS-6R) VCC 3.15 3.3 3.6 V 1 • (HM51W4405BS-7) VCC 3.0 3.3 3.6 V 1 Input high voltage VIH 2.0 — VCC + 0.3 V 1 Input low voltage VIL –0.3 — 0.8 V 1 Note: 1. All voltage referred to VSS . 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Note HM51W4405BS Series DC Characteristics (Ta = 0 to +70°C, VCC= 3.3 V +0.3 V/–0.15 V, VSS= 0 V) (HM51W4405BS-6R) (Ta = 0 to +70°C, VCC= 3.3 V ±0.3 V, VSS = 0 V) (HM51W4405BS-7) HM51W4405B -6R Parameter -7 Symbol Min Max Min Max Unit Test conditions I CC1 — 80 — 70 mA RAS, CAS cycling, t RC = min Standby current I CC2 — 2 — 2 mA TTL interface, RAS, CAS = VIH Dout = High-Z Standby current I CC2 — 1 — 1 mA CMOS interface RAS, CAS ≥ V CC –0.2 V Dout = High-Z I CC3 — 80 — 70 mA t RC = min Standby current* I CC5 — 4 — 4 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RASrefresh current I CC6 — 80 — 70 mA t RC = min EDO page mode current*1, 3 I CC4 — 100 — 85 mA t HPC = min Input leakage current I LI –10 10 –10 10 µA 0 V ≤ Vin ≤ 4.6 V Output leakage current I LO –10 10 –10 10 µA 0 V ≤ Vout ≤ 4.6 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA Operating current* 1, 2 RAS-only refresh current*2 1 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Capacitance (Ta = 25°C, VCC= 3.3 V +0.3 V/–0.15 V) (HM51W4405BS-6R) (Ta = 25°C, VCC= 3.3 V ±0.3 V) (HM51W4405BS-7) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series AC Characteristics (Ta = 0 to +70°C, VCC= 3.3 V +0.3 V /–0.15 V , VSS= 0 V ) (H M 51W4405BS-6R)* 1 , *1 4 , *1 5 (Ta = 0 to +70°C, VCC= 3.3 V ±0.3 V, VSS= 0 V) (HM51W4405BS-7)*1, *14, *15 Test Conditions • • • • • Input rise and fall time : 2 ns Input level : VIL = 0 V, V IH = 3.0 V Input timing reference levels : 0.8 V, 2.0 V Output timing reference levels : 0.8 V, 2.0 V Output load: 1 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM51W4405B -6R Parameter Symbol Min Random read or write cycle time t RC RAS precharge time -7 Max Min Max Unit 104 — 124 — ns t RP 40 — 50 — ns RAS pulse width t RAS 60 10000 70 10000 ns 17 CAS pulse width t CAS 10 10000 13 10000 ns 18 Row address setup time t ASR 0 — 0 — ns Row address hold time t RAH 10 — 10 — ns Column address setup time t ASC 0 — 0 — ns Column address hold time t CAH 10 — 13 — ns RAS to CAS delay time t RCD 20 45 20 50 ns 8 RAS to column address delay time t RAD 15 30 15 35 ns 9 RAS hold time t RSH 15 — 18 — ns CAS hold time t CSH 48 — 58 — ns CAS to RAS precharge time t CRP 10 — 10 — ns OE to Din delay time t ODD 15 — 18 — ns OE delay time from Din t DZO 0 — 0 — ns CAS setup time from Din t DZC 0 — 0 — ns Transition time (rise and fall) tT 2 50 2 50 ns Refresh period t REF — 16 — 16 ms 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Notes 21 7 HM51W4405BS Series Read Cycle HM51W4405B -6R Parameter Symbol Min Access time from RAS t RAC Access time from CAS -7 Max Min Max Unit Notes — 60 — 70 ns 2, 3 t CAC — 15 — 18 ns 3, 4, 13 Access time from address t AA — 30 — 35 ns 3, 5, 13 Access time from OE t OAC — 15 — 18 ns 3 Read command setup time t RCS 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — ns 16 Read command hold time to RAS t RRH 0 — 0 — ns 16 Column address to RAS lead time t RAL 30 — 35 — ns Column address to CAS lead time t CAL 18 — 23 — ns Output buffer turn-off time t OFF1 — 15 — 15 ns 6,19 Output buffer turn-off time to OE t OFF2 — 15 — 15 ns 6 CAS to Din delay time t CDD 15 — 18 — ns RAS to Din delay time t RDD 15 — 18 — ns WE to Din delay time t WDD 15 — 18 — ns OE pulse width t OEP 15 — 18 — ns Turn-off to RAS t OFR — 15 — 15 ns 6, 19 Turn-off to WE t WEZ — 15 — 15 ns 6 Output data hold time t OH 5 — 5 — ns Output data hold time from RAS t OHR 5 — 5 — ns Read command hold time from RAS t RCHR 60 — 70 — ns Read command hold time from CAS t RCHC 15 — 18 — ns Read command hold time from column address t RCHA 30 — 35 — ns 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Write Cycle HM51W4405B -6R Parameter Symbol Min Write command setup time t WCS Write command hold time -7 Max Min Max Unit Notes 0 — 0 — ns 10 t WCH 10 — 13 — ns Write command pulse width t WP 10 — 10 — ns Write command to RAS lead time t RWL 10 — 13 — ns Write command to CAS lead time t CWL 10 — 13 — ns Data-in setup time t DS 0 — 0 — ns 11 Data-in hold time t DH 10 — 13 — ns 11 Notes Read-Modify-Write Cycle HM51W4405B -6R Parameter Symbol Min Read-modify-write cycle time t RWC RAS to WE delay time -7 Max Min Max Unit 133 — 159 — ns t RWD 77 — 90 — ns 10 CAS to WE delay time t CWD 32 — 38 — ns 10 Column address to WE delay time t AWD 47 — 55 — ns 10 OE hold time from WE t OEH 15 — 18 — ns Refresh Cycle HM51W4405B -6R Parameter Symbol Min CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) -7 Max Min Max Unit 10 — 10 — ns t CHR 10 — 10 — ns RAS precharge to CAS hold time t RPC 10 — 10 — ns CAS precharge time in normal mode t CPN 10 — 13 — ns CBR refresh cycle WE setup time t WS 0 — 0 — ns CBR refresh cycle WE hold time t WH 10 — 10 — ns 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Notes HM51W4405BS Series EDO Page Mode Cycle HM51W4405B -6R Parameter Symbol Min EDO page mode cycle time t HPC EDO page mode CAS precharge time -7 Max Min Max Unit Notes 25 — 30 — ns 20 t CP 10 — 13 — ns EDO page mode RAS pulse width t RASC — 100000 — 100000 ns 12 Access time from CAS precharge t ACP — 35 — 40 ns 3, 13 RAS hold time from CAS precharge t RHCP 35 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — ns CAS hold time referred OE t COL 10 — 13 — ns CAS to OE setup time t COP 5 — 5 — ns Read command hold time from CAS precharge t RCHP 35 — 40 — ns EDO Page Mode Read-Modify-Write Cycle HM51W4405B -6R Parameter Symbol Min EDO page mode read-modify-write cycle time t HPCM EDO page mode read-modify-write t CPW cycle CAS precharge to WE delay time -7 Max Min Max Unit 66 — 77 — ns 52 — 60 — ns Notes 10 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Counter Test Cycle HM51W4405B -6R Parameter Symbol Min CAS precharge time in counter test cycle t CPT 40 -7 Max Min Max Unit — 40 — ns Notes Notes: 1. AC measurements assume t T = 2 ns. 2. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 4. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 5. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 6. t OFF1 (max), tOFF2 (max), tOFR (max) and tWEZ (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD, t CPW and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), tCPW ≥ tCPW (min) and tAWD ≥ tAWD (min), the cycle is a read-modifywrite and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among t AA , t CAC and t ACP. 14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either tRCH or tRRH must be satisfied 17. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 18. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 19. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH, and between tOFR and tOFF. 20. t HPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle tHPC (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. 21. t CSH (min) can be achieved when tRCD ≤ tCSH (min) –tCAS (min). 22. XXX: H or L (H: V IH (min) ≤ V IN ≤ V IH (max), L: VIL (min) ≤ V IN ≤ V IL (max)) 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Timing Waveforms*22 Read Cycle t RC t RAS RAS tT t RP t CRP t RSH t CAS t CSH t RCD CAS t RAD t ASR Address t RAL t CAH t RAH t ASC Row Column t RCHA t CAL t RCS t RDD t OH t OHR t RCHR t RCHC t RCH t RRH WE t OFR t CAC t AA t OFF1 Dout Dout t RAC t OFF2 t OAC t DZC t WDD t ODD t DZO 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WEZ High-Z Din OE t CDD t OEP HM51W4405BS Series Early Write Cycle t RC t RAS RAS t RP t RSH t CAS tT t RCD t CRP t CSH CAS t ASR Address t RAH tASC Row t CAH Column t WCS t WCH WE t DH t DS Din Dout Din High-Z* * t WCS t WCS (min) 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t ASC t RAH t CWL t RWL t CAH Row Column t RCS t WP WE t DS t DH High-Z Din Din t DZC t ODD t DZO t OEH Dout Invalid Dout* t OFF2 OE * * Invalid Dout comes out, when OE is low level. 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR Address t RAH tCAH t ASC Row Column t CWL t CWD t RCS t RWL t AWD t WP WE t RWD t AA t CAC t DS t RAC t DH t DZC High-Z Din Dout Din Dout t OAC t OFF2 t DZO OE t OEH t ODD t OEP 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP tRPC CAS t RAH t ASR Address Row Dout 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z tCRP HM51W4405BS Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR t CHR t RPC t CRP tT CAS t CPN t WS t WH t CPN WE* Address t OFR t OFF1 Dout High-Z * tWS and tWH must be satisfied while CAS = VIL. 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Hidden Refresh Cycle tRC t RP t RAS (Read) t RC t RAS t RC t RP (Refresh) t RAS tRP (Refresh) RAS tT t RSH t CHR t CRP t CAS t RCD CAS t ASC t ASR Address t RAL t RAD t CAH t RAH Row Column t RCH t RRH t OHR t RCS t CAC WE t AA t OFF1 t OH t RAC Dout Dout t DZC t OFF2 t CDD High-Z Din tDZO t OAC OE 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t ODD t RDD t WEZ t WDD HM51W4405BS Series EDO Page Mode Read Cycle (tHPCminimum cycle operation) t RASC t RHCP t RP RAS tT t CSH t RCD t HPC t CAS t CP t CAS t RSH t CP t CRP t CAS CAS t ASR t CAL t RAD t RAH Address t CAH tASC Row Column 1 t CAL t CAL t ASC t CAH Column 2 t RAL t CAH t ASC Column 3 t RCHA t RRH t RCHP t RCS t RCH t RCHC WE t WEZ t DZC t CDD High-Z Din t CAC t CAC t RAC t AA t AA t ACP t DOH Dout 1 Dout t CAC t AA t ACP t DOH Dout 2 t OFR t OH t ODD t OHR t OFF1 Dout 3 t OAC t DZO t OFF2 OE 19 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series EDO Page Mode Read Cycle (High-Z control by WEand OE) t RP t RASC RAS tT t CSH CAS t CP t HPC t CAS t RCS t CP t HPC t CAS tCAS tCAS t RCHP t RCHC t RCHA tASR tRAH t ASC tCAH Row tASC t ASC t CAH Column 2 tCAL tDZC t RRH t RCH t t RAL RCHC t ASC t CAH Column 1 t CRP t RHCP t CP t RCH t RCS t RCHR WE Address t HPC Column 3 t CAL t WDD t CAH Column 4 t CAL tRDD tCDD t CAL High-Z Din tCOL tDZO tCOP tODD OE tAA tCAC tCAC tAA Dout tOFF2 Dout 1 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 tACP tAA tCAC tWEZ tRAC tOFR tOHR tOFF2 tACP tACP tOAC tOAC Dout 2 tAA tOFF2 tDOH Dout 2 tCAC tOFF1 tOH tOAC Dout 3 Dout 4 HM51W4405BS Series EDO Page Mode Early Write Cycle (tHPCminimum cycle operation) t RASC t RP RAS tT t CSH t RCD t RSH t HPC t CAS t CP t CAS t CAS t CP t CRP CAS t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH t ASC t CAH Column t WCS t ASC t CAH Column t WCH t WCH t WCS WE t DS Din Din Dout t DH t DS Din t DH t DS t DH Din High-Z 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series EDO Page Mode Delayed Write Cycle t RP t RASC RAS tT t CSH tRCD t HPC t CAS t CP t CAS t RSH t CAS t CP t CRP CAS t ASR t RAH Address t ASC t CAH t ASC t CAH Row t CAH t ASC Column Column Column t CWL t CWL t RCS t CWL t WP t WP t WP t RWL WE t DH t DS Din t RCS t DH t DS t DH t DS Din Din t RCS Din t OEH High-Z Dout t ODD OE 22 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series EDO Page Mode Read-Modify-Write Cycle t RP t RASC RAS t RCD t HPCM tT t CAS CAS t CRP t CP t CP t CAS t CAS t RAD t RAH t ASR Address t ACP t CAH t ASC t ASC Row t ASC Column Column t CWL t AWD t CWD t RCS t CAH t CAH t AWD t CWL t CWD t RCS t WP t RWD Column t CPW t WP t RCS t CPW t CWL t AWD t RWL t CWD t WP WE t CAC t DZC t DZC t CAC t DH High-Z Din High-Z Din tAA Din t OEH Dout t OAC t OEH Dout t OFF2 t DS t DH t DZC High-Z Din t CAC t DZO tOAC t DZO t DH t AA t RAC Dout t ACP t DS t DS t AA t OAC t OEH Dout t OFF2 t DZO t OFF2 OE t ODD t ODD t OEP t OEP t ODD tOEP 23 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series EDO Page Mode Mix Cycle (1)*20 t RP t RASC RAS t CSH tT CAS t CAS t WCS t CAS tCAS Address t RCHP t RCHC tCPW tAWD t ASC tRAH Row tCAH Column 1 tCAL t DS Din tCAS t WCH WE tASR t ASC t CAH tASC t CAH Column 2 Column 3 t CAL tWP tASC t RRH t RCH t RCHA t RAL t CAH Column 4 t CAL t DS t DH Din 1 t CRP t CP t CP t CP High-Z t DH tRDD tCDD t CAL Din 3 tODD tWDD OE t ACP tAA tOAC tCAC tDZO t ACP tOFF2 tAA tCAC 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Dout 2 tAA tOFF2 tCAC tOAC t DOH Dout tOFR tWEZ tACP Dout 3 tOFF1 tOH Dout 4 HM51W4405BS Series EDO Page Mode Mix Cycle (2) *20 t RP t RASC RAS tT t CSH CAS t CAS t RCS t RCHR t CAS Address tCAS t RCH t WCS t WCH tCAS Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 tCAL t DS High-Z Din t DH Column 4 Din 2 tODD t RRH t RCH t RCHA t RAL t CAH tASC t CAL t DS t CAL t RCHC tWP tCPW t ASC tRAH t RCHP tCWL WE tASR t CRP t CP t CP t CP tRDD tCDD t CAL t DH Din 3 tDZO tODD tWDD tDZO OE tAA tOAC tCAC tOFF2 Dout 1 tOFR tWEZ tOFF2 tACP tCAC tRAC Dout t OAC tACP tAA tOFF2 tAA tCAC tOAC Dout 3 tOFF1 tOH Dout 4 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series CAS-Before-RAS Refresh Counter Check Cycle (Read) t RP t RAS RAS tT t CSR t CHR t CPT t RSH tCRP t CAS CAS t CAL t ASC t CAH Column Address t RCH t RRH t WS t WH t RCS WE t CDD t DZC High-Z Din t OHR t CAC t OFR t AA t OFF1 t OH Dout Dout t DZO t OFF2 t OAC t OEP OE 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t ODD HM51W4405BS Series CAS-Before-RAS Refresh Counter Check Cycle (Write) t RAS t RP RAS tT t CSR t CHR t CPT t RSH t CRP t CAS CAS t CAL t ASC t CAH Address Column t WS t WH t WCS t WCH WE t DS Din Dout t DH Din High-Z OE 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Package Dimensions HM51W4405BS Series (CP-26/20D) 14 13 1.30 Max 0.43 ± 0.10 0.41 ± 0.08 5.08 1.27 0.21 2.40 +– 0.24 9 0.80 +0.25 –0.17 5 0.74 3.50 ± 0.26 1 8.51 ± 0.13 16.90 17.27 Max 22 18 7.62 ± 0.13 26 Unit: mm 6.71 ± 0.28 0.10 Hitachi Code JEDEC Code EIAJ Code Weight 28 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CP-26/20D MO-077-AA SC-633A 0.6 g HM51W4405BS Series Disclaimer When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Sales Offices Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 29 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4405BS Series Revision Record Rev. Date Contents of Modification 1.0 Nov. 29, 1996 Initial issue 30 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Drawn by Approved by