SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999 D D D D D D D D DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) Enable Signal Is SSTL_2 Compatible Flow-Through Architecture Optimizes PCB Layout Designed for Use With 200 Mbit/s Double Data-Rate (DDR) SDRAM Applications Switch On-State Resistance Is Designed to Eliminate Series Resistor to DDR SDRAM Internal 10-kΩ Pulldown Resistors to Ground on B Port Internal 50-kΩ Pullup Resistor on Output-Enable Input Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Shrink Small-Outline (DBQ), Thin Very Small-Outline (DGV), Small-Outline (DW), and Thin Shrink Small-Outline (PW) Packages VREF A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 description This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE) input levels. When OE is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. There are 10-kΩ pulldown resistors to ground on the B port. The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path. The SN74CBTLV3857 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUT OE FUNCTION L A port = B port H Disconnect Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999 logic diagram (positive logic) 22 2 A1 B1 SW RINT 13 11 A10 B10 SW RINT VCC OE VREF 23 1 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range (OE only), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input voltage range (except OE), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999 recommended operating conditions (see Note 3) VCC VREF Supply voltage VIH VIL AC high-level control input voltage VIH VIL DC high-level control input voltage Reference voltage (0.38 × VCC) MIN NOM MAX 3 3.3 3.6 UNIT V 1.15 1.25 1.35 V VREF + 350 mV V AC low-level control input voltage VREF – 350 mV VREF + 180 mV V V DC low-level control input voltage VREF – 180 mV 85 V TA Operating free-air temperature –40 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 3 V, MIN TYP† II = –18 mA –1.2 ±1 OE A port II B port VCC = 3 3.6 6V V, VI = VCC or GND VCC = 3.6 V, VI = 3 V or 0 IO = 0, VO = 3 V or 0, OE = VCC VREF ICC Ci MAX Control inputs Cio(OFF) ron‡ VCC = 3 V VI = VCC or GND V mA ±5 µA ±1 mA ±5 µA 25 mA 3.5 pF 5 pF VI = 0, VI = 0.9 V, II = 24 mA II = 24 mA 5 8 6 11 VI = 1.25 V, II = 24 mA 7 13 VI = 1.6 V, II = 24 mA 9 40 VCC = 0 roff ff‡ UNIT Ω 1 MΩ VCC = 3 V to 3.6 V, VI = 1.65 V, OE = VCC 1 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. Resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd§ A or B B or A ten OE A or B tdis OE A or B PARAMETER VCC = 3.3 V ± 0.3 V MIN UNIT MAX 0.25 ns 1.4 4.2 ns 1.4 4.8 ns § The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBTLV3857 LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V AND VDDQ = 2.5 ± 0.2 V 500 Ω From Output Under Test VDDQ × 2 Open S1 GND CL = 50 pF (see Note A) 500 Ω Output Control LOAD CIRCUIT TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VDDQ × 2 GND VREF† VREF† VIH (AC)‡ VIL (AC)§ tPZL VDDQ VDDQ/2 Input VDDQ/2 0V tPLH Output Waveform 1 S1 at 2 × VDDQ (see Note B) VDDQ/2 Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VDDQ VDDQ/2 VOL + 0.15 V VOL tPZH tPHL VOH VDDQ/2 VOL tPLZ Output Waveform 2 S1 at GND (see Note B) tPHZ VDDQ/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES † VREF = 0.38 × VCC ‡ VIH(AC) = VREF + 350 mV § VIL(AC) = VREF – 350 mV NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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