TI TCA6408RGTRG4

TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
FEATURES
•
•
•
•
•
5-V Tolerant I/O Ports
Active-Low Reset Input (RESET)
Open-Drain Active-Low Interrupt Output (INT)
400-kHz Fast I2C Bus
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power-Up With All Channels Configured as
Inputs
No Glitch On Power-Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
16
VCCP
ADDR
2
15
SDA
RESET
3
14
SCL
ZXY PACKAGE
(TOP VIEW)
1 2 3 4 5
SDA
1
ADDR
VCCI
VCCP
RGT PACKAGE
(TOP VIEW)
PW PACKAGE
(TOP VIEW)
VCCI
16 15 14 13
1
12
A
4
13
INT
P0
2
11
INT
B
P1
5
12
P7
P1
3
10
P7
C
P2
6
11
P6
P2
4
9
P6
D
P3
7
10
P5
GND
8
9
P4
5
6
7
8
P4
SCL
P0
RESET
P5
•
•
•
•
•
•
•
•
•
•
•
P3
•
Operating Power-Supply Voltage Range of
1.65 V to 5.5 V
Allows Bidirectional Voltage-Level Translation
and GPIO Expansion Between
– 1.8-V SCL/SDA and 1.8-V, 2.5-V,
3.3-V, or 5-V P Port
– 2.5-V SCL/SDA and 1.8-V, 2.5-V,
3.3-V, or 5-V P Port
– 3.3-V SCL/SDA and 1.8-V, 2.5-V,
3.3-V, or 5-V P Port
– 5-V SCL/SDA and 1.8-V, 2.5-V,
3.3-V, or 5-V P Port
2
I C to Parallel Port Expander
Low Standby Current Consumption of 1 µA
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the SCL and SDA Inputs
– Vhys = 0.18 V Typ at 1.8 V
– Vhys = 0.25 V Typ at 2.5 V
– Vhys = 0.33 V Typ at 3.3 V
– Vhys = 0.5 V Typ at 5 V
GND
•
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed to provide general-purpose remote I/O
expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)].
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
TOP-SIDE MARKING
QFN – RGT
Reel of 3000
TCA6408RGTR
ZWP
BGA – ZXY (Pb-free)
Reel of 2500
TCA6408ZXYR
PH408
Tube of 70
TCA6408PW
Reel of 2000
TCA6408PWR
TSSOP – PW
(1)
ORDERABLE PART NUMBER
PH408
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The major benefit of this device is its wide VCC range. It can operate from 1.65-V to 5.5-V on the P port side and
on the SDA/SCL side. This allows the TCA6408 to interface with next-generation microprocessors and
microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to
the dropping power supplies of microprocessors and microcontrollers, some PCB components such as LEDs
remain at a 5-V power supply.
The bidirectional voltage level translation in the TCA6408 is provided through VCCI. VCCI should be connected to
the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6408. The voltage
level on the P port of the TCA6408 is determined by VCCP.
The TCA6408 consists of one 8-bit configuration (input or output selection), input, output, and polarity inversion
(active high) register. At power on, the I/Os are configured as inputs. However, the system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is
kept in the corresponding input or output register. The polarity of the input port register can be inverted with the
polarity inversion register. All registers can be read by the system master.
The system master can reset the TCA6408 in the event of a timeout or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
The TCA6408 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
input port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA6408 can remain a simple slave device.
The device P port outputs have high-current sink capabilities for directly driving LEDs while consuming low
device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices
to share the same I2C bus or SMBus.
2
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TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
ZXY Terminal Assignments
1
2
3
4
5
ADDR
A
P3
P2
P1
RESET
B
GND
N.C. (1)
P0
N.C. (1)
VCCI
C
P4
N.C. (1)
INT
N.C. (1)
VCCP
D
P5
P6
P7
SCL
SDA
(1)
N.C. – No internal connection
TERMINAL FUNCTIONS
PIN NUMBER
TSSOP
(PW)
QFN
(RGT)
BGA
(ZXY)
NAME
DESCRIPTION
1
15
B5
VCCI
2
16
A5
ADDR
Address input. Connect directly to VCCP or ground.
3
1
A4
RESET
Active-low reset input. Connect to VCCP through a pullup resistor, if no active
connection is used.
4
2
B3
P0
P port input/output (push-pull design structure). At power on, P0 is configured as
an input.
5
3
A3
P1
P port input/output (push-pull design structure). At power on, P1 is configured as
an input.
6
4
A2
P2
P port input/output (push-pull design structure). At power on, P2 is configured as
an input.
7
5
A1
P3
P port input/output (push-pull design structure). At power on, P3 is configured as
an input.
8
6
B1
GND
9
7
C1
P4
P port input/output (push-pull design structure). At power on, P4 is configured as
an input.
10
8
D1
P5
P port input/output (push-pull design structure). At power on, P5 is configured as
an input.
11
9
D2
P6
P port input/output (push-pull design structure). At power on, P6 is configured as
an input.
12
10
D3
P7
P port input/output (push-pull design structure). At power on, P7 is configured as
an input.
13
11
C3
INT
Interrupt output. Connect to VCCI through a pullup resistor.
14
12
D4
SCL
Serial clock bus. Connect to VCCI through a pullup resistor.
15
13
D5
SDA
Serial data bus. Connect to VCCI through a pullup resistor.
16
14
C5
VCCP
Supply voltage of TCA6408 for P port.
Supply voltage of I2C bus. Connect directly to the VCC of the external I2C master.
Provides voltage level translation.
Ground
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TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Voltage Translation
Table 1 shows how to set up VCC levels for the necessary voltage translation between the I2C bus and the
TCA6408.
Table 1. Voltage Translation
4
VCCI
(SCL and SDA of I2C master)
(V)
VCCP
(P Port)
(V)
1.8
1.8
1.8
2.5
1.8
3.3
1.8
5
2.5
1.8
2.5
2.5
2.5
3.3
2.5
5
3.3
1.8
3.3
2.5
3.3
3.3
3.3
5
5
1.8
5
2.5
5
3.3
5
5
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TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
INT
ADDR
SCL
SDA
VCCI
VCCP
RESET
GND
13
Interrupt
Logic
LP Filter
2
14
15
Input
Filter
2
I C Bus
Control
1
8 Bits
I/O Port
P7–P0
Write Pulse
Read Pulse
16
3
Shift
Register
Power-On
Reset
8
A.
All pin numbers shown are for the PW package.
B.
All I/Os are set to inputs at reset.
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TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Simplified Schematic of P0 to P7
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
VCCP
Configuration
Register
D
Q
Q1
FF
Write Configuration
Pulse
CK Q
D
Q
FF
Write Pulse
P0 to P7
CK Q
Output
Port
Register
Q2
Input
Port
Register
Q
D
FF
Read Pulse
ESD Protection Diode
GND
Input Port
Register Data
CK Q
To INT
Data From
Shift Register
D
Q
FF
Write Polarity Pulse
Polarity
Register Data
CK Q
Polarity
Inversion
Register
A.
On power up or reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high (see Figure 1). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address input (ADDR) of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 2).
6
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TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 3. Acknowledgment on the I2C Bus
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TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Interface Definition
BIT
BYTE
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C slave address
L
H
L
L
L
L
ADDR
R/W
I/O data bus
P7
P6
P5
P4
P3
P2
P1
P0
Device Address
The address of the TCA6408 is shown in Figure 4.
Slave Address
0
0
1
0
Fixed
0
0 AD
DR R/W
Programmable
Figure 4. TCA6408 Address
Address Reference
ADDR
I2C BUS SLAVE ADDRESS
L
32 (decimal), 20 (hexadecimal)
H
33 (decimal), 21 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgement of the address byte, the bus master sends a command byte, which
is stored in the control register in the TCA6408. Two bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
B7
B6
B5
B4
B3
B2
B1
B0
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
BYTE
(HEX)
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
1
01
Output Port
Read/write byte
1111 1111
0
0
0
0
0
0
1
0
02
Polarity Inversion
Read/write byte
0000 0000
0
0
0
0
0
0
1
1
03
Configuration
Read/write byte
1111 1111
(1)
8
Undefined
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REGISTER
PROTOCOL
POWER-UP
DEFAULT
Input Port
Read byte
xxxx xxxx (1)
TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Register Descriptions
The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the configuration register. They act only on read operation. Writes to this
register have no effect. The default value (X) is determined by the externally applied logic level. Before a read
operation, a write transmission is sent with the command byte to indicate to the I2C device that the input port
register will be accessed next.
Register 0 (Input Port Register)
BIT
I-7
I-6
I-5
I-4
I-3
I-2
I-1
I-0
DEFAULT
X
X
X
X
X
X
X
X
The output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 (Output Port Register)
BIT
O-7
O-6
O-5
O-4
O-3
O-2
O-1
O-0
DEFAULT
1
1
1
1
1
1
1
1
The polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration
register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in
this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Register 2 (Polarity Inversion Register)
BIT
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N-0
DEFAULT
0
0
0
0
0
0
0
0
The configuration register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register)
BIT
C-7
C-6
C-5
C-4
C-3
C-2
C-1
C-0
DEFAULT
1
1
1
1
1
1
1
1
Power-On Reset
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408 in a reset condition
until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6408 registers and
I2C/SMBus state machine initialize to their default states. After that, VCCP must be lowered to below 0.2 V and
back up to the operating voltage for a power-reset cycle.
Reset Input (RESET)
The RESET input can be asserted to intialize the system while keeping VCCP at its operating level. A reset can
be accomplished by holding the RESET pin low for a minimum of tW. The TCA6408 registers and I2C/SMBus
state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels
at the P port can be changed externally or through the master. This input requires a pullup resistor to VCCP, if no
active connection is used.
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TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
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SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt or in a stop event. Resetting occurs in the read
mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a
stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock
pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the
I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the input port register.
The INT output has an open-drain structure and requires a pullup resistor to VCCP or VCCI depending on the
application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6408,
then the INT pin has to be connected to VCCI. If not, the INT pin can be connected to VCCP.
Bus Transactions
Data is exchanged between the master and TCA6408 through write and read commands.
Writes
Data is transmitted to the TCA6408 by sending the device address and setting the least-significant bit to a logic
0 (see Figure 4 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one
write transmission.
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
1
0
0
0
Command Byte
AD
0 DR 0
Start Condition
0
A
0
0
0
0
0
Data to Port
0
Data 1
A
1
R/W ACK From Slave
A
ACK From Slave
P
ACK From Slave
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 6. Write to Output Port Register
<br/>
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
1
0
0
Start Condition
0
Command Byte
AD
0 DR 0
R/W
A
0
0
0
0
ACK From Slave
0
0
Data to Register
1 1/0 A
Data
ACK From Slave
Figure 7. Write to Configuration or Polarity Inversion Registers
10
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A
P
ACK From Slave
TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
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SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Reads
The bus master first must send the TCA6408 address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the TCA6408 (see Figure 8 and Figure 9).
Data is clocked into the register on the rising edge of the ACK clock pulse.
ACK From
Slave
Slave Address
S 0
0
1
0
0
0 AD
DR 0
ACK From
Slave
Command Byte
A
R/W
ACK From
ACK From
Slave Data from Register Master
Slave Address
A S 0
1
0
0 0 AD
DR 1 A
0
At this moment, master-transmitter
becomes master-receiver, and
slave-receiver becomes
slave-transmitter
Data
A
First byte
R/W
Data from Register
NACK From
Master
Data
NA P
Last Byte
Figure 8. Read From Register
<br/>
1
SCL
2
3
4
5
6
7
8
9
Data From Port
Slave Address
S 0
SDA
1
Start
Condition
0
0
0
AD
0 DR 0
R/W
Data From Port
Data 1
A
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT
tiv
tir
A.
Transfer of data can be stopped at any time by a stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
input port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8).
Figure 9. Read Input Port Register
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LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
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SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCCI
Supply voltage range
–0.5
6.5
UNIT
V
VCCP
Supply voltage range
–0.5
6.5
V
range (2)
–0.5
6.5
V
–0.5
6.5
V
VI
Input voltage
VO
Output voltage range (2)
IIK
Input clamp current
ADDR, RESET, SCL
VI < 0
±20
mA
IOK
Output clamp current
INT
VO < 0
±20
mA
P Port
VO < 0 or VO > VCCP
±20
mA
SDA
VO < 0 or VO > VCCI
±20
mA
Continuous output low current
P Port
VO = 0 to VCCP
50
mA
Continuous output low current
SDA, INT
VO = 0 to VCCI
25
mA
Continuous output high current
P Port
VO = 0 to VCCP
50
mA
Continuous current through GND
200
mA
Continuous current through VCCP
160
mA
Continuous current through VCCI
10
mA
IIOK
Input/output clamp current
IOL
IOH
ICC
PW package
θJA
Package thermal impedance (3)
Tstg
(1)
(2)
(3)
108
RGT package
53
ZXY package
193
Storage temperature range
–65
150
°C/W
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
VCCI
Supply voltage
VCCP
Supply voltage
MIN
MAX
1.65
5.5
1.65
5.5
SCL, SDA
0.7 × VCCI
5.5
ADDR, P7–P0, RESET
0.7 × VCCP
5.5
UNIT
V
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P7–P0
10
mA
IOL
Low-level output current
P7–P0
25
mA
TA
Operating free-air temperature
85
°C
12
SCL, SDA
–0.5
0.3 × VCCI
ADDR, P7–P0, RESET
–0.5
0.3 × VCCP
–40
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TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Electrical Characteristics
over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCP
MIN
–1.2
VIK
Input diode clamp voltage II = –18 mA
1.65 V to 5.5 V
VPOR
Power-on reset voltage (2) VI = VCCP or GND, IO = 0
1.65 V to 5.5 V
IOH = –8 mA
P port high-level output
voltage
VOH
IOH = –10 mA
IOL = 8 mA
P port low-level output
voltage
VOL
IOL = 10 mA
1.65 V
1.2
2.3 V
1.8
3V
2.6
4.5 V
4.1
1.65 V
1.1
2.3 V
1.7
3V
2.5
4.5 V
4.0
TYP (1)
MAX
1
1.4
UNIT
V
V
V
1.65 V
0.45
2.3 V
0.25
3V
0.25
4.5 V
0.2
1.65 V
0.6
2.3 V
0.3
3V
0.25
4.5 V
0.2
V
SDA
VOL = 0.4 V
1.65 V to 5.5 V
3
INT
VOL = 0.4 V
1.65 V to 5.5 V
3
SCL, SDA
VI = VCCI or GND
ADDR, RESET
VI = VCCP or GND
IIH
P port
VI = VCCP
IIL
P port
VI = GND
Operating
mode
SDA,
P Port,
ADDR,
RESET
VI on SDA = VCCI or GND,
VI on P port, ADDR and
RESET = VCCP or GND,
IO = 0, I/O = inputs,
fSCL = 400 kHz
SDA,
P Port,
ADDR,
RESET
VI on SDA = VCCI or GND,
VI on P port, ADDR and
RESET = VCCP or GND,
IO = 0, I/O = inputs,
fSCL = 100 kHz
SCL, SDA,
P Port,
ADDR,
RESET
VI on SCL and SDA = VCCI or
GND,
VI on P Port, ADDR and
RESET = VCCP or GND,
IO = 0, I/O = inputs,
fSCL = 0
SCL, SDA
One input at VCCI – 0.6 V,
Other inputs at VCCI or GND
1.65 V to 5.5 V
25
µA
P Port,
ADDR,
RESET
One input at VCCP – 0.6 V,
Other inputs at VCCP or GND
1.65 V to 5.5 V
60
µA
1.65 V to 5.5 V
6
7
pF
7
8
7.5
8.5
IOL
II
ICC
(ICCI + ICCP)
Operating
mode
Standby
mode
∆ICCI
∆ ICCP
Ci
SCL
VI = VCCI or GND
SDA
VIO = VCCI or GND
P Port
VIO = VCCP or GND
Cio
(1)
(2)
±0.1
1.65 V to 5.5 V
±0.1
1.65 V to 5.5 V
Additional
current in
Standby
mode
mA
15
1
µA
1
µA
3.6 V to 5.5 V
10
20
2.3 V to 3.6 V
6.5
15
1.65 V to 2.3 V
4
9
3.6 V to 5.5 V
2.5
5
2.3 V to 3.6 V
1.6
3.8
1.65 V to 2.3 V
1
2.3
3.6 V to 5.5 V
0.2
1
2.3 V to 3.6 V
0.1
0.6
1.65 V to 2.3 V
0.1
0.4
1.65 V to 5.5 V
µA
µA
pF
All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408 in a reset condition until VCCP has reached
VPOR. At that time, the reset condition is released, and the TCA6408 registers and I2C/SMBus state machine initialize to their default
states. After that, VCCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.
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TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
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SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
MIN
MAX
100
UNIT
MIN
MAX
0
400
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
0.6
µs
tscl
I2C clock low time
4.7
1.3
µs
tsp
I2C
tsds
I2C serial data setup time
tsdh
I2C serial data hold time
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time; 10 pF to 400 pF bus
tbuf
I2C bus free time between Stop and Start
4.7
1.3
µs
tsts
I2C
4.7
0.6
µs
tsth
I2C Start or repeater Start condition hold time
4
0.6
µs
tsps
I2C Stop condition setup time
4
0.6
µs
tvd(data)
Valid data time; SCL low to SDA output valid
1
1
µs
tvd(ack)
Valid data time of ACK condition; ACK signal from SCL low to
SDA (out) low
1
1
µs
(1)
spike time
0
50
100
0
0
input fall time
Start or repeater Start condition setup time
0
250
kHz
50
ns
ns
ns
1000
20 + 0.1Cb (1)
300
300
20 + 0.1Cb
(1)
300
ns
300
20 + 0.1Cb (1)
300
µs
ns
Cb = total capacitance of one bus line in pF
Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE
I2C BUS
MIN
FAST MODE
I2C BUS
MAX
MIN
UNIT
MAX
tW
Reset pulse duration
4
4
ns
tREC
Reset recovery time
0
0
ns
600
600
ns
tRESET
(1)
Time to
reset (1)
Minimum time for SDA to become high or minimum time to wait before doing a START
Switching Characteristics
over recommended operating free-air temperature range, CL≤ 100 pF (unless otherwise noted) (see Figure 10)
PARAMETER
STANDARD
MODE
I2C BUS
FAST MODE
I2C BUS
FROM
TO
P Port
INT
4
4
µs
SCL
INT
4
4
µs
400
ns
MIN
MAX
MIN
UNIT
MAX
tiv
Interrupt valid time
tir
Interrupt reset delay time
tpv
Output data valid
SCL
P7–P0
tps
Input data setup time
P Port
SCL
0
0
ns
tph
Input data hold time
P Port
SCL
300
300
ns
14
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TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
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SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
SUPPLY CURRENT
vs
TEMPERATURE
VCC = 5.0 V
10
8
VCC = 3.3 V
6
4
VCC = 2.5 V
2
VCC = 1.8 V
0
–40
–15 10
35
60
Temperature, TA (°C)
100
SCL = VCC
All I/Os unloaded
80
VCC = 5.0 V
VCC = 3.3 V
60
VCC = 2.5 V
40
VCC = 1.8 V
25
15
TA = 85°C
10
5
0.0
0.1
0.2
0.3
0.4
0.5
1.5
–40
0.6
TA = –40°C
50
40
TA = 25°C
TA = 85°C
20
10
0.1
0.2
0.3
0.4
0.5
Output Low Voltage, VOL (V)
0.6
Output Low Voltage, VOL (mV)
Sink Current, ISINK (mA)
70
3.0
3.5
4.0
4.5
5.0
5.5
85
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
50
40
TA = –40°C
30
TA = 25°C
20
TA = 85°C
10
0.1
0.2
0.3
0.4
0.5
VCC = 3.3 V
50
TA = –40°C
40
30
TA = 25°C
20
TA = 85°C
10
0.1
0.2
0.3
0.4
0.5
Output Low Voltage, VOL (V)
Output Low Voltage, VOL (V)
I/O LOW VOLTAGE
vs
TEMPERATURE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
250
VCC = 1.8 V, ISOURCE = 10 mA
200
150
VCC = 5.0 V, ISOURCE = 10 mA
100
VCC = 1.8 V, ISOURCE = 1 mA
50
VCC = 5 V, ISOURCE = 1 mA
0
60
0
0.0
0.6
300
80 VCC = 5.0 V
2.5
70
0
0.0
90
0
0.0
–15 10
35
60
Temperature, TA (°C)
VCC = 2.5 V
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
30
2.0
0
Output Low Voltage, VOL (V)
60
4
2
0
60
TA = –40°C
TA = 25°C
8
6
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
20
0
12
10
Supply Voltage, VCC (V)
85
Sink Current, ISINK (mA)
Sink Current, ISINK (mA)
VCC = 1.8 V
fSCL = 400 kHz
16 All I/Os unloaded
14
20
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
30
18
Sink Current, ISINK (mA)
12
120
–40
Source Current, ISOURCE (mA)
14
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
Supply Current, ICC (µA)
fSCL = 400 kHz
All I/Os unloaded
16
Supply Current, ICC (nA)
Supply Current, ICC (µA)
18
STANDBY SUPPLY CURRENT
vs
TEMPERATURE
0.6
30
VCC = 1.8 V
25
TA = –40°C
20
15
TA = 25°C
10
TA = 85°C
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VCCP – VOH (V)
–15
10
35
60
85
Temperature, TA (°C)
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LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
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SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
90
70
VCC = 2.5 V
40
35
TA = –40°C
30
25
20
15
TA = 25°C
TA = 85°C
10
5
0
0.0
0.1
0.2
0.3
0.4
0.5
VCC = 3.3 V
60
50
TA = –40°C
40
30
TA = 25°C
20
TA = 85°C
10
0
0.0
0.6
Source Current, ISOURCE (mA)
45
Source Current, ISOURCE (mA)
Source Current, ISOURCE (mA)
50
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
0.1
0.2
0.3
0.4
0.5
0.6
I/O HIGH VOLTAGE
vs
TEMPERATURE
300
VCC – VOH (V)
250
200
VCC = 1.8 V, ISOURCE = 10 mA
150
100
50
0
–40
VCC = 5.0 V, ISOURCE = 10 mA
–15
10
35
60
Temperature, TA (°C)
16
VCC = 5.0 V
70
60
TA = –40°C
50
40
30
TA = 25°C
TA = 85°C
20
10
0
0.0
0.1
0.2
0.3
0.4
VCCP – VOH (V)
VCCP – VOH (V)
VCCP – VOH (V)
80
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0.5
0.6
TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
PARAMETER MEASUREMENT INFORMATION
VCCI
R L = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
(see Figure 9)
Address
Bit 7
(MSB)
Stop
Start
Condition Condition
(P)
(S)
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 ´ VCCI
SCL
0.3 ´ VCCI
ticr
tsp
ticf
tbuf
tvd
tocf
tvd
tsts
tsps
SDA
0.7 ´ VCCI
0.3 ´ VCCI
ticr
ticf
tsth
tsdh
tsds
tvd(ack)
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
2
1
I C address
2
Input register port data
A.
CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
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TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VCCI
RL = 4.7 kW
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
0
1
0
0
0
0
AD
DR
1
A
1
2
3
4
5
6
7
8
A
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
tiv
A
tsps
A
Data
Into
Port
Address
Data 1
0.5 ´ VCCI
INT
SCL
Data 2
0.7 ´ VCCI
R/W
tiv
A
0.3 ´ VCCI
tir
0.5 ´ VCCP
Pn
0.5 ´ VCCI
INT
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
18
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TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Pn
500 W
DUT
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P PORT LOAD CONFIGURATION
SCL
P0
A
P3
0.7 ´ VCCP
0.3 ´ VCCI
Slave
ACK
SDA
tpv
(see Note B)
Pn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
SCL
0.7 ´ VCCI
P0
A
tps
P3
0.3 ´ VCCI
tph
Pn
0.5 ´ VCCP
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 12. P Port Load Circuit and Timing Waveforms
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TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VCCI
RL = 1 kW
Pn
SDA
500 W
DUT
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 ´ VCCI
tRESET
VCCP/2
RESET
tREC
tREC
tW
VCCP/2
Pn
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
20
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TCA6408
LOW-VOLTAGE 8-BIT
AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
APPLICATION INFORMATION
Figure 14 shows an application in which the TCA6408 can be used.
VCCI VCCP
VCCI
(1.8 V)
14
SCL
Master
Controller SDA
15
13
INT
GND
16
1
10 kW
(x 4)
VCC
3
RESET
100 kW (x 3)
VCCI VCCP
SCL
P0
SDA
ALARM
(see note D)
Subsystem 1
(e.g., Alarm)
4
INT
RESET
A
5
P1
TCA6408
ENABLE
B
P2
2
ADDR
P3
P4
P5
P6
P7
6
7
9
Keypad
10
11
12
GND
8
A.
Device address configured as 0100000 for this example.
B.
P0 and P2–P4 are configured as inputs.
C.
P1 and P5-P7 are configured as outputs.
D.
Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a
resistor is not needed. Outputs (in the P port) do not need pullup resistors.
Figure 14. Typical Application
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TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
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SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
APPLICATION INFORMATION (continued)
Minimizing ICC When the I/O is Used to Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 14. The LED acts as a diode so when the LED is off the I/O VIN is about 1.2 V less than VCC. The ∆ICC
parameter in "Electrical Characteristics" shows how ICC increases as VIN becomes lower than VCC. Designs
needing to minimize current consumption, such as battery power applications, should consider maintaining the
I/O pins greater than or equal to VCC when the LED is off.
Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
VCC
LED
100 kΩ
VCC
Px
Figure 15. High-Value Resistor in Parallel With the LED
3.3 V
5V
LED
VCC
Px
Figure 16. Device Supplied by a Low Voltage
22
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TCA6408PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TCA6408PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TCA6408PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TCA6408PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TCA6408RGTR
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TCA6408RGTRG4
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TCA6408ZXYR
ACTIVE
ZXY
20
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BGA MI
CROSTA
R JUNI
OR
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TCA6408PWR
TCA6408RGTR
TCA6408ZXYR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TSSOP
PW
16
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ZXY
20
2500
330.0
12.4
2.8
3.3
1.0
4.0
12.0
Q2
BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TCA6408PWR
TSSOP
PW
16
2000
346.0
346.0
29.0
TCA6408RGTR
QFN
RGT
16
3000
346.0
346.0
29.0
TCA6408ZXYR
BGA MICROSTAR
JUNIOR
ZXY
20
2500
340.5
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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