TI PCA9555PW

PCA9555
www.ti.com ......................................................................................................................................................... SCPS131E – AUGUST 2005 – REVISED MAY 2008
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
FEATURES
1
•
•
•
•
Polarity Inversion Register
Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
INT
A1
A2
P00
P01
P02
P03
P04
P05
P06
P07
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
RGE PACKAGE
(TOP VIEW)
A2
A1
INT
VCC
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
SDA
SCL
•
•
•
•
•
•
Low Standby-Current Consumption of
1 µA Max
I2C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
5-V Tolerant I/O Ports
Compatible With Most Microcontrollers
400-kHz Fast I2C Bus
Address by Three Hardware Address Pins for
Use of up to Eight Devices
24 23 22 21 20 19
P00
P01
P02
P03
P04
P05
1
18 A0
2
3
17 P17
16 P16
4
5
15 P15
14 P14
13 P13
6
7 8 9 10 11 12
P06
P07
GND
P10
P11
P12
•
DESCRIPTION/ORDERING INFORMATION
This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock
(SCL), serial data (SDA)].
The PCA9555 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active high or active low operation) registers. At power on, the I/Os are configured as inputs. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input or Output register. The polarity of the Input Port register
can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the PCA9555 in the event of a timeout or other improper operation by utilizing the
power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine.
The PCA9555 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9555 can remain a simple slave device.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated
PCA9555
SCPS131E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The device outputs (latched) have high-current drive capability for directly driving LEDs.
Although pin-to-pin and I2C-address is compatible with the PCF8575, software changes are required due to the
enhancements.
The PCA9555 is identical to the PCA9535, except for the inclusion of the internal I/O pullup resistor, which pulls
the I/O to a default high when configured as an input and undriven.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus. The fixed I2C address of the PCA9555 is the same as the
PCF8575, PCF8575C, and PCF8574, allowing up to eight of these devices in any combination to share the same
I2C bus or SMBus.
ORDERING INFORMATION
TA
PACKAGE
SSOP – DB
–40°C to 85°C
(1) (2)
PCA9555DBR
Tube of 60
PCA9555DB
Reel of 2500
TVSOP – DGV
Reel of 2000
PCA9555DGVR
Tube of 25
PCA9555DW
Reel of 2000
PCA9555DWR
Reel of 250
PCA9555DWT
SOIC – DW
TSSOP – PW
QFN – RGE
2
Reel of 2000
TOP-SIDE MARKING
PD9555
PCA9555DBQR
QSOP – DBQ
Tube of 60
(1)
(2)
ORDERABLE PART NUMBER
Reel of 2000
PCA9555DBQRG4
PCA9555
PD9555
PCA9555
PCA9555PW
PCA9555PWE4
PCA9555PWR
PD9555
PCA9555PWRE4
Reel of 250
PCA9555PWT
Reel of 3000
PCA9555RGER
PD9555
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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TERMINAL FUNCTIONS
NO.
SOIC (D),
SSOP (DB),
QSOP (DBQ),
TSSOP (PW), AND
TVSOP (DGV)
QFN (RGE)
1
22
INT
Interrupt output. Connect to VCC through a pullup resistor.
2
23
A1
Address input 1. Connect directly to VCC or ground.
3
24
A2
Address input 2. Connect directly to VCC or ground.
4
1
P00
P-port input/output. Push-pull design structure.
5
2
P01
P-port input/output. Push-pull design structure.
6
3
P02
P-port input/output. Push-pull design structure.
7
4
P03
P-port input/output. Push-pull design structure.
8
5
P04
P-port input/output. Push-pull design structure.
9
6
P05
P-port input/output. Push-pull design structure.
10
7
P06
P-port input/output. Push-pull design structure.
11
8
P07
P-port input/output. Push-pull design structure.
12
9
GND
Ground
13
10
P10
P-port input/output. Push-pull design structure.
14
11
P11
P-port input/output. Push-pull design structure.
15
12
P12
P-port input/output. Push-pull design structure.
16
13
P13
P-port input/output. Push-pull design structure.
17
14
P14
P-port input/output. Push-pull design structure.
18
15
P15
P-port input/output. Push-pull design structure.
19
16
P16
P-port input/output. Push-pull design structure.
20
17
P17
P-port input/output. Push-pull design structure.
21
18
A0
Address input 0. Connect directly to VCC or ground.
22
19
SCL
Serial clock bus. Connect to VCC through a pullup resistor.
23
20
SDA
Serial data bus. Connect to VCC through a pullup resistor.
24
21
VCC
Supply voltage
NAME
DESCRIPTION
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LOGIC DIAGRAM (POSITIVE LOGIC)
INT
A0
A1
A2
SCL
SDA
PCA9555
1
Interrupt
Logic
LP Filter
21
2
P07−P00
3
22
23
Input
Filter
I2C Bus
Control
Shift
Register
16 Bits
I/O
Port
P17−P10
Write Pulse
VCC
GND
4
Read Pulse
24
12
Power-On
Reset
A.
Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
B.
All I/Os are set to inputs at reset.
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SIMPLIFIED SCHEMATIC OF P-PORT I/Os(1)
Data From
Shift Register
Output Port
Register Data
Configuration
Register
Data From
Shift Register
D
Q
FF
Write Configuration
Pulse
VCC
Q1
CLK Q
Write Pulse
100 kW
D
Q
FF
I/O Pin
CLK Q
Output Port
Register
Q2
Input Port
Register
D
Q
FF
Read Pulse
GND
Input Port
Register Data
CLK Q
To INT
Data From
Shift Register
D
Q
Polarity
Register Data
FF
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
(1)
At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input
voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte
is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address.
After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during
the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed
between the Start and Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 2. Bit Transfer
6
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Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 3. Acknowledgment on I2C Bus
Interface Definition
BYTE
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C slave address
L
H
L
L
A2
A1
A0
R/W
P0x I/O data bus
P07
P06
P05
P04
P03
P02
P01
P00
P1x I/O data bus
P17
P16
P15
P14
P13
P12
P11
P10
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Device Address
Figure 4 shows the address byte of the PCA9555.
R/W
Slave Address
0
1
0
0 A2 A1 A0
Fixed
Programmable
Figure 4. PCA9555 Address
Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
A1
A0
L
L
L
32 (decimal), 20 (hexadecimal)
L
L
H
33 (decimal), 21 (hexadecimal)
L
H
L
34 (decimal), 22 (hexadecimal)
L
H
H
35 (decimal), 23 (hexadecimal)
H
L
L
36 (decimal), 24 (hexadecimal)
H
L
H
37 (decimal), 25 (hexadecimal)
H
H
L
38 (decimal), 26 (hexadecimal)
H
H
H
39 (decimal), 27 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9555. Three bits of this data byte state the operation (read or write) and
the internal register (input, output, polarity inversion, or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
0
0
0
0
0
B2
B1
B0
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
8
B2
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0
0x00
Input Port 0
Read byte
xxxx xxxx
0
0
1
0x01
Input Port 1
Read byte
xxxx xxxx
0
1
0
0x02
Output Port 0
Read/write byte
1111 1111
0
1
1
0x03
Output Port 1
Read/write byte
1111 1111
1
0
0
0x04
Polarity Inversion Port 0
Read/write byte
0000 0000
1
0
1
0x05
Polarity Inversion Port 1
Read/write byte
0000 0000
1
1
0
0x06
Configuration Port 0
Read/write byte
1111 1111
1
1
1
0x07
Configuration Port 1
Read/write byte
1111 1111
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Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to
these registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the the I2C device that
the Input Port register will be accessed next.
Registers 0 and 1 (Input Port Registers)
Bit
Default
Bit
Default
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
X
X
X
X
X
X
X
I0.0
X
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
X
X
X
X
X
X
X
X
The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Registers 2 and 3 (Output Port Registers)
Bit
Default
Bit
Default
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
1
1
1
1
1
1
1
O0.0
1
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
1
1
1
1
1
1
1
1
The Polarity Inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the
Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Registers 4 and 5 (Polarity Inversion Registers)
Bit
Default
Bit
Default
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
0
0
0
0
0
0
0
0
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
0
0
0
0
0
0
0
0
The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is
set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this
register is cleared to 0, the corresponding port pin is enabled as an output.
Registers 6 and 7 (Configuration Registers)
Bit
Default
Bit
Default
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
1
1
1
1
1
1
1
1
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
1
1
1
1
1
1
1
1
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9555 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released and the PCA9555 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
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Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read
mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read
independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pullup resistor to VCC.
Bus Transactions
Data is exchanged between the master and the PCA9555 through write and read commands.
Writes
Data is transmitted to the PCA9555 by sending the device address and setting the least-significant bit to a logic 0
(see Figure 4 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte.
The eight registers within the PCA9555 are configured to operate as four register pairs. The four pairs are input
ports, output ports, polarity inversion ports, and configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent
to output port (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
1
SCL
2
3
4
5
6
7
8
9
Command Byte
Slave Address
SDA
S
0
1
0
0
A2 A1 A0
0
A
0
0
0
0
0
0
Data to Port 0
1
R/W Acknowledge
From Slave
Start Condition
0.7
A
0
Data to Port 1
0.0
Data 0
Acknowledge
From Slave
A 1.7
1.0
Data 1
A
P
Acknowledge
From Slave
Write to Port
Data Out from Port 0
tpv
Data Valid
Data Out from Port 1
tpv
Figure 6. Write to Output Port Registers
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Slave Address
SDA
S
0
1
0
Start Condition
0
A2 A1 A0
4
5
6
7
8
9
1
2
3
Command Byte
0
R/W
A
0
0
0
Acknowledge
From Slave
0
0
1
1
4
5
6
7
8
9
1
2
3
Data to Register
0
A MSB
Data 0
4
5
Data to Register
LSB
Acknowledge
From Slave
A MSB
Data 1
LSB
A
P
Acknowledge
From Slave
Figure 7. Write to Configuration Registers
10
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Reads
The bus master first must send the PCA9555 address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9555 (see Figure 8 through Figure 10).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Slave Address
S
0
1
0
0
A2
Acknowledge
From Slave
A1 A0
0
Slave Address
Acknowledge
From Slave
Command Byte
A
A
R/W
S
0
1
0
0
Data From Lower
or Upper Byte
of Register
Acknowledge
From Slave
A2 A1 A0
1
Data
A MSB
LSB
A
First Byte
R/W
At this moment, master transmitter
becomes master receiver, and
slave-receiver becomes
slave-transmitter.
Acknowledge
From Master
Data From Upper
or Lower Byte
of Register
MSB
No Acknowledge
From Master
LSB NA
Data
P
Last Byte
Figure 8. Read From Register
1
SCL
2
3
4
5
6
7
8
9
I0.x
SDA
S
0
1
0
0
A2
A1
A0
1
A
7
6
5
4
3
I1.x
2
Acknowledge
R/W
From Slave
1
0
A
7
6
5
Acknowledge
From Master
4
3
I0.x
2
1
0
A
7
6
5
4
3
I1.x
2
1
0
A
7
6
5
4
3
2
1
Acknowledge
From Master
Acknowledge
From Master
0
1
P
No Acknowledge
From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
tiv
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 9. Read Input Port Register, Scenario 1
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1
SCL
2
3
4
5
6
7
8
9
I0.x
SDA
S
0
1
0
0
A2
A1
A0
1
R/W
A
00
Acknowledge
From Slave
I1.x
A
10
I0.x
A
03
Acknowledge
From Master
Acknowledge
From Master
I1.x
A
12
P
No Acknowledge
From Master
tps
tph
1
Acknowledge
From Master
Read From Port 0
Data Into Port 0
Data 00
Data 01
Data 02
Data 03
tph
tps
Read From Port 1
Data 10
Data Into Port 1
Data 11
Data 12
INT
tiv
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 10. Read Input Port Register, Scenario 2
12
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6
V
VI
Input voltage range (2)
–0.5
6
V
(2)
VO
Output voltage range
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
θJA
–0.5
Continuous current through GND
–250
Continuous current through VCC
160
Package thermal impedance, junction to free air (3)
θJP
Package thermal impedance, junction to pad
Tstg
Storage temperature range
(1)
(2)
(3)
6
UNIT
DB package
63
DBQ package
61
DGV package
86
DW package
46
PW package
88
V
mA
°C/W
RGE package
45
RGE package
1.5
°C/W
150
°C
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
2.3
5.5
SCL, SDA
0.7 × VCC
5.5
A2–A0, P07–P00, P17–P10
0.7 × VCC
5.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, P07–P00, P17–P10
–0.5
0.3 × VCC
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P07–P00, P17–P10
–10
mA
IOL
Low-level output current
P07–P00, P17–P10
25
mA
TA
Operating free-air temperature
85
°C
–40
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V
V
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
VCC
MIN
2.3 V to 5.5 V
–1.2
VPOR
IOH = –8 mA
P-port high-level output voltage (2)
VOH
IOH = –10 mA
2.3 V
1.8
3V
2.6
4.75 V
4.1
2.3 V
1.7
3V
2.5
4.75 V
SDA
VOL = 0.4 V
VOL = 0.5 V
P port (3)
IOL
VOL = 0.7 V
INT
A2–A0
2.3 V to 5.5 V
VI = VCC or GND
2.3 V to 5.5 V
P port
VI = VCC
2.3 V to 5.5 V
IIL
P port
VI = GND
2.3 V to 5.5 V
ICC
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz, No load
Low inputs
VI = GND, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load
Standby mode
High inputs
VI = VCC, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load
24
mA
±1
±1
µA
–100
µA
20
50
5.5 V
1.1
1.5
3.6 V
0.7
1.3
2.7 V
0.5
1
5.5 V
0.5
1
3.6 V
0.4
0.9
2.7 V
0.25
0.8
2.3 V to 5.5 V
2.3 V to 5.5 V
µA
1
2.7 V
VI = VCC or GND
14
20
75
SCL
(3)
8
10
30
CI
(1)
(2)
4
3.6 V
2.3 V to 5.5 V
VIO = VCC or GND
V
V
200
One input at VCC – 0.6 V,
Other inputs at VCC or GND
P port
V
100
Additional current in standby
mode
Cio
1.65
5.5 V
ΔICC
SDA
1.5
UNIT
3
IIH
Operating mode
MAX
3
VOL = 0.4 V
SCL, SDA
II
TYP (1)
µA
mA
µA
1.5
mA
3
7
pF
3
7
3.7
9.5
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum
current of 100 mA, for a device total of 200 mA.
The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
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I2C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11)
fscl
I2C clock frequency
tsch
I2C clock high time
I C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
MAX
UNIT
0
400
kHz
µs
0.6
2
tscl
MIN
µs
1.3
50
100
2
ns
ns
tsdh
I C serial-data hold time
ticr
I2C input rise time
20 + 0.1Cb (1)
300
ns
ticf
I2C input fall time
20 + 0.1Cb (1)
300
ns
(1)
300
2
0
10-pF to 400-pF bus
20 + 0.1Cb
ns
tocf
I C output fall time
tbuf
I2C bus free time between Stop and Start
1.3
µs
tsts
I2C Start or repeated Start condition setup
0.6
µs
tsth
I2C Start or repeated Start condition hold
0.6
µs
0.6
µs
2
tsps
I C Stop condition setup
tvd(Data)
Valid-data time
SCL low to SDA output valid
50
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low to SDA (out) low
0.1
Cb
I2C bus capacitive load
(1)
ns
ns
0.9
µs
400
pF
Cb = total capacitance of one bus line in pF
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 12 and Figure 13)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
MIN
MAX
UNIT
4
µs
4
µs
200
ns
tiv
Interrupt valid time
tir
Interrupt reset delay time
SCL
INT
tpv
Output data valid
SCL
P port
tps
Input data setup time
P port
SCL
150
ns
tph
Input data hold time
P port
SCL
1
µs
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TYPICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
SUPPLY CURRENT
vs
TEMPERATURE
STANDBY SUPPLY CURRENT
vs
TEMPERATURE
55
70
30
SCL = V CC
50
V CC = 5 V
ICC – Supply Current – nA
40
f SCL = 400 kHz
I/Os Unloaded
35
30
25
V CC = 3.3 V
20
15
10
V CC = 2.5 V
5
0
-50
f SCL = 400 kHz
I/Os Unloaded
60
25
ICC – Supply Current – µA
45
ICC – Supply Current – µA
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
20
V CC = 5 V
15
V CC = 3.3 V
10
40
30
20
10
V CC = 2.5 V
5
50
0
-25
0
25
50
75
0
-50
100
TA – Free-Air Tem perature – °C
2.3
-25
0
25
50
75
2.7
3.1
100
3.5
3.9
4.3
4.7
5.1
5.5
V CC – Supply Voltage – V
TA – Free-Air Tem perature – °C
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
30
50
40
V CC = 3.3 V
V CC = 2.5 V
TA = –40°C
20
TA = 25°C
15
10
TA = 125°C
25
TA = 25°C
20
15
10
TA = 125°C
5
5
0.1
0.2
0.3
0.4
0.5
0.1
I/O OUTPUT LOW VOLTAGE
vs
TEMPERATURE
ISOURCE – I/O Source Current – mA
V OL – Output Low Voltage – mV
0.3
0.4
0.5
200
V CC = 5 V, ISINK = 10 m A
150
125
100
V CC = 2.5 V, ISINK = 1 m A
50
V CC = 5 V, ISINK = 1 m A
25
15
10
TA = 125°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
V OL – Output Low Voltage – V
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
50
TA = –40°C
25
TA = 25°C
20
V CC = 3.3 V
45
30
15
10
TA = 125°C
5
TA = –40°C
40
35
TA = 25°C
30
25
20
15
10
TA = 125°C
5
0
0.0
-25
0
25
50
75
100
0.1
0.2
0.3
0.4
0.5
0.6
(V CC – V OH) – V
0.7
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(V CC – V OH) – V
TA – Free-Air Tem perature – °C
16
0.6
V CC = 2.5 V
225
0
-50
0.2
35
V CC = 2.5 V, ISINK = 10 m A
250
75
20
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
300
175
25
V OL – Output Low Voltage – V
V OL – Output Low Voltage – V
275
TA = 25°C
30
0
0.0
0.6
ISOURCE – I/O Source Current – mA
0.0
35
5
0
0
TA = –40°C
40
30
ISINK – I/O Sink Current – mA
ISINK – I/O Sink Current – mA
TA = –40°C
V CC = 5 V
45
35
25
ISINK – I/O Sink Current – mA
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
SUPPLY CURRENT
vs
NUMBER OF I/Os HELD LOW
300
V CC = 5 V
V OH – Output High Voltage – mV
TA = 25°C
35
30
25
20
15
TA = 125°C
10
5
0
0.0
0.1
0.2
0.3
0.4
1100
250
TA = –40°C
60
55
50
45
40
1200
275
0.5
0.6
225
200
175
150
V CC = 5 V, IOL = 10 m A
125
100
75
800
700
600
TA = 25°C
500
400
300
200
25
100
TA = 125°C
0
0
-50
(V CC – V OH) – V
TA = –40°C
900
50
0.7
V CC = 5 V
1000
V CC = 2.5 V, IOL = 10 m A
ICC – Supply Current – µA
75
70
65
ISOURCE – I/O Source Current – mA
I/O HIGH VOLTAGE
vs
TEMPERATURE
-25
0
25
50
75
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Num ber of I/Os Held Low
TA – Free-Air Tem perature – °C
OUTPUT HIGH VOLTAGE
vs
SUPPLY VOLTAGE
6
V OH – Output High Voltage – V
TA = 25°C
5
4
IOH = –8 m A
3
IOH = –10 m A
2
1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
V CC – Supply Voltage – V
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PARAMETER MEASUREMENT INFORMATION
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
ticf
tbuf
tsts
tPHL
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 11. I2C Interface Load Circuit and Voltage Waveforms
18
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
16 Bits
(Two Data Bytes)
From Port
R/W
Slave Address (PCA9555)
S
0
1
0
0 A2 A1 A0 1
A
1
2
3
4
A
5
6
7
8
Data 1
ACK
From Slave
Data 2
Data From Port
A
Data 3
1
P
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
0.3 × VCC
SCL
Data 2
Data 3
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
INT
0.3 × VCC
0.3 × VCC
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 12. Interrupt Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
DUT
Pn
CL = 100 pF
GND
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P00
A
P17
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note A)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P00
A
tps
P17
0.3 × VCC
tph
0.7 × VCC
Pn
0.3 × VCC
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 13. P-Port Load Circuit and Voltage Waveforms
20
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 1 kΩ
DUT
SDA
DUT
CL = 100 pF
CL = 50 pF
SDA LOAD CONFIGURATION
Pn
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y VCC
tREC
RESET
VCC/2
tREC
tw
Pn
VCC/2
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 14. Reset Load Circuits and Voltage Waveforms
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APPLICATION INFORMATION
Figure 15 shows an application in which the PCA9555 can be used.
Subsystem 1
(e.g., Temperature
Sensor)
INT
VCC
(5 V)
VCC
10 kW
10 kW
10 kW
24
10 kW
22
SCL
Master
Controller SDA
23
1
INT
Subsystem 2
(e.g., Counter)
2 kW
VCC
SCL
SDA
INT
P00
P01
P02
P03
GND
P04
P05
RESET
4
5
A
6
7
ENABLE
8
9
B
PCA9555
VCC
P06
P07
3
A2
P10
P11
2
A1
P12
P13
21
A0
P14
P15
P16
GND P17
12
A.
Device address is configured as 0100100 for this example.
B.
P00, P02, and P03 are configured as outputs.
C.
P01, P04–P07, and P10–P17 are configured as inputs.
D.
Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
10
11
13
14
15
16
17
18
19
20
Controlled Switch
(e.g., CBT Device)
ALARM
Keypad
Subsystem 3
(e.g., Alarm)
Figure 15. Typical Application
22
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Minimizing ICC When I/O Is Used to Control LED
When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 15.
Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For
battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when the
LED is off to minimize current consumption.
Figure 16 shows a high-value resistor in parallel with the LED. Figure 17 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
VCC
LED
100 kW
VCC
Pn
Figure 16. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
Pn
Figure 17. Device Supplied by Lower Voltage
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PACKAGE OPTION ADDENDUM
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24-Jun-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PCA9555DB
ACTIVE
SSOP
DB
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DBG4
ACTIVE
SSOP
DB
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DBQR
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PCA9555DBQRG4
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PCA9555DBR
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DBRG4
ACTIVE
SSOP
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DGVR
ACTIVE
TVSOP
DGV
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DGVRG4
ACTIVE
TVSOP
DGV
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555DWRG4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555PWE4
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555PWG4
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555PWR
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555PWRE4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555PWRG4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9555RGER
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PCA9555RGERG4
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2009
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCA9555DBQR
Package Package Pins
Type Drawing
SSOP/
QSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
PCA9555DBR
SSOP
DB
24
2000
330.0
16.4
8.2
8.8
2.5
12.0
16.0
Q1
PCA9555DGVR
TVSOP
DGV
24
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
PCA9555DWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
PCA9555PWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
PCA9555RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9555DBQR
SSOP/QSOP
DBQ
24
2500
346.0
346.0
33.0
PCA9555DBR
SSOP
DB
24
2000
346.0
346.0
33.0
PCA9555DGVR
TVSOP
DGV
24
2000
346.0
346.0
29.0
PCA9555DWR
SOIC
DW
24
2000
346.0
346.0
41.0
PCA9555PWR
TSSOP
PW
24
2000
346.0
346.0
33.0
PCA9555RGER
VQFN
RGE
24
3000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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