SCLS554A − JANUARY 2004 − REVISED MARCH 2004
D Qualification in Accordance With
D OR PW PACKAGE
(TOP VIEW)
AEC-Q100†
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
D
D
D
D
D
Y4
Y6
COM
Y7
Y5
INH
NC
GND
Can Be Supported Along With
Major-Change Approval
Injection-Current Cross Coupling <1mV/mA
(see Figure 1)
Low Crosstalk Between Switches
Pin Compatible With CD74HC4051,
SN74LV4051A, and CD4051B
2-V to 6-V VCC Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
Y2
Y1
Y0
Y3
A
B
C
NC − No internal connection
† Contact factory for details. Q100 qualification data available on
request.
description/ordering information
This eight-channel CMOS analog multiplexer/demultiplexer is pin compatible with the ’4051 function and,
additionally, features injection-current effect control, which has excellent value in automotive applications where
voltages in excess of normal supply voltages are common.
The injection-current effect control allows signals at disabled analog input channels to exceed the supply
voltage without affecting the signal of the enabled analog channel. This eliminates the need for external
diode/resistor networks typically used to keep the analog channel signals within the supply-voltage range.
ORDERING INFORMATION
−40°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
SOIC − D
Tape and reel
SN74HC4851QDRQ1
TSSOP − PW
Tape and reel
SN74HC4851QPWRQ1
HC4851Q
HC4851Q
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
B
A
ON
CHANNEL
INH
C
L
L
L
L
Y0
L
L
L
H
Y1
L
L
H
L
Y2
L
L
H
H
Y3
L
H
L
L
Y4
L
H
L
H
Y5
L
H
H
L
Y6
L
H
H
H
Y7
H
X
X
X
None
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
POST OFFICE BOX 655303
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1
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
logic diagram (positive logic)
Injection−
Current
Control
Injection−
Current
Control
11
3
13
COM
Y0
Injection−
Current
Control
14
Injection−
Current
Control
15
Injection−
Current
Control
12
Y3
Injection−
Current
Control
1
Y4
Injection−
Current
Control
5
Injection−
Current
Control
2
Y1
A
B
C
INH
2
10
9
Injection−
Current
Control
6
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4
Y2
Y5
Y6
Y7
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I/O diode current, IIOK (VIO < 0 or VIO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
VCC
VIH
Supply voltage
2
High-level input voltage,
control inputs
VCC = 2 V
VCC = 3 V
1.5
VCC = 3.3 V
VCC = 4.5 V
2.3
VCC = 6 V
VCC = 2 V
VIL
VI
VIO
Low-level input voltage,
control inputs
V
V
3.15
4.2
0.5
VCC = 4.5 V
VCC = 6 V
1.35
1
V
1.8
0
Input/output voltage
UNIT
2.1
0.9
Control input voltage
0
Input transition rise or fall time
6
VCC = 3 V
VCC = 3.3 V
VCC = 2 V
VCC = 3 V
∆t/∆v
MAX
VCC
VCC
V
V
1000
800
VCC = 3.3 V
VCC = 4.5 V
700
VCC = 6 V
400
ns
500
TA
Operating free-air temperature
−40
125
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
ron
∆ron
II
IS(off)
IS(on)
ICC
CIC
On-state
switch resistance
Difference in
on-state resistance
between switches
Control input current
TEST CONDITIONS
IT ≤ 2 mA,
VI = VCC to GND,
VINH = VIL
(see Figure 5)
IT ≤ 2 mA,
VI = VCC/2,
VINH = VIL
Off-state switch
leakage current
(any one channel)
VI = VCC or GND
VI = VCC or GND,
VINH = VIH
(see Figure 6)
Off-state switch
leakage current
(common channel)
VI = VCC or GND,
VINH = VIH
(see Figure 7)
On-state switch
leakage current
VI = VCC or GND,
VINH = VIL
(see Figure 8)
Supply current
Control input capacitance
VI = VCC or GND
A, B, C, INH
VCC
MIN
TA = 25°C
TYP
MAX
UP TO 85°C
MIN
MAX
UP TO 125°C
MIN
MAX
2.V
500
650
670
700
3V
215
280
320
360
3.3 V
210
270
305
345
4.5 V
160
210
240
270
6V
150
195
220
250
2.V
4
13
18
23
3V
2
10
12
16
3.3 V
2
9
12
16
4.5 V
2
9
12
16
6V
3
10
14
19
±0.1
±0.1
±1
±0.1
±0.5
±1
6V
UNIT
Ω
Ω
µA
µA
A
6V
6V
±0.2
±2
±4
±0.1
±0.5
±1
µA
2
20
40
µA
3.5
10
10
10
pF
6V
CIS
Common terminal
capacitance
Switch off
22
40
40
40
pF
COS
Switch terminal capacitance
Switch off
6.7
15
15
15
pF
injection current coupling specifications, TA = −40°C to 125°C
PARAMETER
VCC
3.3 V
5V
3.3 V
V∆out
Maximum shift of output voltage of enabled analog
channel
TEST CONDITIONS
II‡ ≤ 1 mA
RS ≤ 3.9 kΩ
II‡ ≤ 10 mA
5V
3.3 V
5V
3.3 V
II‡ ≤ 1 mA
RS ≤ 20 kΩ
5V
† Typical values are measured at TA = 25°C.
‡ II = total current injected into all disabled channels
4
POST OFFICE BOX 655303
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II‡ ≤ 10 mA
MIN
TYP†
MAX
0.05
1
0.1
1
0.345
5
0.067
5
0.05
2
0.11
2
0.05
20
0.024
20
UNIT
mV
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
switching characteristics over recommended operating free-air temperature range,
VCC = 2 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
UP TO 85°C
MIN
MAX
UP TO 125°C
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
19.5
30
34
37
ns
tPLH
tPHL
Propagation
delay time
A, B, C
COM or Yn
23
35
40
45
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
95
105
115
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
95
105
115
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
MAX
UP TO 85°C
MIN
MAX
UP TO 125°C
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
12
17.5
19.5
21.5
ns
tPLH
tPHL
Propagation
delay time
A, B, C
COM or Yn
13.5
19.5
22
25
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
90
100
110
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
90
100
110
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
UP TO 85°C
MIN
MAX
UP TO 125°C
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
11
16.5
18.5
20.5
ns
tPLH
tPHL
Propagation
delay time
A, B, C
COM or Yn
12.5
18.5
21
24
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
85
95
105
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
85
95
105
ns
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5
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
switching characteristics over recommended operating free-air temperature range,
VCC = 4.5 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
UP TO 85°C
MIN
MAX
UP TO 125°C
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
8.6
14
15
16
ns
tPLH
tPHL
Propagation
delay time
A, B, C
COM or Yn
10
16
18
20
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
80
90
100
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
80
90
100
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 6 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
MAX
UP TO 85°C
MIN
MAX
UP TO 125°C
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
8
12.5
13.5
14.5
ns
tPLH
tPHL
Propagation
delay time
A, B, C
COM or Yn
9.5
15
17
19
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
78
80
80
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
78
80
80
ns
operating characteristics, TA = 25°C (see Figure 15)
PARAMETER
Cpd
6
Power dissipation capacitance
VCC
3.3 V
5V
POST OFFICE BOX 655303
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TEST CONDITIONS
TYP
UNIT
32
No load
37
pF
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
APPLICATION INFORMATION
VCC = 5 V
IIO
VIN2 < VSS or VCC < VIN2
Any Disabled Channel
VSS < VIN1 < VCC
Enabled Channel
Vout = VI1 V ± V∆out
RS
Figure 1. Injection-Current Coupling Specification
5V
6V
5V
VCC
VCC
’HC4051
Sensor
Channel 1
Channel 2
Microcontroller
Channel 3
Channel 4
Channel 5
Channel 6
(8× Identical
Circuitry)
Channel 7
Channel 8
Common Out
A/D − Input
Figure 2. Alternate Solution Requires 32 Passive Components and One Extra 6-V Regulator
to Suppress Injection Current Into a Standard ’HC4051 Multiplexer
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7
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
APPLICATION INFORMATION
VCC
5V
VCC
’HC4851
Sensor
Channel 1
Channel 2
Channel 3
Microcontroller
Channel 4
Channel 5
Channel 6
(8× Identical
Circuitry)
Channel 7
Channel 8
Common Out
A/D − Input
Figure 3. Solution by Applying the ’HC4851 Multiplexer
Gate = VCC
(Disabled)
Disabled Analog Multiplex Input
VIN > VCC + 0.7 V
Common Analog Output
Vout > VCC
P+
P+
+
+
+
N − Substrate (on VCC potential)
Figure 4. Diagram of Bipolar Coupling Mechanism
(Appears if VIN Exceeds VCC, Driving Injection Current Into the Substrate)
8
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SCLS554A − JANUARY 2004 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIL
VCC
VI = VCC to GND
VO
(ON)
GND
r on +
VI – VO
W
IT
IT
V
VI − VO
Figure 5. On-State-Resistance Test Circuit
VCC
16
GND
VCC
OFF
A
VCC
OFF
NC
VINH = VIH
Common O/I
6
8
Figure 6. Maximum Off-Channel Leakage Current, Any One Channel, Test Setup
VCC
VCC
16
GND
VCC
VCC
16
A
ON
Analog I/O
OFF
GND
OFF
VCC
OFF
Common O/I
VCC
VINH =VIH
NC
Common O/I
6
Analog I/O
VINH = VIL
8
6
8
Figure 7. Maximum Off-Channel Leakage Current,
Common Channel, Test Setup
POST OFFICE BOX 655303
Figure 8. Maximum On-Channel Leakage Current,
Channel to Channel, Test Setup
• DALLAS, TEXAS 75265
9
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VCC
16
VCC
Common O/I
ON/OFF
Analog I/O
OFF/ON
CL†
Test
Point
VCC
Channel
Select
50%
GND
tPLH
6
tPHL
8
Analog
Out
50%
Channel Select
† Includes all probe and jig capacitance
Figure 10. Propagation-Delay Test Setup,
Channel Select to Analog Out
Figure 9. Propagation Delays,
Channel Select to Analog Out
VCC
16
Analog I/O
ON
Common O/I
Test
Point
CL†
VCC
Analog In
50%
GND
tPLH
Analog Out
6
tPHL
8
50%
† Includes all probe and jig capacitance
Figure 11. Propagation Delays,
Analog In to Analog Out
10
POST OFFICE BOX 655303
Figure 12. Propagation-Delay Test Setup,
Analog In to Analog Out
• DALLAS, TEXAS 75265
SCLS554A − JANUARY 2004 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
tf
tf
Enable
tPZL
Position 1 when testing tPHZ and tPZH
Position 2 when testing tPLZ and tPZL
1
2
GND
16
VCC
Analog I/O
1
High
Impedance
VCC
10 kΩ
tPLZ
50 %
Analog
Out
ON/OFF
2
CL
10%
Test
Point
VOL
tPZH
Analog
Out
VCC
90%
50%
10%
tPHZ
50 %
90%
Enable
VOH
6
8
High
Impedance
Figure 14. Propagation-Delay Test Setup,
Enable to Analog Out
Figure 13. Propagation Delays,
Enable to Analog Out
A VCC
16
VCC
ON/OFF
Common O/I
NC
Analog I/O
OFF/ON
VCC
6
11
8
Channel Select
Figure 15. Power-Dissipation Capacitance Test Setup
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11
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74HC4851QDRQ1
ACTIVE
SOIC
D
16
2500
SN74HC4851QPWRQ1
ACTIVE
TSSOP
PW
16
2000
Lead/Ball Finish
MSL Peak Temp (3)
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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Applications
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amplifier.ti.com
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www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
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www.ti.com/video
Wireless
www.ti.com/wireless
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