SCLS503C − MAY 2003 − REVISED MAY 2004
D Controlled Baseline
D
D
D
D
D
D
D
D
D
D
D
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−40°C to 105°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
2-V to 5.5-V VCC Operation
Supports Mixed-Mode Voltage Operation on
All Ports
High On-Off Output-Voltage Ratio
D
Low Crosstalk Between Switches
Individual Switch Controls
Extremely Low Input Current
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D OR PW PACKAGE
(TOP VIEW)
2Y1
2Y0
3Y1
3-COM
3Y0
INH
GND
GND
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
2-COM
1-COM
1Y1
1Y0
A
B
C
description/ordering information
This triple 2-channel CMOS analog multiplexer/demultiplexer is designed for 2-V to 5.5-V VCC operation.
The SN74LV4053A handles both analog and digital signals. Each channel permits signals with amplitudes up
to 5.5 V (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
−40°C to 105°C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
SOIC − D
Tape and reel
SN74LV4053ATDREP
TOP-SIDE
MARKING
LV4053ATEP
TSSOP − PW Tape and reel
SN74LV4053ATPWREP
L4053EP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS503C − MAY 2003 − REVISED MAY 2004
FUNCTION TABLE
INPUTS
B
A
ON CHANNELS
INH
C
L
L
L
L
1Y0, 2Y0, 3Y0
L
L
L
H
1Y1, 2Y0, 3Y0
L
L
H
L
1Y0, 2Y1, 3Y0
L
L
H
H
1Y1, 2Y1, 3Y0
L
H
L
L
1Y0, 2Y0, 3Y1
L
H
L
H
1Y1, 2Y0, 3Y1
L
H
H
L
1Y0, 2Y1, 3Y1
L
H
H
H
1Y1, 2Y1, 3Y1
H
X
X
X
None
logic diagram (positive logic)
15
14
A
12
2
2
1Y1
2Y0
2Y1
9
5
3
INH
1Y0
10
1
C
1-COM
11
13
B
2-COM
6
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3Y0
3Y1
3-COM
SCLS503C − MAY 2003 − REVISED MAY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
I/O diode current, IIOK (VIO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
VCC
VIH
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level input voltage, control inputs
VIL
Low-level input voltage, control inputs
VI
VIO
Control input voltage
∆t/∆v
MIN
2‡
Supply voltage
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
0.5
VCC × 0.3
VCC × 0.3
0
VCC = 4.5 V to 5.5 V
V
VCC × 0.7
0
Input transition rise or fall rate
UNIT
1.5
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
5.5
VCC × 0.7
VCC × 0.7
VCC = 2 V
VCC = 2.3 V to 2.7 V
Input/output voltage
MAX
VCC × 0.3
5.5
V
V
VCC
200
V
100
ns/V
20
TA
Operating free-air temperature
−40
105
°C
‡ With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
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3
SCLS503C − MAY 2003 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST
CONDITIONS
PARAMETER
On-state switch
resistance
ron
ron(p)
∆ron
VCC
IT = 2 mA, VI = VCC or GND,
VINH = VIL, (see Figure 1)
Peak on-state resistance
IT = 2 mA, VI = VCC to GND,
VINH = VIL
MIN
IT = 2 mA, VI = VCC to GND,
VINH = VIL
MIN
MAX
2.3 V
41
180
225
3V
30
150
190
4.5 V
23
75
100
2.3 V
139
500
600
3V
63
180
225
4.5 V
35
100
125
2.3 V
Difference in on-state
resistance between
switches
TA = 25°C
TYP
MAX
2
30
40
3V
1.6
20
30
4.5 V
1.3
UNIT
Ω
Ω
Ω
15
20
±0.1
±1
µA
II
Control input current
VI = 5.5 V or GND
0 to
5.5 V
IS(off)
Off-state switch leakage
current
VI = VCC and VO = GND, or
VI = GND and VO = VCC,
VINH = VIH, (see Figure 2)
5.5 V
±0.1
±1
µA
IS(on)
On-state switch leakage
current
VI = VCC or GND, VINH = VIH
(see Figure 3)
5.5 V
±0.1
±1
µA
Supply current
VI = VCC or GND
5.5 V
20
µA
ICC
CIC
Control input capacitance
2
pF
CIS
Common terminal
capacitance
8.2
pF
COS
Switch terminal
capacitance
5.6
pF
CF
Feedthrough capacitance
0.5
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
4
TA = 25°C
TYP
MAX
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Yn
Yn or COM
CL = 15 pF,
(see Figure 4)
2.5
10
16
ns
MIN
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
7.6
18
23
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
7.7
18
23
ns
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF,
(see Figure 4)
4.4
12
18
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
8.8
28
35
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
11.7
28
35
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS503C − MAY 2003 − REVISED MAY 2004
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
TA = 25°C
TYP
MAX
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Yn
Yn or COM
CL = 15 pF,
(see Figure 4)
1.6
6
10
ns
MIN
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
5.3
12
15
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
6.1
12
15
ns
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF,
(see Figure 4)
2.9
9
12
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
6.1
20
25
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
8.9
20
25
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
TA = 25°C
TYP
MAX
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or Yn
Yn or COM
CL = 15 pF,
(see Figure 4)
0.9
4
7
ns
MIN
MIN
MAX
UNIT
tPLH
tPHL
Propagation
delay time
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
3.8
8
10
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 15 pF,
(see Figure 5)
4.6
8
10
ns
tPLH
tPHL
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF,
(see Figure 4)
1.8
6
8
ns
tPZH
tPZL
Enable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
4.3
14
18
ns
tPHZ
tPLZ
Disable
delay time
INH
COM or Yn
CL = 50 pF,
(see Figure 5)
6.3
14
18
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCLS503C − MAY 2003 − REVISED MAY 2004
analog switch characteristics
PARAMETER
Frequency response
(switch on)
COM or Yn
Crosstalk
(between any switches)
Crosstalk
(control input to signal
output)
Feedthrough attenuation
(switch off)
Sine-wave distortion
FROM
(INPUT)
COM or Yn
INH
TEST CONDITIONS
VCC
2.3 V
30
Yn or COM
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz (sine wave)
(see Note 5 and Figure 6)
3V
35
4.5 V
50
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz (sine wave)
(see Note 6 and Figure 7)
2.3 V
−45
3V
−45
4.5 V
−45
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz (square wave)
(see Figure 8)
2.3 V
20
3V
35
4.5 V
65
CL = 50 pF,
RL = 600 Ω,,
fin = 1 MHz
(see Note 6 and Figure 9)
2.3 V
−45
3V
−45
4.5 V
−45
CL = 50 pF,
RL = 10 kΩ,
fin = 1 kHz
(sine wave)
(see Figure 10)
2.3 V
0.1
3V
0.1
4.5 V
0.1
Yn or COM
COM or Yn
COM or Yn
COM or Yn
TA = 25°C
MIN
TYP
MAX
TO
(OUTPUT)
Yn or COM
Yn or COM
VI = 2 Vp-p
VI = 2.5 Vp-p
VI = 4 Vp-p
UNIT
MHz
dB
mV
dB
%
NOTES: 5. Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB.
6. Adjust fin voltage to obtain 0-dBm input.
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 10
MHz
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIL
VCC
VI = VCC or GND
VO
(ON)
GND
r on +
2 mA
V
VI − VO
Figure 1. On-State Resistance Test Circuit
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VI – VO
2
10 –3
W
TYP
UNIT
5.3
pF
SCLS503C − MAY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = VIH
VCC
A
VI
VO
(OFF)
GND
Condition 1: VI = 0, VO = VCC
Condition 2: VI = VCC, VO = 0
Figure 2. Off-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VCC
A
VI
Open
(ON)
GND
VI = VCC or GND
Figure 3. On-State Switch Leakage-Current Test Circuit
VCC
VINH = VIH
VCC
Input
Output
(ON)
50 Ω
GND
CL
Figure 4. Propagation Delay Time, Signal Input to Signal Output
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCLS503C − MAY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
50 Ω
VINH
VCC
VI
S1
VO
GND
1 kΩ
S2
TEST
S1
S2
tPLZ/tPZL
tPHZ/tPZH
GND
VCC
VCC
GND
CL
TEST CIRCUIT
VCC
VCC
VINH
50%
50%
0V
0V
tPZL
tPZH
≈VCC
VOH
VO
50%
50%
VOL
≈0 V
(tPZL, tPZH)
VCC
VCC
VINH
50%
50%
0V
0V
tPLZ
tPHZ
≈VCC
VOH
VO
VOL + 0.3 V
VOL
(tPLZ, tPHZ)
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
VCC
VINH = GND
VCC
(ON)
fin
50 Ω
0.1 µF
GND
VO
RL
CL
VCC/2
NOTE A: fin is a sine wave.
Figure 6. Frequency Response (Switch On)
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS503C − MAY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = GND
VCC
(ON)
fin
0.1 µF 600 Ω
50 Ω
VO1
GND
RL
CL
VCC/2
VCC
VINH = VCC
VCC
(OFF)
fin
VO2
GND
600 Ω
RL
CL
VCC/2
Figure 7. Crosstalk Between Any Two Switches
50 Ω
VCC
VINH
VCC
VO
GND
600 Ω
RL
VCC/2
CL
VCC/2
Figure 8. Crosstalk Between Control Input and Switch Output
VCC
VINH = GND
0.1 µF
VCC
(OFF)
fin
50 Ω
600 Ω
GND
VCC/2
VO
RL
CL
VCC/2
Figure 9. Feedthrough Attenuation (Switch Off)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SCLS503C − MAY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
VINH = GND
10 µF
fin
600 Ω
10 µF
VCC
(ON)
VO
GND
RL
VCC/2
Figure 10. Sine-Wave Distortion
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CL
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV4053ATDREP
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV4053ATPWREP
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/03666-01XE
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/03666-01YE
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4053A-EP :
SN74LV4053A
• Catalog:
• Automotive: SN74LV4053A-Q1
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV4053ATDREP
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV4053ATPWREP
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV4053ATDREP
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV4053ATPWREP
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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