SN74AUC16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES390E – MARCH 2002 – REVISED DECEMBER 2002 D D D D D D D D D DGG OR DGV PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 2 ns at 1.8 V Low Power Consumption, 20-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE description/ordering information This 16-bit buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC16240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides inverting outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE† TA –40°C to 85°C ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74AUC16240DGGR AUC16240 TVSOP – DGV Tape and reel SN74AUC16240DGVR MH240 VFBGA – GQL Tape and reel SN74AUC16240GQLR MH240 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AUC16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES390E – MARCH 2002 – REVISED DECEMBER 2002 GQL PACKAGE (TOP VIEW) 1 2 3 4 5 6 terminal assignments 1 2 3 4 5 6 A A 1OE NC NC NC NC 2OE B B 1Y2 1Y1 GND GND 1A1 1A2 C C 1Y4 1Y3 1A4 D 2Y2 2Y1 VCC GND 1A3 D VCC GND 2A1 2A2 E 2Y4 2Y3 2A3 2A4 F 3Y1 3Y2 3A2 3A1 G 3Y3 3Y4 GND GND 3A4 3A3 H 4Y1 4Y2 4A1 4Y3 4Y4 VCC GND 4A2 J VCC GND 4A4 4A3 K 4OE NC NC NC NC 3OE E F G H J K NC – No internal connection FUNCTION TABLE (each 4-bit buffer) INPUTS 2 OE A OUTPUT Y L H L L L H H X Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUC16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES390E – MARCH 2002 – REVISED DECEMBER 2002 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 Pin numbers shown are for the DGG and DGV packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AUC16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES390E – MARCH 2002 – REVISED DECEMBER 2002 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V MIN MAX 0.8 2.7 VCC 0.65 × VCC UNIT V V 1.7 VCC = 0.8 V VCC = 1.1 V to 1.95 V 0 0.35 × VCC VIL Low-level input voltage VI VO Input voltage 0 3.6 V Output voltage 0 VCC –0.7 V VCC = 2.3 V to 2.7 V VCC = 0.8 V VCC = 1.1 V IOH IOL ∆t/∆v High-level output current Low-level output current Input transition rise or fall rate 0.7 –3 VCC = 1.4 V VCC = 1.65 V –5 VCC = 2.3 V VCC = 0.8 V –9 0.7 3 VCC = 1.65 V VCC = 2.3 V 8 VCC = 2.7 V mA –8 VCC = 1.1 V VCC = 1.4 V VCC = 0.8 V, 1.3 V VCC = 1.6 V, 1.95 V V 5 mA 9 20 10 ns/V 5 TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUC16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES390E – MARCH 2002 – REVISED DECEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 0.8 V to 2.7 V IOH = –100 µA IOH = –0.7 mA VOH VOL II Ioff A or OE inputs TYP† MIN MAX 0.8 V 0.55 IOH = –3 mA IOH = –5 mA 1.1 V 0.8 1.4 V 1 IOH = –8 mA IOH = –9 mA 1.65 V 1.2 2.3 V 1.8 IOL = 100 µA IOL = 0.7 mA 0.8 V to 2.7 V V 0.2 0.8 V 0.25 IOL = 3 mA IOL = 5 mA 1.1 V 0.3 1.4 V 0.4 IOL = 8 mA IOL = 9 mA 1.65 V 0.45 2.3 V 0.6 VI = VCC or GND VI or VO = 2.7 V IOZ ICC VO = VCC or GND VI = VCC or GND, Ci VI = VCC or GND V ±5 µA 0 ±10 µA 2.7 V ±10 µA 0.8 V to 2.7 V 20 µA 0 to 2.7 V IO = 0 UNIT VCC–0.1 Co VO = VCC or GND † All typical values are at TA = 25°C. 2.5 V 3 4 pF 2.5 V 5.5 6 pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX tpd A Y 5.9 0.9 2.6 0.7 1.8 0.6 1.4 2 0.4 1.6 ns ten OE Y 7.9 1.2 3.8 0.8 2.5 0.7 1.5 2.5 0.7 2 ns tdis OE Y 9.3 2.1 6 1.5 4.8 1.8 2.7 4.5 0.6 2.3 ns PARAMETER UNIT operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS VCC = 0.8 V TYP VCC = 1.2 V TYP VCC = 1.5 V TYP VCC = 1.8 V TYP VCC = 2.5 V TYP 24 24 25 26 30 2 2 2 3 4 f = 10 MHz UNIT pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74AUC16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES390E – MARCH 2002 – REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open RL VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V LOAD CIRCUIT CL RL 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω V∆ 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VCC/2 VOL tPHL VOH Output tPLZ VCC VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ tPZH VCC/2 VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VCC/2 VCC/2 tPZL VOH VCC/2 Output VCC Output Control VCC/2 VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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