TI SN74AUP1G98YZPR

SN74AUP1G98
www.ti.com
SCES506H – NOVEMBER 2003 – REVISED MAY 2010
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
Check for Samples: SN74AUP1G98
FEATURES
1
•
•
•
•
•
•
•
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption
(ICC = 0.9 mA Max)
Low Dynamic-Power Consumption
(Cpd = 4.6 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typ)
Low Noise – Overshoot and Undershoot
<10% of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Includes Schmitt-Trigger Inputs
•
•
•
•
•
•
•
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DSF PACKAGE
(TOP VIEW)
DRY PACKAGE
(TOP VIEW)
B
1
6
B
C
GND
2
5
VCC
A
3
4
Y
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 5.3 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
1
6
C
GND
2
5
VCC
A
3
4
Y
DRL PACKAGE
(TOP VIEW)
YFP PACKAGE
(TOP VIEW)
B
GND
A
A1
1
6 A2
B1
2
5 B2
C1
3
4 C2
C
VCC
Y
YZP PACKAGE
(TOP VIEW)
B
GND
A
A1
1
6 A2
B1
2
5 B2
C1
3
4 C2
C
VCC
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
The SN74AUP1G98 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All
inputs can be connected to VCC or GND.
The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition and
better switching-noise immunity at the input.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2010, Texas Instruments Incorporated
SN74AUP1G98
SCES506H – NOVEMBER 2003 – REVISED MAY 2010
www.ti.com
Static-Power Consumption
Dynamic-Power Consumption
(µA)
(pF)
100%
80%
80%
60%
40%
3
60%
3.3-V
Logic†
at 25 MHz†
3.5
Voltage − V
100%
Switching Characteristics
3.3-V
LVC
Logic†
40%
AUP
0%
†
Input
2
1.5
1
Output
0.5
20%
20%
2.5
0
−0.5
AUP
0%
Single, dual, and triple gates
Figure 1. AUP – The Lowest-Power Family
20 25 30
Time − ns
† AUP1G08 data at C = 15 pF
L
0
5
10
15
35
40
45
Figure 2. Excellent Signal Integrity
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION (1)
–40°C to 85°C
(1)
(2)
(3)
ORDERABLE
PART NUMBER
PACKAGE (2)
TA
TOP-SIDE
MARKING (3)
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YFP (Pb-free)
Reel of 3000
SN74AUP1G98YFPR
___HR_
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUP1G98YZPR
___HR_
QFN – DRY
Reel of 5000
SN74AUP1G98DRYR
HR
uQFN – DSF
Reel of 5000
SN74AUP1G98DSFR
HR
SOT (SOT-23) – DBV
Reel of 3000
SN74AUP1G98DBVR
H98_
SOT (SC-70) – DCK
Reel of 3000
SN74AUP1G98DCKR
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G98DRLR
HR_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free).
FUNCTION TABLE
INPUTS
2
A
OUTPUT
Y
L
L
H
L
H
H
L
H
L
L
C
B
L
L
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
H
H
H
H
L
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SCES506H – NOVEMBER 2003 – REVISED MAY 2010
LOGIC DIAGRAM (POSITIVE LOGIC)
A
3
4
B
C
1
Y
6
Table 1. FUNCTION SELECTION TABLE
LOGIC FUNCTION
FIGURE NO.
2-to-1 data selector with inverted output
Figure 3
2-input NAND gate
Figure 4
2-input NOR gate with one inverted input
Figure 5
2-input AND gate with one inverted input
Figure 5
2-input NAND gate with one inverted input
Figure 6
2-input OR gate with one inverted input
Figure 6
2-input NOR gate
Figure 7
Noninverted buffer
Figure 8
Inverter
Figure 9
LOGIC CONFIGURATIONS
VCC
C
B
B
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 3. 2-to-1 Data Selector With Inverted Output
When C is L, Y = B
When C is H, Y = A
VCC
C
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 4. 2-Input NAND Gate
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SCES506H – NOVEMBER 2003 – REVISED MAY 2010
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VCC
C
Y
A
C
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 5. 2-Input NOR Gate With One Inverted Input
2-Input AND Gate With One Inverted Input
VCC
C
Y
B
B
C
B
Y
1
6
2
5
3
4
C
Y
GND
Figure 6. 2-Input NAND Gate With One Inverted Input
2-Input OR Gate With One Inverted Input
VCC
C
B
Y
B
1
6
2
5
3
4
C
Y
GND
Figure 7. 2-Input NOR Gate
VCC
C
Y
1
6
2
5
3
4
C
Y
GND
Figure 8. Noninverted Buffer
4
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SCES506H – NOVEMBER 2003 – REVISED MAY 2010
VCC
B
B
Y
1
6
2
5
3
4
Y
GND
Figure 9. Inverter
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SN74AUP1G98
SCES506H – NOVEMBER 2003 – REVISED MAY 2010
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Output voltage range in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
qJA
Package thermal impedance (3)
DBV package
165
DCK package
259
DRL package
142
DSF package
300
DRY package
234
YFP/YZP package
Tstg
(1)
(2)
(3)
V
°C/W
123
Storage temperature range
–65
.
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
MIN
MAX
UNIT
VCC
Supply voltage
0.8
3.6
V
VI
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
V
VCC = 0.8 V
–20
A
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65
–1.9
VCC = 2.3 V
–3.1
IOH
IOL
High-level output current
Low-level output current
VCC = 3 V
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
TA
(1)
6
Operating free-air temperature
mA
mA
mA
4
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES506H – NOVEMBER 2003 – REVISED MAY 2010
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
VCC
TA = 25°C
MIN
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
0.8 V
0.3
0.6
0.3
0.6
1.1 V
0.53
0.9
0.53
0.9
Positive-going
input threshold
voltage
1.4 V
0.74
1.11
0.74
1.11
1.65 V
0.91
1.29
0.91
1.29
2.3 V
1.37
1.77
1.37
1.77
3V
1.88
2.29
1.88
2.29
VT–
0.8 V
0.1
0.6
0.1
0.6
1.1 V
0.26
0.65
0.26
0.65
Negative-going
input threshold
voltage
ΔVT
Hysteresis
(VT+ – VT–)
VOH
0.39
0.75
0.84
0.47
0.84
2.3 V
0.69
1.04
0.69
1.04
3V
0.88
1.24
0.88
1.24
0.8 V
0.07
0.5
0.07
0.5
1.1 V
0.08
0.46
0.08
0.46
1.4 V
0.18
0.56
0.18
0.56
1.65 V
0.27
0.66
0.27
0.66
2.3 V
0.53
0.92
0.53
0.92
3V
0.79
1.31
0.79
1.31
0.8 V to 3.6 V
VCC – 0.1
VCC – 0.1
1.1 V
0.75 × VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
2.05
1.97
1.9
1.85
2.72
2.67
IOH = –2.7 mA
IOH = –4 mA
2.3 V
3V
IOL = 20 mA
0.8 V to 3.6 V
IOL = 1.1 mA
2.6
V
V
V
V
2.55
0.1
0.1
1.1 V
0.3 × VCC
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
0.37
IOL = 1.9 mA
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
0 V to 3.6 V
0.1
0.5
mA
IOL = 2.3 mA
IOL = 3.1 mA
IOL = 2.7 mA
IOL = 4 mA
All inputs
0.75
0.47
IOH = –1.1 mA
IOH = –3.1 mA
II
0.39
IOH = –20 mA
IOH = –2.3 mA
VOL
1.4 V
1.65 V
UNIT
VI = GND to 3.6 V
2.3 V
3V
V
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
mA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
mA
ICC
VI = GND or (VCC to 3.6 V),
IO = 0
0.8 V to 3.6 V
0.5
0.9
mA
ΔICC
VI = VCC – 0.6 V (1), IO = 0
40
50
mA
Ci
VI = VCC or GND
Co
VO = GND
(1)
3.3 V
0V
1.5
3.6 V
1.5
0V
pF
3
pF
One input at VCC – 0.6 V, other inputs at VCC or GND.
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
0.8 V
tpd
A, B, or C
Y
TA = –40°C
to 85°C
TA = 25°C
TYP
MAX
MIN
UNIT
MAX
22.2
1.2 V ± 0.1 V
2.7
9.1
13.6
2.2
17
1.5 V ± 0.1 V
2
6.4
9.2
1.5
11.1
1.8 V ± 0.15 V
1.4
5.2
7.2
0.9
8.9
2.5 V ± 0.2 V
1.2
3.8
5.3
0.7
6.3
3.3 V ± 0.3 V
1
3.1
4.5
0.5
5.3
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
0.8 V
tpd
A, B, or C
Y
TA = –40°C
to 85°C
TA = 25°C
TYP
MAX
MIN
UNIT
MAX
25.4
1.2 V ± 0.1 V
5.2
10.4
15.4
4.7
19
1.5 V ± 0.1 V
4
7.4
10.5
3.5
12.6
1.8 V ± 0.15 V
3.1
6
8.3
2.6
10.2
2.5 V ± 0.2 V
2.7
4.5
6.1
2.2
7.3
3.3 V ± 0.3 V
2.5
3.7
5
2
6
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
0.8 V
tpd
A, B, or C
Y
TA = –40°C
to 85°C
TA = 25°C
TYP
MAX
MIN
MAX
21.1
UNIT
28.7
1.2 V ± 0.1 V
3.7
11.5
17
3.2
1.5 V ± 0.1 V
2.8
8.3
11.6
2.3
14
1.8 V ± 0.15 V
2.1
6.7
9.2
1.6
11.3
2.5 V ± 0.2 V
1.8
5
6.7
1.3
8.1
3.3 V ± 0.3 V
1.6
4.1
5.5
1.1
6.6
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
0.8 V
tpd
8
A, B, or C
Y
TA = –40°C
to 85°C
TA = 25°C
TYP
MAX
MIN
MAX
39.7
1.2 V ± 0.1 V
5.1
15.3
21.6
4.6
26.8
1.5 V ± 0.1 V
3.9
10.9
14.6
3.4
17.6
1.8 V ± 0.15 V
3.1
8.9
11.5
2.6
14.1
2.5 V ± 0.2 V
2.6
6.7
8.4
2.1
10.1
3.3 V ± 0.3 V
2.3
5.5
6.9
1.8
8.3
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UNIT
ns
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SCES506H – NOVEMBER 2003 – REVISED MAY 2010
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
0.8 V
4
1.2 V ± 0.1 V
4
1.5 V ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
4.3
3.3 V ± 0.3 V
4.6
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UNIT
pF
9
SN74AUP1G98
SCES506H – NOVEMBER 2003 – REVISED MAY 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Duration)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
0V
tPLH
tsu
VOH
VM
Output
th
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 10. Load Circuit and Voltage Waveforms
10
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PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
VOL + V∆
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VCC/2
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 11. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
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19-May-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP1G98DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DBVRE4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DBVTE4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DCKR
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DCKRE4
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DCKRG4
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DCKTE4
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DRLR
ACTIVE
SOT
DRL
6
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DRLRG4
ACTIVE
SOT
DRL
6
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DRYR
ACTIVE
SON
DRY
6
5000 Green (RoHS &
no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DSFR
ACTIVE
SON
DSF
6
5000 Green (RoHS &
no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98YFPR
ACTIVE
DSBGA
YFP
6
3000
SN74AUP1G98YZPR
ACTIVE
DSBGA
YZP
6
3000 Green (RoHS &
no Sb/Br)
TBD
Lead/Ball Finish
Call TI
SNAGCU
MSL Peak Temp (3)
Call TI
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2010
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74AUP1G98DBVR
SOT-23
3000
180.0
9.2
DBV
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G98DBVT
SOT-23
DBV
6
250
180.0
9.2
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G98DCKR
SC70
DCK
6
3000
180.0
8.4
2.24
2.34
1.22
4.0
8.0
Q3
SN74AUP1G98DCKT
SC70
DCK
6
250
180.0
8.4
2.24
2.34
1.22
4.0
8.0
Q3
SN74AUP1G98DRLR
SOT
DRL
6
4000
180.0
9.2
1.78
1.78
0.69
4.0
8.0
Q3
SN74AUP1G98DRYR
SON
DRY
6
5000
180.0
8.4
1.25
1.6
0.7
4.0
8.0
Q1
SN74AUP1G98DSFR
SON
DSF
6
5000
180.0
8.4
1.16
1.16
0.63
4.0
8.0
Q2
SN74AUP1G98YFPR
DSBGA
YFP
6
3000
178.0
9.2
0.89
1.29
0.62
4.0
8.0
Q1
SN74AUP1G98YZPR
DSBGA
YZP
6
3000
180.0
8.4
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G98DBVR
SOT-23
DBV
6
3000
202.0
201.0
28.0
SN74AUP1G98DBVT
SOT-23
DBV
6
250
202.0
201.0
28.0
SN74AUP1G98DCKR
SC70
DCK
6
3000
202.0
201.0
28.0
SN74AUP1G98DCKT
SC70
DCK
6
250
202.0
201.0
28.0
SN74AUP1G98DRLR
SOT
DRL
6
4000
202.0
201.0
28.0
SN74AUP1G98DRYR
SON
DRY
6
5000
202.0
201.0
28.0
SN74AUP1G98DSFR
SON
DSF
6
5000
202.0
201.0
28.0
SN74AUP1G98YFPR
DSBGA
YFP
6
3000
220.0
220.0
35.0
SN74AUP1G98YZPR
DSBGA
YZP
6
3000
220.0
220.0
34.0
Pack Materials-Page 2
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