Sample & Buy Product Folder Technical Documents Support & Community Tools & Software SN74AUP1G00 SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 SN74AUP1G00 Low-Power Single 2-Input Positive-NAND Gate 1 Features • 1 • • • • • • • • • • • • • 2 Applications 2 Available in the Ultra Small 0.64 mm Package (DPW) with 0.5-mm Pitch Low Static-Power Consumption (ICC = 0.9 µA Max) Low Dynamic-Power Consumption (Cpd = 4 pF Typ at 3.3 V) Low Input Capacitance (Ci = 1.5 pF Typ) Low Noise Overshoot and Undershoot <10% of VCC Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input (Vhys = 250 mV Typ at 3.3 V) Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation tpd = 4.8 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) • • • • • • • • • • • • • • • • • • • ATCA Solutions Active Noise Cancellation (ANC) Barcode Scanner Blood Pressure Monitor CPAP Machine Cable Solutions DLP 3D Machine Vision, Hyperspectral Imaging, Optical Networking, and Spectroscopy E-Book Embedded PC Field Transmitter: Temperature or Pressure Sensor Fingerprint Biometrics HVAC: Heating, Ventilating, and Air Conditioning Network-Attached Storage (NAS) Server Motherboard and PSU Software Defined Radio (SDR) TV: High-Definition (HDTV), LCD, and Digital Video Communications System Wireless Data Access Card, Headset, Keyboard, Mouse, and LAN Card X-ray: Baggage Scanner, Medical, and Dental 3 Description This single 2-input positive-NAND gate performs the Boolean function Y = A × B or Y = A + B in positive logic. Device Information(1) PART NUMBER SN74AUP1G00 PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm SC70 (5) 2.00 mm × 1.25 mm SOT (5) 1.60 mm × 1.20 mm USON (6) 1.45 mm × 1.00 mm X2SON (4) 0.80 mm × 0.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic A B Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AUP1G00 SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 4 4 5 5 6 6 7 7 7 7 8 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, CL = 5 pF ........................ Switching Characteristics, CL = 10 pF ...................... Switching Characteristics, CL = 15 pF ...................... Switching Characteristics, CL = 30 pF ...................... Operating Characteristics........................................ Typical Characteristics ............................................ Parameter Measurement Information .................. 9 8.1 Propagation Delays, Setup and Hold Times, and Pulse Width................................................................ 9 8.2 Enable and Disable Times ...................................... 10 9 Detailed Description ............................................ 11 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 11 11 11 11 10 Application and Implementation........................ 12 10.1 Application Information.......................................... 12 10.2 Typical Application ............................................... 12 11 Power Supply Recommendations ..................... 14 12 Layout................................................................... 14 12.1 Layout Guidelines ................................................. 14 12.2 Layout Example .................................................... 14 13 Device and Documentation Support ................. 15 13.1 Trademarks ........................................................... 15 13.2 Electrostatic Discharge Caution ............................ 15 13.3 Glossary ................................................................ 15 14 Mechanical, Packaging, and Orderable Information ........................................................... 15 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (April 2012) to Revision I Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Removed Ordering Information table. .................................................................................................................................... 1 • Updated Ioff in Features. ........................................................................................................................................................ 1 • Added Applications. ................................................................................................................................................................ 1 • Added Device Information table. ........................................................................................................................................... 1 • Added DPW Package. ........................................................................................................................................................... 3 • Added Handling Ratings table. ............................................................................................................................................... 4 • Added Thermal Information table. .......................................................................................................................................... 5 • Added Typical Characteristics. ............................................................................................................................................... 8 Changes from Revision G (March 2010) to Revision H • 2 Page Corrected the MIN Value for 1.2 V per available characterization data. ................................................................................ 7 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 SN74AUP1G00 www.ti.com SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 6 Pin Configuration and Functions DBV PACKAGE (TOP VIEW) 1 A B 2 GND 3 DCK PACKAGE (TOP VIEW) 4 1 B 2 GND 3 A 1 B 2 GND 3 VCC 5 4 5 VCC 4 Y Y YZP PACKAGE (TOP VIEW) DSF PACKAGE (TOP VIEW) VCC 6 1 Y DRY PACKAGE (TOP VIEW) A A VCC 5 DRL PACKAGE (TOP VIEW) B 2 5 N.C. GND 3 4 Y A 1 6 VCC B 2 5 N.C. GND 3 4 Y A B GND A1 1 B1 2 C1 3 5 A2 4 C2 YFP PACKAGE (TOP VIEW) VCC Y A B GND A1 1 6 A2 B1 2 5 B2 C1 3 4 C2 VCC DNU Y DPW PACKAGE (TOP VIEW) DNU – Do not use N.C. – No internal connection See mechanical drawings for dimensions. GND B A 1 5 3 2 4 VCC Y Pin Functions PIN I/O DESCRIPTION NAME DBV, DCK, DRL DPW DRY, DSF YZP YFP A 1 2 1 A1 A1 I Input A B 2 1 2 B2 B2 I Input B GND 3 3 3 C3 B3 — Ground Y 4 4 4 C4 C4 O Output Y VCC 5 5 6 A5 A6 — Power Pin Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 3 SN74AUP1G00 SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 4.6 UNIT V (2) VI Input voltage range –0.5 4.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 4.6 V VO Output voltage range in the high or low state (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 50 mA IOK Output clamp current VO < 0 50 mA IO Continuous output current 20 mA Continuous current through VCC or GND 50 mA (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 Handling Ratings Tstg V(ESD) (1) (2) 4 MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 Storage temperature range Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 SN74AUP1G00 www.ti.com SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX 0.8 3.6 Supply voltage VCC = 0.8 V VIH 0.65 × VCC VCC = 2.3 V to 2.7 V V 1.6 VCC = 3 V to 3.6 V 2 VCC = 0.8 V VIL Low-level input voltage VI Input voltage VO Output voltage 0 VCC = 1.1 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V High-level output current 0.9 0 3.6 0 Low-level output current VCC V –20 µA VCC = 1.1 V –1.1 VCC = 1.4 V –1.7 VCC = 1.65 –1.9 VCC = 2.3 V –3.1 Input transition rise or fall rate TA Operating free-air temperature (1) mA –4 VCC = 0.8 V 20 VCC = 1.1 V 1.1 VCC = 1.4 V 1.7 VCC = 1.65 V 1.9 VCC = 2.3 V 3.1 VCC = 3 V Δt/Δv V VCC = 0.8 V VCC = 3 V IOL V 0.7 VCC = 3 V to 3.6 V IOH V VCC VCC = 1.1 V to 1.95 V High-level input voltage UNIT A mA 4 VCC = 0.8 V to 3.6 V 200 ns/V 85 °C –40 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7.4 Thermal Information THERMAL METRIC (1) DBV DCK DPW DRL DRY DSF 5 PINS 5 PINS 5 PINS 5 PINS 6 PINS 6 PINS RθJA Junction-to-ambient thermal resistance 298.6 314.4 291.8 349.7 554.9 407.1 RθJC(top) Junction-to-case (top) thermal resistance 240.2 128.7 224.2 120.5 385.4 232.0 RθJB Junction-to-board thermal resistance 134.6 100.6 245.8 171.4 388.2 306.9 ψJT Junction-to-top characterization parameter 114.5 7.1 31.4 10.8 159.0 40.3 ψJB Junction-to-board characterization parameter 133.9 99.8 245.6 169.4 384.1 306.0 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a 195.4 n/a n/a n/a (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 5 SN74AUP1G00 SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 www.ti.com 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC MAX MIN 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1 1.1 V 0.75 × VCC 0.7 × VCC IOH = –1.7 mA 1.4 V 1.11 1.03 IOH = –1.9 mA 1.65 V 1.32 1.3 2.05 1.97 1.9 1.85 2.72 2.67 2.3 V IOH = –2.7 mA 3V IOH = –4 mA IOL = 20 µA 0.8 V to 3.6 V IOL = 1.1 mA IOL = 1.7 mA IOL = 1.9 mA IOL = 2.3 mA IOL = 3.1 mA V 2.55 0.1 1.1 V 0.3 × VCC 0.3 × VCC 1.4 V 0.31 0.37 1.65 V 0.31 0.35 0.31 0.33 0.44 0.45 0.31 0.33 0.44 0.45 0 V to 3.6 V 0.1 0.5 µA 2.3 V 3V IOL = 4 mA VI = GND to 3.6 V 2.6 UNIT MAX 0.1 IOL = 2.7 mA A or B input TYP IOH = –1.1 mA IOH = –3.1 mA II MIN TA = –40°C to 85°C IOH = –20 µA IOH = –2.3 mA VOL TA = 25°C V Ioff VI or VO = 0 V to 3.6 V 0V 0.2 0.6 µA ΔIoff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 µA ICC VI = GND or (VCC to 3.6 V), IO = 0 0.8 V to 3.6 V 0.5 0.9 µA ΔICC VI = VCC – 0.6 V (1), IO = 0 3.3 V 40 50 µA Ci VI = VCC or GND Co VO = GND (1) 0V 1.5 3.6 V 1.5 0V pF 3 pF One input at VCC – 0.6 V, other input at VCC or GND. 7.6 Switching Characteristics, CL = 5 pF over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd 6 A or B Y TA = –40°C to 85°C TA = 25°C VCC TYP UNIT MAX MIN MAX 16.6 1.2 V ± 0.1 V 2.6 7 13.8 2.1 17.1 1.5 V ± 0.1 V 2.9 5 9.2 2.9 11.1 1.8 V ± 0.15 V 2 4 7.1 2 9 2.5 V ± 0.2 V 1.3 2.9 4.9 1.3 6.2 3.3 V ± 0.3 V 1 2.4 3.8 1 4.8 Submit Documentation Feedback ns Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 SN74AUP1G00 www.ti.com SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 7.7 Switching Characteristics, CL = 10 pF over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP 0.8 V tpd A or B Y TA = –40°C to 85°C TA = 25°C VCC UNIT MAX MIN MAX 18.9 1.2 V ± 0.1 V 3.2 8 15.7 3.1 18.8 1.5 V ± 0.1 V 2.9 5.8 10.5 2.9 12.1 1.8 V ± 0.15 V 2 4.7 8.2 2 9.8 2.5 V ± 0.2 V 1.3 3.4 5.7 1.3 6.8 3.3 V ± 0.3 V 1 2.9 4.5 1 5.2 ns 7.8 Switching Characteristics, CL = 15 pF over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP 0.8 V tpd A or B Y TA = –40°C to 85°C TA = 25°C VCC UNIT MAX MIN MAX 21.3 1.2 V ± 0.1 V 3.6 9 17.3 3.1 21.5 1.5 V ± 0.1 V 2.9 6.5 11.6 2.9 14 1.8 V ± 0.15 V 2 5.3 9.2 2 11.4 2.5 V ± 0.2 V 1.3 3.9 6.4 1.3 8 3.3 V ± 0.3 V 1 3.3 5.1 1 6.4 ns 7.9 Switching Characteristics, CL = 30 pF over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A or B Y TA = –40°C to 85°C TA = 25°C VCC TYP UNIT MAX MIN MAX 28.4 1.2 V ± 0.1 V 4.9 11.9 21.9 4.4 27.1 1.5 V ± 0.1 V 2.9 8.6 14.7 2.9 17.7 1.8 V ± 0.15 V 2 7.1 11.5 2 14.2 2.5 V ± 0.2 V 1.3 5.3 8.1 1.3 10 3.3 V ± 0.3 V 1 4.5 6.5 1 8 ns 7.10 Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC TYP 0.8 V 4 1.2 V ± 0.1 V 4 1.5 V ± 0.1 V 4 1.8 V ± 0.15 V 4 2.5 V ± 0.2 V 4 3.3 V ± 0.3 V 4 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 UNIT pF 7 SN74AUP1G00 SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 www.ti.com 7.11 Typical Characteristics 6 18 TPD in ns 16 5 14 4 TPD (ns) TPD (ns) 12 10 8 3 2 6 4 1 2 TPD in ns 0 0 1 2 VCC (V) 3 4 0 -50 D001 Figure 1. TDP vs VCC 8 0 50 Temperature (qC) 100 150 D001 Figure 2. TPD vs Temperature Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 SN74AUP1G00 www.ti.com SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 8 Parameter Measurement Information 8.1 Propagation Delays, Setup and Hold Times, and Pulse Width From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC tw VCC Input VCC/2 VCC/2 VI VM Input 0V VM VOLTAGE WAVEFORMS PULSE DURATION 0V tPHL tPLH VOH VM Output VM VOL tPHL VCC Timing Input 0V tPLH tsu VOH VM Output th VCC VM VOL Data Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. E. VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 9 SN74AUP1G00 SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 www.ti.com 8.2 Enable and Disable Times 2 × VCC S1 5 kΩ From Output Under Test GND CL (see Note A) 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 × VCC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V VCC Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 0V tPLZ tPZL VCC VCC/2 VOL + V∆ VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VCC/2 VCC/2 VOH VOH - V∆ ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 10 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 SN74AUP1G00 www.ti.com SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 9 Detailed Description 9.1 Overview This is a single 2-input positive-NAND gate that is designed in Texas Instrument’s ultra-low power technology. It performs the Boolean function Y = A × B or Y = A + B in positive logic. The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered. The Ioff feature also allows for live insertion. 9.2 Functional Block Diagram A Y B 9.3 Feature Description • • • • • Wide operating VCC range of 0.8 V to 3.6 V 3.6-V I/O tolerant to support down translation Input hysteresis allows slow input transition and better switching noise immunity at the input Ioff feature allows voltages on the inputs and outputs when VCC is 0 V Low noise due to slower edge rates 9.4 Device Functional Modes Table 1. Function Table INPUTS B OUTPUT Y L L H L H H H L H H H L A Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 11 SN74AUP1G00 SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 www.ti.com 10 Application and Implementation 10.1 Application Information The AUP family is TI's premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. It has a small amount of hysteresis built in allowing for slower or noisy input signals. The lowered drive produces slower edges and prevents overshoot and undershoot on the outputs. 10.2 Typical Application 3.3 V Bus Driver V CC 1-V Micro Processor 0.1 µF µC Driver Figure 5. Typical Application Diagram 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. 10.2.2 Detailed Design Procedure 1. Recommended Input conditions – Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions – Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions – Inputs are overvoltage tolerant allowing them to go as high as 3.6 V at any valid VCC 2. Recommend output conditions – Load currents should not exceed 20 mA on the output and 50 mA total for the part – Outputs should not be pulled above VCC 12 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 SN74AUP1G00 www.ti.com SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 Typical Application (continued) 10.2.3 Application Curves Switching Characteristics at 25 MHz† 3.5 Voltage − V 3 2.5 Input 2 1.5 1 Output 0.5 0 −0.5 0 5 10 15 20 25 30 Time − ns 35 40 45 † AUP1G08 data at C = 15 pF L Figure 6. AUP – The Lowest-Power Family Figure 7. Excellent Signal Integrity The AUP family of single gate logic makes excellent translators for the new lower voltage microprocessors that typically are powered from 0.8 V to 1.2 V. They can drop the voltage of peripheral drivers and accessories that are still powered by 3.3 V to the new uC power levels. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 13 SN74AUP1G00 SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 www.ti.com 11 Power Supply Recommendations The power supply can be any voltage between the Min and Max supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple-bit logic devices, inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 8 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled. 12.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 8. Layout Diagram 14 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 SN74AUP1G00 www.ti.com SCES604I – SEPTEMBER 2004 – REVISED JUNE 2014 13 Device and Documentation Support 13.1 Trademarks All trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: SN74AUP1G00 15 PACKAGE OUTLINE SN74LVC1GXX and SN74AUP1GXX DPW0005A-C01 X2SON - 0.4 mm max height SCALE 12.000 PLASTIC SMALL OUTLINE - NO LEAD 0.85 0.75 B A 0.85 0.75 PIN 1 INDEX AREA 0.4 MAX C SEATING PLANE NOTE 4 (0.1) 0.05 0.00 0.25 0.1 THERMAL PAD 2 4 2X 0.48 NOTE 4 3 5 1 4X 0.27 0.17 (0.06) 3X 0.32 0.23 0.27 0.17 0.1 C A 0.05 C B 4221849/A 12/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. The size and shape of this feature may vary. www.ti.com EXAMPLE BOARD LAYOUT SN74LVC1GXX and SN74AUP1GXX DPW0005A-C01 X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.78) SYMM 4X (0.42) ( 0.1) VIA 0.05 MIN ALL AROUND TYP 1 5 4X (0.22) SYMM 4X (0.26) (0.48) 3 2 4 (R0.05) TYP 4X (0.06) ( 0.25) LAND PATTERN EXAMPLE SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK TYP SOLDER MASK DEFINED SCALE:60X 4221849/A 12/2014 NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com EXAMPLE STENCIL DESIGN SN74LVC1GXX and SN74AUP1GXX DPW0005A-C01 X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4X (0.42) 4X (0.22) 4X (0.06) 5 1 ( 0.24) 4X (0.26) SYMM (0.21) TYP SOLDER MASK EDGE 3 2 (R0.05) TYP (0.48) 4 SYMM (0.78) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X 4221849/A 12/2014 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74AUP1G00DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 H00R SN74AUP1G00DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 H00R SN74AUP1G00DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 H00R SN74AUP1G00DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (HAF ~ HAK ~ HAR) SN74AUP1G00DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (HAF ~ HAK ~ HAR) SN74AUP1G00DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HAR SN74AUP1G00DPWR ACTIVE X2SON DPW 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 A4 SN74AUP1G00DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (HA7 ~ HAR) SN74AUP1G00DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (HA7 ~ HAR) SN74AUP1G00DRY2 ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HA SN74AUP1G00DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HA SN74AUP1G00DSF2 ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 HA SN74AUP1G00DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 HA SN74AUP1G00YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74AUP1G00YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1 (HA2 ~ HA7 ~ HAN) -40 to 85 (HA7 ~ HAN) Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2016 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74AUP1G00DBVR SOT-23 3000 180.0 8.4 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G00DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G00DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74AUP1G00DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 SN74AUP1G00DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74AUP1G00DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74AUP1G00DRLR SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 SN74AUP1G00DRY2 SON DRY 6 5000 180.0 8.4 1.65 1.2 0.7 4.0 8.0 Q3 SN74AUP1G00DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3 SN74AUP1G00DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74AUP1G00DSF2 SON DSF 6 5000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q3 SN74AUP1G00DSF2 SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3 SN74AUP1G00DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74AUP1G00YFPR DSBGA YFP 6 3000 178.0 9.2 0.89 1.29 0.62 4.0 8.0 Q1 SN74AUP1G00YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUP1G00DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74AUP1G00DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 SN74AUP1G00DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74AUP1G00DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74AUP1G00DCKT SC70 DCK 5 250 202.0 201.0 28.0 SN74AUP1G00DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74AUP1G00DRLR SOT DRL 5 4000 184.0 184.0 19.0 SN74AUP1G00DRY2 SON DRY 6 5000 202.0 201.0 28.0 SN74AUP1G00DRY2 SON DRY 6 5000 184.0 184.0 19.0 SN74AUP1G00DRYR SON DRY 6 5000 184.0 184.0 19.0 SN74AUP1G00DSF2 SON DSF 6 5000 202.0 201.0 28.0 SN74AUP1G00DSF2 SON DSF 6 5000 184.0 184.0 19.0 SN74AUP1G00DSFR SON DSF 6 5000 184.0 184.0 19.0 SN74AUP1G00YFPR DSBGA YFP 6 3000 220.0 220.0 35.0 SN74AUP1G00YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PLASTIC SMALL OUTLINE NO-LEAD DSF (S-PX2SON-N6) 1.05 0.95 A B PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 2X 0.7 4 SYMM 4X 0.35 6 1 (0.1) PIN 1 ID 6X 6X 0.45 0.35 0.22 0.12 0.07 0.05 C A C B 4208186/F 10/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.858 mm D: Max = 1.19 mm, Min = 1.13 mm E: Max = 0.79 mm, Min = 0.73 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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