TI TLC59281DBQ

TLC59281
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SBVS139 – JANUARY 2010
16-Channel, Constant-Current LED Driver
Check for Samples: TLC59281
FEATURES
APPLICATIONS
•
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•
•
1
2
•
•
•
•
•
•
•
•
•
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16 Channels, Constant-Current Sink Output
with On/Off Control
35-mA Capability (Constant-Current Sink)
10-ns High-Speed Constant-Current Switching
Transient Time
Low On-Time Error
LED Power-Supply Voltage up to 17 V
VCC = 3.0 V to 5.5 V
Constant-Current Accuracy:
– Channel-to-Channel = ±1%
– Device-to-Device = ±1%
CMOS Logic Level I/O
35-MHz Data Transfer Rate
20-ns BLANK Pulse Width
Operating Temperature: –40°C to +85°C
VLED
Controller
The TLC59281 is a 16-channel, constant-current sink
LED driver. Each channel can be turned on/off by
writing serial data to an internal register. The
constant-current value of all 16 channels is set by a
single external resistor.
¼
¼
¼
¼
¼
OUT15
OUT0
SOUT
IREF
OUT15
SOUT
VCC
SCLK
LAT
VCC
VCC
BLANK
BLANK
ERROR
READ
¼
SIN
VCC
LAT
BLANK
VLED
¼
SCLK
LAT
VLED
¼
SIN
SCLK
DESCRIPTION
VLED
OUT0
DATA
LED Video Displays
Message Boards
Illumination
TLC59281
IC1
RIREF
IREF
GND
ICn
GND
RIREF
3
Typical Application Circuit (Multiple Daisy-Chained TLC59281s)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TLC59281
SBVS139 – JANUARY 2010
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
TLC59281
TRANSPORT MEDIA, QUANTITY
TLC59281DBQR
Tape and Reel, 2500
SO-24
TLC59281
(1)
ORDERING NUMBER
QFN-24
TLC59281DBQ
Tube, 50
TLC59281RGER
Tape and Reel, 3000
TLC59281RGE
Tape and Reel, 250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
TLC59281
VCC
Supply voltage: VCC
IOUT
Output current (dc)
OUT0 to OUT15
VIN
Input voltage range
VOUT
Output voltage range
TJ(MAX)
Operating junction temperature
TSTG
Storage temperature range
(1)
(2)
–0.3 to +6.0
V
40
mA
SIN, SCLK, LAT, BLANK, IREF
–0.3 to VCC + 0.3
V
SOUT
–0.3 to VCC + 0.3
V
OUT0 to OUT15
Human body model (HBM)
ESD rating
UNIT
Charged device model (CDM)
–0.3 to +18
V
+150
°C
–55 to +150
°C
2
kV
500
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
(1)
2
PACKAGE
OPERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
SO-24
14.3 mW/°C
1782 mW
1140 mW
927 mW
QFN-24 (1)
24.8 mW/°C
3106 mW
1988 mW
1615 mW
The package thermal impedance is calculated in accordance with JESD51-5.
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SBVS139 – JANUARY 2010
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
TLC59281
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
Supply voltage
3.0
5.5
V
VO
Voltage applied to output
VIH
17
V
High-level input voltage
0.7 × VCC
VCC
V
VIL
Low-level input voltage
GND
0.3 × VCC
V
IOH
High-level output current
SOUT
–1
mA
IOL
Low-level output current
SOUT
1
mA
IOLC
Constant output sink current
35
mA
TA
Operating free-air temperature range
–40
+85
°C
TJ
Operating junction temperature range
–40
+125
°C
OUT0 to OUT15
OUT0 to OUT15
2
AC Characteristics: VCC = 3 V to 5.5 V
fCLK
(SCLK)
Data shift clock frequency
SCLK
35
MHz
TWH0
SCLK
10
ns
TWL0
SCLK
10
ns
LAT
20
ns
TWH2
BLANK
20
ns
TWL2
BLANK
20
ns
TSU0
SIN–SCLK↑
4
ns
TWH1
TSU1
TH0
TH1
Pulse duration
Setup time
Hold time
LAT↑–SCLK↑
100
ns
SIN–SCLK↑
3
ns
LAT↑–SCLK↑
10
ns
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TLC59281
SBVS139 – JANUARY 2010
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ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC59281
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –1 mA at SOUT
VOL
Low-level output voltage
IOL = 1 mA at SOUT
IIN
Input current
VIN = VCC or GND at SIN, SCLK, LAT, and BLANK
ICC1
ICC2
Supply current (VCC)
MIN
MAX
UNIT
VCC – 0.4
TYP
VCC
V
0
0.4
V
–1
1
μA
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,
RIREF = 27 kΩ
1
2
mA
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,
RIREF = 3 kΩ
4.5
8
mA
ICC3
SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V,
RIREF = 3 kΩ
7
18
mA
ICC4
SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V,
RIREF = 1.5 kΩ
16
40
mA
34
37
mA
0.1
μA
IOLC
Constant output current
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
(see Figure 6), at OUT0 to OUT15
IOLKG
Output leakage current
All OUTn for constant-current driver, all outputs off
BLANK = high, VOUTn = VOUTfix = 17 V, RIREF = 1.5 kΩ
(see Figure 6), at OUT0 to OUT15
ΔIOLC
Constant-current error
(channel-to-channel) (1)
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15
±1
±3
%
ΔIOLC1
Constant-current error
(device-to-device) (2)
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15
±1
±6
%
ΔIOLC2
Line regulation (3)
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15
±0.5
±1
%/V
ΔIOLC3
Load regulation (4)
All OUTn = ON, VOUTn = 1 V to 3V, VOUTfix = 1 V,
RIREF = 1.5 kΩ, at OUT0 to OUT15
±1
±3
%/V
VIREF
Reference voltage output
RIREF = 1.5 kΩ
1.20
1.24
(1)
1.16
V
The deviation of each output from the average of OUT0–OUT15 constant-current. Deviation is calculated by the formula:
D (%) =
(2)
31
IOUTn
(IOUT0 + IOUT1 + ... + IOUT14 + IOUT15)
-1
´ 100
16
.
The deviation of the OUT0–OUT15 constant-current average from the ideal constant-current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15)
16
D (%) =
- (Ideal Output Current)
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
IOUT(IDEAL) = 42 ´
(3)
Line regulation is calculated by this equation:
D (%/V) =
(4)
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V)
(IOUTn at VCC = 3.0 V)
´
100
5.5 V - 3 V
Load regulation is calculated by the equation:
D (%/V) =
4
1.20
RIREF
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
(IOUTn at VOUTn = 1 V)
´
100
3V-1V
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SBVS139 – JANUARY 2010
SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 130 Ω, RIREF = 1.5 kΩ, and VLED = 5.5 V. Typical values at
VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC59281
PARAMETER
tR0
TEST CONDITIONS
Rise time
tR1
tF0
Fall time
tF1
TYP
MAX
SOUT (see Figure 5)
MIN
5
15
UNIT
ns
OUTn (see Figure 4)
10
30
ns
SOUT (see Figure 5)
5
15
ns
OUTn (see Figure 4)
10
30
ns
8
20
ns
tD0
SCLK↑ to SOUT
tD1
LAT↑ or BLANK↓ to OUTn sink current on
(see Figure 10)
12
30
ns
LAT↑ or BLANK↑ to OUTn sink current off
(see Figure 10)
12
30
ns
+8
ns
Propagation delay time
tD2
tON_ERR
(1)
Output on-time error (1)
On/off latch data = all '1', 20 ns BLANK low level
one-shot pulse input (see Figure 4)
–8
Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low level one-shot pulse width (TWL2).
tOUT_ON indicates the actual on-time of the constant-current driver.
FUNCTIONAL BLOCK DIAGRAM
VCC
TI Reserved
Data
VCC
16
SIN
LSB
MSB
On/Off Control Shift Register
(1 Bit x 16 Channels)
SCLK
0
SOUT
15
16
MSB
LSB
LAT
On/Off Control Data Latch
(1 Bit x 16 Channels)
0
BLANK
15
16
16-Channel Constant-Current Sink Driver
IREF
GND
GND
¼
OUT0
OUT1
OUT14 OUT15
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DEVICE INFORMATION
SO-24
DBQ PACKAGE
(TOP VIEW)
SCLK
SIN
GND
VCC
IREF
SOUT
24
23
22
21
20
19
QFN-24
RGE PACKAGE
(TOP VIEW)
GND
1
24
VCC
SIN
2
23
IREF
SCLK
3
22
SOUT
LAT
4
21
BLANK
LAT
1
18
BLANK
OUT0
5
20
OUT15
OUT0
2
17
OUT15
OUT1
6
19
OUT14
OUT1
3
16
OUT14
15
OUT13
TLC59281
Thermal Pad
(Bottom Side)
TLC59281
5
14
OUT12
OUT4
9
16
OUT11
OUT4
6
13
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
OUT5
12
OUT3
OUT10
OUT12
11
17
OUT9
8
10
OUT3
OUT8
4
9
OUT2
OUT7
OUT13
8
18
OUT6
7
7
OUT2
NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND via the PCB pattern.
6
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SBVS139 – JANUARY 2010
TERMINAL FUNCTIONS
TERMINAL
NAME
DBQ
RGE
I/O
DESCRIPTION
SIN
2
23
I
Serial data input for driver on/off control. When SIN = high level, data '1' are written into LSB
of the on/off control shift register at the rising edge of SCLK.
SCLK
3
24
I
Serial data shift clock. Schmitt buffer input. All data in the on/off control shift register are
shifted toward the MSB by 1-bit synchronization of SCLK. A rising edge on SCLK is allowed
100 ns after a rising edge of LAT.
LAT
4
1
I
Edge triggered latch. The data in the on/off control data shift register are transferred to the
on/off control data latch at this rising edge. At the same time, the data in the on/off control shift
register are replaced with TI reserved data for production test. LAT must be toggled only once
after the shift data are updated to avoid the on/off control latch data being replaced with TI
reserved data in the shift register. The reserved data is not a fixed number.
BLANK
21
18
I
Blank, all outputs. When BLANK = high level, all constant-current outputs (OUT0–OUT15) are
forced off. When BLANK = low level, all constant-current outputs are controlled by the on/off
control data in the data latch.
IREF
23
20
I/O
Constant-current value setting, OUT0–OUT15 sink constant-current is set to desired value by
connection to an external resistor between IREF and GND.
SOUT
22
19
O
Serial data output. This output is connected to the MSB of the on/off data shift register. SOUT
data changes at the rising edge of SCLK.
OUT0
5
2
O
Constant-current output. Each output can be tied together with others to increase the
constant-current. Different voltages can be applied to each output.
OUT1
6
3
O
Constant-current output
OUT2
7
4
O
Constant-current output
OUT3
8
5
O
Constant-current output
OUT4
9
6
O
Constant-current output
OUT5
10
7
O
Constant-current output
OUT6
11
8
O
Constant-current output
OUT7
12
9
O
Constant-current output
OUT8
13
10
O
Constant-current output
OUT9
14
11
O
Constant-current output
OUT10
15
12
O
Constant-current output
OUT11
16
13
O
Constant-current output
OUT12
17
14
O
Constant-current output
OUT13
18
15
O
Constant-current output
OUT14
19
16
O
Constant-current output
OUT15
20
17
O
Constant-current output
VCC
24
21
—
Power-supply voltage
GND
1
22
—
Power ground
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
SOUT
GND
GND
Figure 1. SIN, SCLK, LAT, BLANK
Figure 2. SOUT
OUTn
GND
Figure 3. OUT0 Through OUT15
TEST CIRCUITS
RL
VCC
VCC
OUTn
IREF
RIREF
VCC
VLED
(1)
GND
SOUT
VCC
CL
GND
Figure 4. Rise Time and Fall Time Test Circuit for
OUTn
CL
(1)
Figure 5. Rise Time and Fall Time Test Circuit for
SOUT
(1) CL includes measurement probe and jig capacitance.
VCC
OUT0
¼
VCC
IREF
OUTn
¼
RIREF
GND OUT15
VOUTn
VOUTFIX
Figure 6. Constant-Current Test Circuit for OUTn
8
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TIMING DIAGRAMS
TWH0, TWL0, TWH1, TWH2, TWL2:
VCC
(1)
INPUT
50%
GND
TWH
TWL
TSU0, TSU1, TH0, TH1:
VCC
CLOCK
(1)
INPUT
50%
GND
TSU
TH
VCC
DATA/CONTROL
(1)
INPUT
50%
GND
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 7. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2:
VCC
(1)
INPUT
50%
GND
tD
VOH or VOUTn
90%
OUTPUT
50%
10%
VOL or VOUTn
tR or tF
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Output Timing
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SIN
DATA
0A
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DATA
15B
DATA
13B
DATA
14B
DATA
12B
DATA
11B
DATA
3B
DATA
2B
DATA
0B
DATA
1B
TH0
TSU0
TH1
TWH0
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
DATA
10C
1
2
3
TWL0
4
5
6
TSU1
SCLK
1
2
3
4
5
13
14
15
16
TWH1
LAT
DATA
0A
RSV
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
RSV 0A
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
Shift Register
LSB+1 Data (Internal)
DATA
1A
RSV
RSV
DATA
15B
DATA
14B
DATA
13B
DATA
4B
DATA
3B
DATA
2B
DATA
1B
RSV 1A
RSV
DATA
DATA
DATA
DATA
Shift Register
MSB-1 Data (Internal)
DATA
14A
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DATA
15B
DATA
14B
RSV 14A
RSV
RSV
RSV
RSV
RSV
Shift Register
MSB Data (Internal)
DATA
15A
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DATA
15B
RSV 15A
RSV
RSV
RSV
RSV
RSV
¼
¼
On/Off Control
Latch Data (Internal)
SOUT
¼
Shift Register
LSB Data (Internal)
Previous On/Off Latch Data
DATA
15A
RSV
RSV
RSV
tD0
RSV
RSV
RSV
RSV
DATA
15B
Latest On/Off Latch Data
RSV 15A
RSV
tR0/tF0
RSV
RSV
RSV
RSV
tWH2
BLANK
tWL2
tD2
tD1
OFF
OUTn
(1)
OFF
OUTn
(2)
tD2
tF1
tD1
OFF
(3)
ON
ON
OFF
OFF
OUTn
(4)
tOUTON
OFF
ON
ON
OFF
OUTn
tD1
OFF
ON
ON
ON
tR1
ON
(1) On/off latched data are '1'.
(2) On/off latched data are changed from '1' to '0' at the second LAT signal.
(3) On/off latched data are changed from '0' to '1' at the second LAT signal.
(4) On/off latched data are '0'.
Figure 9. Timing Diagram
10
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TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR
vs OUTPUT CURRENT
POWER DISSIPATION RATE
vs FREE-AIR TEMPERATURE
4000
Power Dissipation Rate (mW)
Reference Resistor (W)
100000
25200
10080
10000
5040
3360
2520
2016
1680
TLC59281RGE
3000
2000
TLC59281DBQ
1000
1440
0
1000
0
15
10
5
20
30
25
35
-40
40
Figure 10.
Figure 11.
OUTPUT CURRENT vs
OUTPUT VOLTAGE
OUTPUT CURRENT vs
OUTPUT VOLTAGE
40
IO = 35 mA
TA = +25°C
Output Current (mA)
Output Current (mA)
25
IO = 20 mA
15
IO = 10 mA
10
IO = 2 mA
IO = 5 mA
5
100
38
30
20
80
IO = 30 mA
39
IO = 30 mA
0
37
36
35
34
33
TA = -40°C
32
TA = +25°C
31
TA = +85°C
30
0
1.5
1.0
0.5
2.0
2.5
0
3.0
1.0
0.5
Output Voltage (V)
1.5
2.0
2.5
3.0
Output Voltage (V)
Figure 12.
Figure 13.
ΔIOLC vs AMBIENT TEMPERATURE
ΔIOLC vs OUTPUT CURRENT
4
4
IO = 35 mA
TA = +25°C
3
3
2
2
1
1
DIOLC (%)
DIOLC (%)
60
40
Free-Air Temperature (°C)
35
0
-1
-2
0
-1
-2
VCC = 3.3 V
-3
-4
20
0
-20
Output Current (mA)
-40
-20
0
20
40
60
80
VCC = 3.3 V
-3
VCC = 5 V
100
-4
VCC = 5 V
0
Ambient Temperature (°C)
10
20
30
40
Output Current (mA)
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
CH1 (2 V/div)
CH1-BLANK
(20 ns)
CH2 (2 V/div)
CH2-OUT0
(BLANK = 20 ns)
CH3 (2 V/div)
CH3-OUT15
(BLANK = 20 ns)
IOLC = 35 mA
TA = +25°C
RL = 130 W
CL = 15 pF
VLED = 5.5 V
Time (12.5 ns/div)
Figure 16.
12
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DETAILED DESCRIPTION
SETTING FOR THE CONSTANT SINK CURRENT VALUE
The constant-current values are determined by an external resistor (RIREF) placed between IREF and GND. The
resistor (RIREF) value is calculated by Equation 1.
RIREF (kW) =
VIREF (V)
´ 42
IOLC (mA)
Where:
VIREF = the internal reference voltage on the IREF pin (typically 1.20 V)
(1)
IOLC must be set in the range of 2 mA to 35 mA. The constant sink current characteristic for the external resistor
value is shown in Figure 10. Table 1 describes the constant-current output versus external resistor value.
Table 1. Constant-Current Output versus External Resistor Value
IOLCMax (mA, Typical)
RIREF (kΩ)
35
1.44
30
1.68
25
2.02
20
2.52
15
3.36
10
5.04
5
10.1
2
25.2
CONSTANT-CURRENT DRIVER ON/OFF CONTROL
When BLANK is low, the corresponding output is turned on if the data in the on/off control data latch are '1' and
remains off if the data are '0'. When BLANK is high, all outputs are forced off. This control is shown in Table 2.
Table 2. On/Off Control Data Truth Table
ON/OFF CONTROL LATCH DATA
CONSTANT-CURRENT OUTPUT STATUS
0
Off
1
On
When the IC is initially powered on, the data in the on/off control shift register and data latch are not set to the
respective default value. Therefore, the on/off control data must be written to the data latch before turning the
constant-current output on. BLANK should be at a high level when powered on because the constant-current
may be turned on as a result of random data in the on/off control latch.
The on/off data corresponding to any unconnected OUTn outputs should be set to ‘0’ before turning on the
remaining outputs. Otherwise, the supply current (ICC) increases while the LEDs are on.
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Product Folder Link(s): TLC59281
13
TLC59281
SBVS139 – JANUARY 2010
www.ti.com
REGISTER CONFIGURATION
The TLC59281 has an on/off control data shift register and data latch. Both the on/off control shift register and
latch are 16 bits long and are used to turn the constant-current drivers on and off. Figure 17 shows the shift
register and latch configuration. The data at the SIN pin are shifted in to the LSB of the shift register at the rising
edge of the SCLK pin; SOUT data change at the rising edge of SCLK. The timing diagram for data writing is
shown in Figure 18. The driver on/off is controlled by the data in the on/off control data latch.
The on/off data are latched into the data latch by a rising edge of LAT after the data are written into the on/off
control shift register by SIN and SCLK. At the same time, the data in the on/off control shift register are replaced
with TI reserved data for production test. Therefore, LAT must be input only once after the on/off data update to
avoid the on/off control data latch being replaced with TI reserved data in the shift register. When the IC initially
powers on, the data in the on/off control shift register and latch are not set to the default values; on/off control
data must be written to the on/off control data latch before turning the constant-current output on. BLANK should
be high when the IC is powered on because the constant-current may be turned on at that time as a result of
random values in the on/off data latch. All constant-current outputs are forced off when BLANK is high.
On/Off Control Shift Register (1 Bit ´ 16 Channels)
SOUT
MSB
15
14
13
12
On/Off Data
for
OUT15
On/Off Data
for
OUT14
On/Off Data
for
OUT13
On/Off Data
for
OUT12
4
11
¼
3
2
1
LSB
0
On/Off Data
for
OUT3
On/Off Data
for
OUT2
On/Off Data
for
OUT1
On/Off Data
for
OUT0
3
2
1
LSB
0
On/Off Data
for
OUT3
On/Off Data
for
OUT2
On/Off Data
for
OUT1
On/Off Data
for
OUT0
SIN
SCLK
¼
MSB
15
14
13
12
On/Off Data
for
OUT15
On/Off Data
for
OUT14
On/Off Data
for
OUT13
On/Off Data
for
OUT12
4
11
On/Off Control Data Latch (1 Bit ´ 16 Channels)
¼
LAT
16 Bits
To Constant Current Driver Control Block
Figure 17. On/Off Control Shift Register and Latch Configuration
14
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
TLC59281
www.ti.com
SBVS139 – JANUARY 2010
SIN
DATA
0A
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
11B
1
2
3
4
5
DATA
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
DATA
10C
16
1
2
3
4
5
6
SCLK
13
14
15
LAT
DATA
0A
RSV
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
RSV 0A
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
Shift Register
LSB+1 Data (Internal)
DATA
1A
RSV
RSV
DATA
15B
DATA
14B
DATA
13B
DATA
4B
DATA
3B
DATA
2B
DATA
1B
RSV 1A
RSV
DATA
15C
DATA
14C
DATA
13C
DATA
12C
Shift Register
MSB-1 Data(Internal)
DATA
14A
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DATA
15B
DATA
14B
RSV 14A
RSV
RSV
RSV
RSV
RSV
Shift Register
MSB Data(Internal)
DATA
1A
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DATA
15B
RSV 15A
RSV
RSV
RSV
RSV
RSV
On/Off Control
Latch Data (Internal)
SOUT
¼
¼
¼
Shift Register
LSB Data (Internal)
Latest On/Off Latch Data
Previous On/Off Latch Data
DATA
1A
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DATA
15B
RSV 15A
RSV
RSV
RSV
RSV
RSV
BLANK
OUTn
(1)
ON
OUTn
(2)
(3)
ON
OFF
OFF
ON
OUTn
OFF
OFF
OFF
ON
OFF
OUTn
(4)
OFF
OFF
ON
ON
OFF
OFF
ON
(1) On/off latched data are '1'.
(2) On/off latched data are changed from '1' to '0' at the second LAT signal.
(3) On/off latched data are changed from '0' to '1' at the second LAT signal.
(4) On/off latched data are '0'.
Figure 18. On/Off Control Operation
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Product Folder Link(s): TLC59281
15
PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TLC59281DBQ
ACTIVE
SSOP/QSOP
DBQ
24
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
TLC59281DBQR
ACTIVE
SSOP/QSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
TLC59281RGE
PREVIEW
TLC59281RGER
ACTIVE
VQFN
RGE
24
24
3000
Green (RoHS
& no Sb/Br)
TBD
CU NIPDAU Level-2-260C-1 YEAR
Call TI
Call TI
Request Free Samples
Samples Not Available
TLC59281RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC59281RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TLC59281RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC59281RGER
VQFN
RGE
24
3000
346.0
346.0
29.0
TLC59281RGET
VQFN
RGE
24
250
190.5
212.7
31.8
Pack Materials-Page 2
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