TI TLC59731

TLC59731
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SBVS222 – FEBRUARY 2013
3-Channel, 8-Bit, PWM LED Driver
with Single-Wire Interface (EasySet)
Check for Samples: TLC59731
FEATURES
APPLICATIONS
•
•
•
1
2
•
•
•
•
•
•
•
•
•
•
•
Three Sink Current Channels
Current Capability:
– 50 mA per Channel
Grayscale (GS) Control with PWM:
– 8-Bit (256 Steps) with Simple Gamma
Correction
Single-Wire Interface (EasySet)
Power-Supply (VCC) Voltage Range:
– No Internal Shunt Regulator Mode:
3 V to 5.5 V
– Internal Shunt Regulator Mode: 3 V to 6 V
OUT Terminals Maximum Voltage: Up to 21 V
Integrated Shunt Regulator
Data Transfer Maximum Rate:
– Bits per Second (bps): 1 Mbps
Internal GS Clock Oscillator: 6 MHz (typ)
Display Repeat Rate: 3.1 kHz (typ)
Output Delay Switching to Prevent Inrush
Current
Unlimited Device Cascading
Operating Temperature: –40°C to +85°C
RGB LED Cluster Lamp Display
DESCRIPTION
The TLC59731 is an easy-to-use, 3-channel, 50-mA
sink current LED driver. The single-wire, 1-Mbps
serial interface (EasySet) provides a solution for
minimizing wiring cost. The LED driver provides 8-bit
pulse width modulation (PWM) resolution and a
simple gamma correction feature. The display repeat
rate is achieved at 3.1 kHz (typ) with an integrated 6MHz grayscale (GS) clock oscillator. The driver also
provides unlimited cascading capability.
Output sink current can be set by each external
resistor connected to the OUTn terminal in series.
The TLC59731 has an internal shunt regulator that
can be used for higher VCC power-supply voltage
applications.
VCC
Power
Supply
(5 V)
GND
GND
OPEN
or GND
TEST
Device
VCC
OUT0
OUT1
OPEN
or GND
GND
VCC
TEST
OUT0
Device
OUT2
Controller
SDI
SDO
OUT1
OUT2
SDI
SDO
Figure 1. Typical Application Circuit Example 1 (No Internal Shunt Regulator Mode)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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TLC59731
SBVS222 – FEBRUARY 2013
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DESCRIPTION (CONTINUED)
LED
Lamp
Power
Supply
VLED
Device and
Controller
Power
Supply
VCC
GND
OPEN
or GND
GND
VCC
TEST
OUT0
Device
Optional
OPEN
or GND
OUT1
GND
VCC
TEST
OUT0
OUT1
Device
OUT2
OUT2
Controller
SDI
Optional
SDI
SDO
SDO
Figure 2. Typical Application Circuit Example 2 (No Internal Shunt Regulator Mode)
VLED
Power
Supply
GND
OPEN
or GND
RVCC
RVCC
CVCC
CVCC
GND
VCC
TEST
OUT0
+5 V
Device
Optional
OPEN
or GND
OUT1
GND
VCC
TEST
OUT0
OUT1
Device
OUT2
Controller
SDI
Optional
OUT2
SDI
SDO
SDO
Figure 3. Typical Application Circuit Example 3 (Internal Shunt Regulator Mode)
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION (1)
(1)
2
PRODUCT
PACKAGE-LEAD
TLC59731
SO-8
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
TLC59731DR
Tape and Reel, 2500
TLC59731D
Tube, 75
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
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SBVS222 – FEBRUARY 2013
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
Voltage (2)
MIN
MAX
UNIT
Supply, VCC
VCC
–0.3
+7.0
V
Input range, VIN
SDI
–0.3
VCC + 1.2
V
OUT0 to OUT2
–0.3
+21
V
SDO
–0.3
+7.0
V
0
+60
mA
Operating junction, TJ
–40
+150
°C
Storage, Tstg
–55
Output range, VOUT
Current
Output (dc), IOUT
Temperature
Electrostatic discharge (ESD) ratings:
(1)
(2)
OUT0 to OUT2
+150
°C
Human body model (HBM)
8000
V
Charged device model (CDM)
2000
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
THERMAL INFORMATION
TLC59731
THERMAL METRIC (1)
D
(SO)
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance
134.6
θJCtop
Junction-to-case (top) thermal resistance
88.6
θJB
Junction-to-board thermal resistance
75.3
ψJT
Junction-to-top characterization parameter
37.7
ψJB
Junction-to-board characterization parameter
74.8
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
3.0
5.0
5.5
V
6.0
V
DC CHARACTERISTICS
VCC
Supply voltage
No internal shunt regulator
mode
Internal shunt regulator mode
VO
Voltage applied to output
OUT0 to OUT2
21
V
VIH
High-level input voltage
SDI
0.7 × VCC
VCC
V
VIL
Low-level input voltage
SDI
GND
0.3 × VCC
V
VIHYST
Input voltage hysteresis
SDI
IOH
High-level output current
SDO
IOL
Low-level output current
IREG
Shunt regulator sink current
TA
Operating free-air temperature range
–40
TJ
Operating junction temperature range
–40
+125
°C
kHz
0.2 × VCC
SDO
OUT0 to OUT2
VCC
V
–2
mA
2
mA
50
mA
20
mA
+85
°C
AC CHARACTERISTICS
fCLK
Data transfer rate
SDI
20
1000
tSDI
SDI input pulse duration
SDI
275
0.5 / fCLK
tWH
Pulse duration, high
SDI
14
tWL
Pulse duration, low
SDI
14
tH0
Hold time: end of sequence (EOS)
SDI↑ to SDI↑
3.5 / fCLK
tH1
Hold time: data latch (GSLAT)
SDI↑ to SDI↑
8 / fCLK
4
(SDI)
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ns
ns
ns
5.5 / fCLK
µs
µs
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SBVS222 – FEBRUARY 2013
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 3 V to 6.0 V, and CVCC = 0.1 µF. Typical values at TA = +25°C and VCC = 5.0 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage (SDO)
IOH = –2 mA
VOL
Low-level output voltage (SDO)
IOL = 2 mA
VR
Shunt regulator output voltage (VCC) ICC = 1 mA, SDI = low
ICC0
Supply current (VCC)
ICC1
MAX
UNIT
VCC – 0.4
MIN
TYP
VCC
V
0
0.4
V
5.9
V
VCC = 3.0 V to 5.5 V, SDI = low, all grayscale (GSn)
= FFh, VOUTn = 0.6 V, SDO = 15 pF
2.3
3.5
mA
VCC = 3.0 V to 5.5V , SDI = 1 MHz, GSn = FFh,
VOUTn = 0.6 V, SDO = 15 pF
2.6
4.5
mA
IOL
LED output current
(OUT0 to OUT2)
All OUTn = on, VOUTn = 0.6 V
IOLKG
Output leakage current
(OUT0 to OUT2)
GSn = 00h, VOUTn = 21 V
RPD
Internal pull-down resistance (SDI)
At SDI
32
40
mA
TJ = –40°C to +85°C
0.1
TJ = +85°C to +125°C
0.2
μA
μA
1
MΩ
SWITCHING CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 3.0 V to 5.5 V, CL = 15 pF, RL = 110 Ω, and VLED = 5.0 V, unless otherwise noted.
Typical values are at TA = +25°C and VCC = 5.0 V.
PARAMETER
tR0
tR1
tF0
tF1
Rise time
Fall time
tD0
TEST CONDITIONS
SDO
MIN
TYP
MAX
2
6
12
ns
200
400
ns
6
12
ns
200
400
ns
50
ns
OUTn (on → off)
SDO
2
OUTn (off → on)
SDI↑ to SDO↑
30
Propagation delay
OUT0↓ to OUT1↓, OUT1↓to OUT2↓,
OUT0↑ to OUT1↑, OUT1↑to OUT2↑
25
tWO
Shift data output one pulse duration
SDO↑ to SDO↓
fOSC
Internal GS oscillator frequency
tD1
ns
75
125
250
4
6
8
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UNIT
ns
MHz
5
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SBVS222 – FEBRUARY 2013
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PARAMETER MEASUREMENT INFORMATION
PIN-EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
SDI
SDO
GND
GND
Figure 4. SDI
Figure 5. SDO
OUTn
(1)
GND
(1) n = 0 to 2.
Figure 6. OUT0 Through OUT2
TEST CIRCUITS
RL
VCC
VCC
OUTn
VCC
(1)
GND
(2)
CL
VLED
SDO
VCC
GND
CL
(1)
(1) n = 0 to 2.
(2) CL includes measurement probe and jig capacitance.
(1) CL includes measurement probe and jig capacitance.
Figure 7. Rise Time and Fall Time Test Circuit for
OUTn
Figure 8. Rise Time and Fall Time Test Circuit for
SDO
6
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TIMING DIAGRAMS
tWH, tW L
VCC
SDI
(1)
50%
tW H
tH0, tH1
1st Data of Next Device (tH0 case) or
1st Data of Next Sequence (tH1 case).
32nd Data
SDI
GND
tW L
VCC
(1)
50%
GND
tH0, tH1
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Input Timing
tR0, tF0, tD0, tW 0
VCC
(1)
SDI
50%
GND
tD0
tW0
VOH
90%
SDO
50%
10%
tR0
VOL
tF0
tR1, tF1, tD1
VOUTnH
OUTn
50%
VOUTnL
tD1
tD1
VOUTnH
90%
OUTn + 1
50%
10%
VOUTnL
tF1
(1)
tR1
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 10. Output Timing
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VCC
1st Device
1st Data (0)
2nd
Data (0)
3rd
Data (1)
4th
Data (1)
32nd
Data (0)
5th
Data (1)
2nd Device
1st Data (0)
2nd
Data (0)
1st Device
1st Data (0)
32nd
Data (0)
SDI
fCLK(SDI)
fCLK(SDI)
Data Transfer
Period Memory
(Internal in all Devices)
tSDI
tWH
tWL
tH0 (for EOS)
tH1 (for GSLAT)
Data transfer period (t CYCLE) is stored.
Data transfer period (t CYCLE) is stored.
Recognized Data,
SIN Signal
(Internal in 1st Device)
1st Data (0)
2nd Data (0)
3rd Data (1)
4th Data (1)
31st
Data
32nd Data (0)
1st Data (0)
31st
Data
32nd Data
1st Data (0)
30th
Data
31st Data
5th Data (1)
SCLK Signal
(Internal in 1st Device)
32-Bit Shift Register LSB
(Internal in 1st Device)
1st Data (0)
2nd Data (0)
3rd Data (1)
4th Data (1)
1st Data (0)
2nd Data (0)
3rd Data (1)
5th Data (1)
32-Bit Shift Register LSB+1
(Internal in 1st Device)
32nd Data (0)
4th Data (1)
32-Bit Shift Register MSB-1
(Internal in 1st Device)
1st Data (0)
32-Bit Shift Register MSB
(Internal in 1st Device)
2nd Data (0)
3rd Data (0)
1st Data (0)
2nd Data (0)
High = SDI data are output from SDO.
OUTEN Signal
(Internal)
Low = SDI data are not output from SDO.
GSLAT Signal
(Internal in 1st Device)
GS Data Latch
(Internal in 1st Device)
(All GS data are ‘0’ when VCC powers up.)
New GS Data
tD0
tWO
SDO
tF0
tR0
SCLK Signal
(Internal in 2nd Device)
32-Bit Shift Register LSB
(Internal in 2nd Device)
1st Data (0)
32nd Data (0)
tH1
GSLAT Signal
(Internal in 2nd Device)
24-Bit GS Data Latch
(Internal in 2nd Device)
New GS Data
(All GS data are ‘0’ when VCC powers up.)
(VOUTnH)
OUT0
OFF
ON
tF1
(VOUTnL)
(1)
tR1
OUT1
OUT2
OFF
(1)
ON
tD1
OFF
(1)
ON
tD1
(1) OUTn on-time changes, depending on the data in the 24-bit GS data latch.
Figure 11. Data Write and OUTn Switching Timing
8
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PIN CONFIGURATION
D PACKAGE
SO-8
(Top View)
1
8
VCC
OUT1 2
7
TEST
OUT2
3
6
SDI
GND
4
5
SDO
OUT0
PIN DESCRIPTIONS
PIN
NAME
NO.
I/O
GND
4
—
OUT0
1
O
OUT1
2
O
OUT2
3
O
DESCRIPTION
Power ground
Sink driver outputs.
Multiple outputs can be configured in parallel to increase the sink drive current capability.
Different voltages can be applied to each output.
SDI
6
I
Serial data input. This pin is internally pulled down to GND with a 1-MΩ (typ) resistor.
SDO
5
O
Serial data output
TEST
7
—
TI internal test terminal. This pin must be connected to GND or left open.
VCC
8
—
Power-supply voltage
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FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
Shunt
Regulator
reset
UVLO
Pulse
Generator
SDI
outen
SDO
LSB
MSB
sin
Interface
Control
32-Bit Shift Register
sclk
0
31
Upper 8 Bits
Lower 24 Bits
LSB
Command
Decoder (3Ah)
MSB
gslat
24-Bit GS Data Latch
0
Internal
Oscillator
6 MHz
reset
23
GS Clock
Counter
24
8
reset
TEST
8-Bit PWM Timing Control
with Simple Gamma Correction
TEST
3
Switching Delay
3
GND
3-Channel Sink Driver
OUT0
10
OUT1
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OUT2
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TYPICAL CHARACTERISTICS
At TA = +25°C and VCC = 12 V, unless otherwise noted.
1.0
Ta
±40°
TA = ±40ƒC
0.9
TA = +25ƒC
Ta
+25°
0.8
TA = +85ƒC
Ta
+85°
Output Voltage (V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
10
20
30
40
50
Output Current (mA)
C001
Figure 12. OUTPUT CURRENT vs OUTPUT VOLTAGE (OUTn)
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DETAILED DESCRIPTION
SINK CURRENT VALUE SETTING
The typical sink current value of each channel (IOUTn) can be set by resistor (RLn) that is placed between the LED
cathode and OUTn pins, as shown in Figure 13. The typical sink current value can be calculated by Equation 1
and the typical resistor value can be calculated by Equation 2.
VLED (V) - VF_TOTAL (V) - VOUTn (V)
IOUTn (mA) =
RLn (W)
NOTE: n = 0 to 2.
RLn (W) =
(1)
VLED (V) - VF_TOTAL (V) - VOUTn (V)
IOUTn (mA)
NOTE: n = 0 to 2.
(2)
Where:
VLED = the LED anode voltage, VF_TOTAL = the total LED forward voltage, and VOUTn = the OUTn output voltage.
Note that the typical VOUTn value is 0.6 V with a 40-mA output current; see Figure 12.
VLED
Power
Supply
RVCC
RVCC
GND
+5V
Open
or
GND
CVCC
CVCC
(0.1 mF)
(0.1 mF)
GND
VCC
TEST
OUT0
1st Device
RL0
OUT1
OUT2
Controller
SDI
VF_TOTAL
Open
or
GND
RL1
GND
VCC
TEST
OUT0
RL0
2nd Device
RL2
OUT1
OUT2
SDO
SDI
Optional
RL1
RL2
SDO
Figure 13. Internal Shunt Regulator Mode Application Circuit
RESISTOR AND CAPACITOR VALUE SETTING FOR SHUNT REGULATOR
The TLC59731 internally integrates a shunt regulator to regulate VCC voltage. Refer to Figure 12 for an
application circuit that uses the internal shunt regulator through a resistor, RVCC. The recommended RVCC value
can be calculated by Equation 3.
VLED (V) - 5.9 V
VLED (V) - 5.9 V
< RVCC <
6 mA
8 mA
(3)
Table 1 shows the typical resistor value for several VLED voltages. Note that the CVCC value should be 0.1 μF.
Table 1. Resistor Example for Shunt Resistor versus LED Voltage
12
VLED (V)
RVCC (Ω)
RESISTOR WATTAGE (W)
9
470
0.02
12
910
0.04
18
1800
0.08
24
2700
0.12
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GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The TLC59731 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The PWM data bit length for each output is 8 bits. The architecture of 8 bits per channel results in 256
brightness steps, from 0% to 99.9% on-time duty cycle.
The PWM operation for OUTn is controlled by an 8-bit grayscale (GS) counter. The GS counter increments on
each internal GS clock (GSCLK) rising edge. All OUTn are turned on when the GS counter is ‘1’. All OUTn turn
on when the GS count is '1', except when OUTn are programed to GS data '0' in the 24-bit GS data latch. After
turning on, each output is turns off when the GS counter value exceeds the programmed GS data for the output.
The GS counter resets to 00h and all outputs are forced off when the GS data are written to the 24-bit GS data
latch. Afterwards, the GS counter begins incrementing and PWM control is started from the next internal GS
clock.
Table 2 summarizes the GS data values versus the output ideal on-time duty cycle. The on-time duty cycle is not
proportional to the GS data because a simple gamma correction is implemented in the TLC59731. Furthermore,
actual on-time differs from the ideal on-time because the output drivers and control circuit have some timing
delay. When the device is powered on, all outputs are forced off and remain off until the non-zero GS data are
written to the 24-bit GS data latch.
Table 2. Output Duty Cycle and Total On-Time versus GS Data
GS DATA
DECIMAL
HEX
NO. OF GSCLKs
OUTn TURNS ON
NO. OF GSCLKs
OUTn TURNS OFF
TOTAL IDEAL TIME
(µs)
0
0
Off
Off
0
0
1
1
1
2
0.2
0.1
2
2
1
4
0.5
0.2
3
3
1
6
0.8
0.3
—
—
—
—
—
—
6
6
1
12
1.8
0.6
7
7
1
14
2.2
0.7
8
8
1
18
2.8
0.9
9
9
1
22
3.5
1.1
10
10
1
26
4.2
1.3
—
—
—
—
—
—
30
1E
1
106
17.5
5.5
31
1F
1
110
18.2
5.7
32
20
1
118
19.5
6.2
33
21
1
126
20.8
6.6
34
22
1
134
22.2
7.0
—
—
—
—
—
—
62
3E
1
358
59.5
18.8
63
3F
1
366
60.8
19.2
64
40
1
374
62.2
19.6
65
41
1
382
63.5
20.0
66
42
1
390
64.8
20.5
ON-TIME DUTY (%)
—
—
—
—
—
—
127
7F
1
878
146.2
46.1
128
80
1
886
147.5
46.5
129
81
1
894
148.8
47.0
—
—
—
—
—
—
253
FD
1
1886
314.2
99.1
254
FE
1
1894
315.5
99.5
255
FF
1
1902
316.8
99.9
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PWM Control
The GS counter keeps track of the number of grayscale reference clocks (GSCLKs) from the internal oscillator.
Each output stays on while the counter is less than or equal to the programmed GS value. Each output turns off
when the GS counter is greater than the GS value in the 24-bit GS data latch. Figure 14 illustrates the PWM
operation timing.
13
1 2
Grayscale
Reference Clock, GSCLK
(Internal)
OUTn
(GSDATA = 0)
OFF
3 4
5 6
15
14
17
110
111
16
113
116
114
117
112
115
118
1886
1889
1892
1895
1898
1901
1887
1890
1893
1896
1899
1902
1888
1891
1894
1897
1900
1903
(VOUTnH)
No river
turns on.
ON
(VOUTnL)
T = GSCLK ´ 1
OUTn
(GSDATA = 1)
OFF
ON
T = GSCLK ´ 3
OFF
OUTn
(GSDATA = 2)
ON
T = GSCLK ´ 5
OUTn
(GSDATA = 3)
OFF
ON
T = GSCLK ´ 13
OFF
OUTn
(GSDATA = 7)
ON
T = GSCLK ´ 17
OFF
OUTn
(GSDATA = 8)
ON
T = GSCLK ´ 109
OUTn
(GSDATA = 31)
OFF
ON
T = GSCLK ´ 117
OUTn
(GSDATA = 32)
OFF
ON
T = GSCLK ´ 1885
OUTn
(GSDATA = 253)
OFF
ON
T = GSCLK ´ 1893
OFF
OUTn
(GSDATA = 254
ON
T = GSCLK ´ 1901
OUTn
(GSDATA = 255)
T = GSCLK ´ 1
OFF
ON
(1) Actual on-time differs from the ideal on-time.
Figure 14. PWM Operation
14
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REGISTER AND DATA LATCH CONFIGURATION
The TLC59731 has a 32-bit shift register and a 24-bit data latch that stores GS data. When the internal GS data
latch pulse is generated and the data of the eight MSBs in the shift register are 3Ah, the lower 24-bit data in the
32-bit shift register are copied into the 24-bit GS data latch. If the data of the eight MSBs is not 3Ah, the 24-bit
data are not copied into the 24-bit GS data latch. Figure 15 shows the shift register and GS data latch
configurations. Table 3 shows the 32-bit shift register bit assignment.
32-Bit Shift Register
LSB
MSB
Write
Command
Bit 7 (1)
31
---
Write
Command
Bit 0 (0)
OUT2
GS Data
Bit 7
24
23
---
OUT2
GS Data
Bit 0
OUT1
GS Data
Bit 7
16
15
OUT1
GS Data
Bit 0
OUT0
GS Data
Bit 7
8
7
---
OUT0
GS Data
Bit 0
---
Shift Data (Internal)
Shift Clock (Internal)
0
24 Bits
8 Bits
MSB
23
8-Bit Write
Command
Decoder
The internal latch pulse is generated after 8 tCYCLES without SDI clocking.
24-Bit GS Data Latch
---
OUT2
GS Data
Bit 7
16
15
OUT2
GS Data
Bit 0
OUT1
GS Data
Bit 7
8
7
OUT1
GS Data
Bit 0
OUT0
GS Data
Bit 7
---
---
LSB
0
OUT0
GS Data
Bit 0
GS Data
Latch Pulse
(Internal)
Write Command = 3Ah (00111010b)
24 Bits
To Grayscale Timing
Control Circuit
Figure 15. Common Shift Register and Control Data Latches Configuration
Table 3. 32-Bit Shift Register Data Bit Assignment
BITS
BIT NAME
CONTROLLED CHANNEL/FUNCTIONS
0 to 7
GSOUT0
GS data bits 0 to 7 for OUT0
8 to 15
GSOUT1
GS data bits 0 to 7 for OUT1
16 to 23
GSOUT2
GS data bits 0 to 7 for OUT2
WRTCMD
Data write command (3Ah) for GS data.
The lower 24-bit GS data in the 32-bit shift register are copied to the GS data latch
when the internal GS latch is generated (when these data bits are 3Ah,
00111010b).
24 to 32
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ONE-WIRE INTERFACE (EasySet) DATA WRITING METHOD
There are four sequences to write GS data into the TLC59731 via a single-wire interface. This section discusses
each sequence in detail.
Data Transfer Rate (tCYCLE) Measurement Sequence
The TLC59731 measures the time between the first and second SDI rising edges either after the device is
powered up or when the GS data latch sequence is executed (as described in the GS Data Latch Sequence
(GSLAT) section) and the time is internally stored as tCYCLE. tCYCLE serves as a base time used to recognize one
complete data write operation, a 32-bit data write operation, and a GS data write operation to the GS data latch.
tCYCLE can be set between 1 µs and 50 µs (fCLK(SDI) = 20 kHz to 1000 kHz). In this sequence, two instances of
data ‘0’ are written to the LSB side of the 32-bit shift register. Figure 16 shows the tCYCLE measurement timing.
1st SID
Rising Edge
2nd SID
Rising Edge
SDI
tCYCLE
Figure 16. Data Transfer Rate (tCYCLE) Measurement
Data ‘0’ and Data ‘1’ Write Sequence (Data Write Sequence)
When the second SDI rising edge is not input before 50% of tCYCLE elapses from the first SDI rising edge input,
the second rising edge is recognized as data '0'. When the second SDI rising edge is input before 50% of tCYCLE
elapses from the first SDI rising edge input, the second rising edge is recognized as data '1'. This write sequence
must be repeated 30 times after the tCYCLE measurement sequence in order to send the write command to the
lower 6-bit (3Ah) and 24-bit GS data. Figure 17 shows the data ‘0’ and ‘1’ write timing.
Data 0 Writing
Data 1 Writing
First SDI
Rising Edge
First SDI
Rising Edge
Second SDI
Rising Edge
Dotted line waveform
is accepted.
SDI
tSDI = 0.5 x tCYCLE
When the second SDI
rising edge is not input, it
is recognized as ‘0’.
When the second SDI
rising edge is input by
0.5 x tCYCLE, it
is recognized as ‘1’.
tSDI = 0.5 x tCYCLE
This time must be between tCYCLE x 1.0 and tCYCLE x 2.0
Figure 17. Data ‘0’ and ‘1’ Write Operation
16
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One Communication Cycle End of Sequence (EOS)
One communication cycle end of sequence (EOS) must be input after the 32-bit data are written because the
TLC59731 does not count the number of input data. When SDI is held low for the EOS hold time (tH0), the 32-bit
shift register values are locked and a buffered SDI signal is output from SDO to transfer GS data to the next
device. Figure 18 shows the EOS timing.
The first SDI rising edge of the last input data.
SDI
3.5 x tCYCLE (min) to 5.5 x tCYCLE (max)
32-Bit Shift
Register
(Internal)
Shift register data are locked.
GSLATignal
(Internal)
GS data latch signal is not generated.
24-Bit GS
Data Latch
(Internal)
GS data are not changed.
High = pulse signal output from SDO.
OUTEN Signal
(Internal)
Low = pulse signal not
output from SDO.
SDO
Figure 18. End of Sequence (EOS)
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GS Data Latch (GSLAT) Sequence
A GS data latch (GSLAT) sequence must be input after the 32-bit data for all cascaded devices are written.
When SDI is held low for the data latch hold time (tH1), the 32-bit shift register data in all devices are copied to
the GS data latch in each device. Furthermore, PWM control starts with the new GS data at the same time.
Figure 19 shows the GSLAT timing.
The first SDI rising edge of the last input data.
SDI
8 x tCYCLE (min)
32-Bit Shift
Register
(Internal)
Shift register data are
written after GSLAT is input.
GSLAT Signal
(Internal)
GS Data in
24-Bit
Data Latch
(Internal)
New GS Data
High = pulse signal output from SDO.
OUTEN Signal
(Internal)
Low = pulse signal not output from SDO.
SDO
Figure 19. GS Data Latch Sequence (GSLAT)
18
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HOW TO CONTROL DEVICES CONNECTED IN SERIES
The 8-bit write command and 24-bit grayscale (GS) data for OUT0 to OUT2 (for a total of 32 bits of data) must
be written to the device.Figure 20 shows the 32-bit data packet configuration. When multiple devices are
cascaded (as shown in Figure 21), N times the packet must be written into each TLC59731 in order to control all
devices. There is no limit on how many devices can be cascaded, as long as proper VCC voltage is supplied.
The packet for all devices must be written again whenever any GS data changes.
MSB
LSB
Data 0
Data 0
for tCYCLE for tCYCLE
Data
1
Data
1
Data
1
Data
0
Data
1
Data
0
Data
0 or 1
Bit 7
Write Command Data (8 Bits)
(3Ah = 00111010b)
Data
0 or 1
Bit 0
OUT2
GS Data (8 Bits)
Data
0 or 1
Bit 7
Data
0 or 1
Data
0 or 1
Bit 0
OUT1
GS Data (8 Bits)
Bit 7
Data
0 or 1
Bit 0
OUT0
GS Data (8 Bits)
Figure 20. 32-Bit Data Packet Configuration for One TLC59731
VLED
GND
GND
RVCC
5.0 V
VCC
1st Device
CLK
SDO
SDI
CVCC
0.1 µF
2nd Device
VCC
VCC
Controller
GND
GND
GND
GND
N-1st Device
SDO
SDI
GND
Nth Device
VCC
VCC
SDO
SDI
SDO
SDI
GND
GND
GND
Figure 21. Cascade Connection of N TLC59731 Units (Internal Shunt Regulator Mode)
Refer to Figure 22 for the 32-bit data packet, EOS, and GSLAT input timing of all devices. The function setting
write procedure and display control is as follows:
1. Power-up VCC (VLED); all OUTn are off because GS data are not written yet.
2. Write the 32-bit data packet (MSB-first) for the first device using tCYCLE and the data write sequences
illustrated in Figure 16 and Figure 17. The first 8-bits of the 32-bit data packet are used as the write
command. The write command must be 3Ah (00111010b); otherwise, the 24-bit GS data in the 32-bit shift
register are not copied to the 24-bit GS data latch.
3. Execute one communication cycle EOS (refer to Figure 18) for the first device.
4. Write the 32-bit data packet for the second TLC59731 as described step 2. However, tCYCLE should be set to
the same timing as the first device.
5. Execute one communication cycle EOS for the second device.
6. Repeat steps 4 and 5 until all devices have GS data.
7. The number of total bits is 32 × N. After all data are written, execute a GSLAT sequence as described in
Figure 19 in order to copy the 24-bit LSBs in the 32-bit shift resister to the 24-bit GS data latch in each
device; PWM control starts with the written GS data at the same time.
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VLED Power
MSB
1st Device SDI
LSB
32-Bit Data Packet
for 1st Device
MSB
EOS
1st Device SDO
LSB
MSB
LSB
MSB
LSB
MSB
32-Bit Data Packet
for 2nd Device
EOS
For 3rd
Device
For
N-1th
EOS
32-Bit Data Packet
for Nth Device
GSLAT
32-Bit Data Packet
for 2nd Device
EOS
For 3rd
Device
For
N-1th
EOS
32-Bit Data Packet
for Nth Device
GSLAT
For 3rd
Device
For
N-1st
EOS
32-Bit Data Packet
for Nth Device
GSLAT
32-Bit Data Packet
for Nth Device
GSLAT
N-2nd Device SDO
N-1st Device SDO
LSB
Next Data Packet
for 1st Device
PWM Control Starts
with new GS Data
OUTn
Figure 22. Data Packet Input Order for N TLC59731 Units
CONNECTOR DESIGN APPLICATION
When the connector pin of the device application printed circuit board (PCB) is connected or disconnected to
other PCBs, the power must be turned off to avoid device malfunction or failure. Furthermore, designing the
connector GND pin to be longer than other pins (as shown in Figure 23) is preferable. This arrangement allows
the GND line to either be connected first or disconnected last, which is imperative for proper device function.
GND
VCC (VLED)
N+1st Device PCB
Nth Device PCB
To N-1st
Device
PCB or
Controller
and Power
Supply
To
N+2nd
Device
PCB
SDI
Connector (Male)
Figure 23. Connector Pin Design Application
20
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC59731D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TLC59731DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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