TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 24-Channel, Constant-Current LED Driver with Global Brightness Control and LED Open-Short Detection • • FEATURES 1 • 24-Channel Constant-Current Sink Output with On/Off Control • Current Capability: – 35 mA for 16 Channels – 26.2 mA for 8 Channels • Global Brightness Control (BC) for Each Color Group: 7-Bit (128 Step), Three Groups • LED Power-Supply Voltage up to 15 V • VCC = 3.0 V to 5.5 V • Constant-Current Accuracy: – Channel-to-Channel = ±1% – Device-to-Device = ±3% • CMOS Logic Level I/O • Data Transfer Rate: 35 MHz • BLANK Pulse Width: 15 ns • Open Load, Short Load, and Over-Temperature Detection • Thermal Shutdown (TSD) with Auto Restart • Delay Switching to Prevent Inrush Current 23 Operating Temperature: –40°C to +85°C Packages: HTSSOP-32, QFN-32 APPLICATIONS • • Full-Color LED Displays LED Signboards DESCRIPTION The TLC5952 is a 24-channel, constant-current sink driver. Each channel can be turned on/off with internal register data. The output channels are grouped into three groups of eight channels each. Each channel group has a 128-step global brightness control (BC) function. Both on/off data and BC are writable via a serial interface. The maximum current value of all 24 channels is set by a single external resistor. The TLC5952 has three error detection circuits: LED open detection (LOD), LED short detection (LSD), and a thermal error flag (TEF). The error detection is read via a serial interface. VLED + OUTR0 DATA ¼ ¼ ¼ ¼ ¼ ¼ ¼ SIN SCLK OUTB7 SCLK LAT LAT BLANK BLANK OUTR0 SOUT OUTB7 SOUT SCLK VCC TLC5952 IC1 ¼ SIN LAT VCC BLANK VCC TLC5952 ICn GND VCC GND Controller IREF IREF RIREF RIREF 3 ERROR READ Typical Application Circuit (Multiple Daisy-Chained TLC5952s) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Incorporated. All other trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD TLC5952 HTSSOP-32 PowerPAD™ 5-mm × 5-mm QFN-32 (2) TLC5952 (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TLC5952DAPR Tape and Reel, 2000 TLC5952DAP Tube, 46 TLC5952RHBR Tape and Reel, 3000 TLC5952RHBT Tape and Reel, 250 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Product preview device. ABSOLUTE MAXIMUM RATINGS (1) (2) Over operating free-air temperature range, unless otherwise noted. PARAMETER VCC Supply voltage IOUT Output current (dc) VIN Input voltage range VCC –0.3 to +6.0 V 45 mA OUTB0-OUTB7 35 mA SIN, SCLK, LAT, BLANK, IREF –0.3 to VCC + 0.3 V SOUT –0.3 to VCC + 0.3 V –0.3 to +16 V Output voltage range TJ(max) Operation junction temperature TSTG Storage temperature range (1) (2) 2 UNIT OUTR0-OUTR7, OUTG0-OUTG7 VOUT ESD rating TLC5952 OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7 +150 °C –55 to +150 °C Human body model (HBM) 2000 V Charged device model (CDM) 500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 DISSIPATION RATINGS PACKAGE DERATING FACTOR ABOVE TA = +25°C TA < +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING HTSSOP-32 with PowerPAD soldered (1) 42.54 mW/°C 5318 mW 3403 mW 2765 mW HTSSOP-32 with PowerPAD not soldered (2) 22.56 mW/°C 2820 mW 1805 mW 1466 mW 27.86 mW/°C 3482 mW 2228 mW 1811 mW QFN-32 (1) (2) (3) (3) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2-oz. copper. For more information, see SLMA002 (available for download at www.ti.com). With PowerPAD not soldered onto copper area on PCB. The package thermal impedance is calculated in accordance with JESD51-5. RECOMMENDED OPERATING CONDITIONS At TA = –40°C to +85°C, unless otherwise noted. TLC5952 PARAMETER MIN NOM MAX UNIT DC CHARACTERISTICS: VCC = 3 V to 5.5 V VCC Supply voltage 3.0 5.5 V 15 V V VO Voltage applied to output OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7 VIH High level input voltage SIN, SCLK, LAT, BLANK 0.7 × VCC VCC VIL Low level input voltage SIN, SCLK, LAT, BLANK GND 0.3 × VCC IOH High level output current SOUT IOL Low level output current SOUT OUTR0-OUTR7, OUTG0-OUTG7 V –1 mA 1 mA 35 mA 26.2 mA IOLC Constant output sink current TA Operating free-air temperature –40 +85 °C TJ Operating junction temperature –40 +125 °C OUTB0-OUTB7 AC CHARACTERISTICS, VCC = 3 V to 5.5 V fCLK (SCLK) Data shift clock frequency TWH0 SCLK 35 MHz SCLK 10 ns SCLK 10 ns LAT 15 ns TWH2 BLANK 15 ns TWL2 BLANK 15 ns TWL0 TWH1 TSU0 TSU1 TH0 TH1 Pulse duration Setup time Hold time SIN – SCLK↑ LAT↑ – SCLK↑ SIN – SCLK↑ LAT↑ – SCLK↑ 4 ns 150 ns 3 ns 10 ns Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 3 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V. TLC5952 PARAMETER TEST CONDITIONS VOH High level output voltage IOH = –1 mA at SOUT VOL Low level output voltage IOL = 1 mA at SOUT IIN Input current VI = VCC or GND at SIN, SCLK, LAT, and BLANK MIN TYP VCC – 0.4 –1 MAX UNIT VCC V 0.4 V 1 µA ICC1 SIN, SCLK, LAT = low, BLANK = high, VOUTRn/Gn/Bn = 1 V, BCR/G/B = 7Fh, RIREF = 24 kΩ (IOUTRn/Gn = 2 mA target, IOUTBn = 1.5 mA target) 1 3 mA ICC2 SIN, SCLK, LAT = low, BLANK = high, VOUTRn/Gn/Bn = 1 V, BCR/G/B = 7Fh, RIREF = 2.4 kΩ (IOUTRn/Gn = 20 mA target, IOUTBn = 15 mA target) 8 14 mA ICC3 SIN, SCLK, LAT = low, BLANK = low, all OUTRn/Gn/Bn = on, VOUTRn/Gn/Bn = 1 V, BCR/G/B = 7Fh, RIREF = 2.4 kΩ (IOUTRn/Gn = 20 mA target, IOUTBn = 15 mA target) 12 30 mA ICC4 SIN, SCLK, LAT = low, BLANK = low, all OUTRn/Gn/Bn = on, VOUTRn/Gn/Bn = 1 V, BCR/G/B = 7Fh, RIREF = 1.5 kΩ (IOUTRn/Gn = 32 mA target, IOUTBn = 24 mA target) 20 50 mA IOLC At OUTR0-OUTR7 and OUTG0-OUTG7, All OUTRn/Gn/Bn = on, BCR/G/B = 7Fh, VOUTRn/Gn/Bn = VOUTfix = 1 V, RIREF = 1.5 kΩ (IOUTRn/Gn = 32 mA target) 29 32 35 mA At OUTB0-OUTB7, All OUTRn/Gn/Bn = on, BCR/G/B = 7Fh, VOUTRn/Gn/Bn = VOUTfix = 1 V, RIREF = 1.5 kΩ (IOUTBn = 24 mA target) 21.8 24 26.2 mA 0.1 µA Supply current Constant output current IOLC1 IOLKG Leakage output current At OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7, BLANK = high, VOUTRn/Gn/Bn = VOUTfix = 15 V, RIREF = 1.5 kΩ ΔIOLC Constant-current error (1) (channel-to-channel in same color group) At OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7, All OUTRn/Gn/Bn = on, BCR/G/B = 7Fh, VOUTRn/Gn/Bn = VOUTfix = 1 V, RIREF = 1.5 kΩ (IOUTRn/Gn = 32 mA target, IOUTBn = 24 mA target), at same color group output ±1 ±3 % ΔIOLC1 Constant current error (2) (device to device in same color group) At OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7, All OUTRn/Gn/Bn = on, BCR/G/B = 7Fh, VOUTRn/Gn/Bn = VOUTfix = 1 V, RIREF = 1.5 kΩ (IOUTRn/Gn = 32 mA target, IOUTBn = 24 mA target), at same color group output ±3 ±6 % (1) The deviation of each output in the same color group from the average of the same color group (OUTR0-OUTR7, OUTG0-OUTG7, or OUTB0-OUTB7) constant current. The deviation is calculated by the formula (X = R, G, or B; n = 0-7): IOUTXn D (%) = -1 ´ 100 (IOUTX0 + IOUTX1 + ... + IOUTX6 + IOUTX7) 8 (2) The deviation of the constant-current average of each color group from the ideal constant-current value. The deviation is calculated by the formula (X = R, G, or B): (IOUTX0 + IOUTX1 +¼+IOUTX7) - (Ideal Output Current) 8 D (%) = ´ 100 Ideal Output Current Ideal current is calculated by the following equation for OUTR0-OUTR7 and OUTG0-OUTG7 (X = R, G, or B): IOUTRn/Gn(IDEAL, mA) = 40 ´ 1.20 RIREF (W) Ideal current is calculated by the following equation for OUTR0-OUTR7 and OUTG0-OUTG7 (X = R, G, or B): IOUTBn(IDEAL, mA) = 30 ´ 4 1.20 RIREF (W) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V. TLC5952 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±0.5 ±1 % ±1 ±3 %/V ΔIOLC2 Line regulation (3) At OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7, All OUTRn/Gn/Bn = on, BCR/G/B = 7Fh, VOUTRn/Gn/Bn = VOUTfix = 1 V, RIREF = 1.5 kΩ ΔIOLC3 Load regulation (4) At OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7, All OUTRn/Gn/Bn = on, BCR/G/B = 7Fh, VOUTRn/Gn/Bn = 1 V to 3 V, VOUTfix = 1 V, RIREF = 1.5 kΩ TTEF Thermal error flag threshold Junction temperature (5) +150 +165 +180 °C THYS Thermal error flag hysteresis Junction temperature (5) 5 10 20 °C All OUTRn/Gn/Bn = on, detection voltage select code = 0h 0.25 0.30 0.35 V All OUTRn/Gn/Bn = on, detection voltage select code = 1h 0.50 0.60 0.70 V All OUTRn/Gn/Bn = on, detection voltage select code = 2h 0.80 0.90 1.00 V VLOD3 All OUTRn/Gn/Bn = on, detection voltage select code = 3h 1.10 1.20 1.30 V VLSD0 All OUTRn/Gn/Bn = on, detection voltage select code = 4h 0.55 × VCC 0.60 × VCC 0.65 × VCC V All OUTRn/Gn/Bn = on, detection voltage select code = 5h 0.65 × VCC 0.70 × VCC 0.75 × VCC V All OUTRn/Gn/Bn = on, detection voltage select code = 6h 0.75 × VCC 0.80 × VCC 0.85 × VCC V All OUTRn/Gn/Bn = on, detection voltage select code = 7h 0.85 × VCC 0.90 × VCC 0.95 × VCC V 1.17 1.20 1.23 V VLOD0 VLOD1 VLOD2 VLSD1 VLSD2 LED open detection threshold LED short detection threshold VLSD3 VIREF (3) Reference voltage output RIREF = 1.5 kΩ Line regulation is calculated by the following equation (X = R, G, or B; n = 0-7): D (%/V) = (IOUTXn at VCC = 5.5 V) - (IOUTXn at VCC = 3.0 V) 100 ´ (IOUTXn at VCC = 3.0 V) (4) Load regulation is calculated by the following equation (X = R, G, or B; n = 0-7): D (%/V) = (IOUTXn at VOUTXn = 3 V) - (IOUTXn at VOUTXn = 1 V) 100 ´ (IOUTXn at VOUTXn = 1 V) (5) 5.5 V - 3 V 3V-1V Not tested; specified by design. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 5 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com SWITCHING CHARACTERISTICS At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 120 Ω, RIREF = 1.5 kΩ, and VLED = 5.0 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V. PARAMETER tR0 Rise time tR1 tF0 Fall time tF1 TEST CONDITIONS MIN SOUT OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7, BCR/G/B = 7Fh SOUT OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7, BCR/G/B = 7Fh TYP MAX UNIT 6 15 ns 10 30 ns 6 15 ns 10 30 ns 8 20 ns tD0 SCLK↑ to SOUT tD1 LAT↑ to OUTR0 on/off, BCR/G/B = 7Fh 22 45 ns tD2 BLANK↓↑ to OUTR0 on/off, BCR/G/B = 7Fh 15 30 ns tD3 OUTRn on to OUTGn on, OUTGn on to OUTBn on, OUTBn on to OUTRn + 1 on, BCR/G/B = 7Fh 3 6 ns tD4 OUTRn off to OUTGn off, OUTGn off to OUTBn off, OUTBn off to OUTRn + 1 off, BCR/G/B = 7Fh 3 6 ns tD5 LAT↑ to IOUTn changing by global brightness control (BC data are 0Ch-72h or 72h-0Ch) 20 50 ns 5 ns Propagation delay time (1) tON_ERR (1) (2) 6 Output on-time error (2) On/off latched data = '1', BCR/G/B = 7Fh, 20 ns BLANK low level one-shot pulse input –11 Propagation delay, tD3 (OUTRn on to OUTGn on, OUTGn on to OUTBn on, OUTBn on to OUTRn + 1 on ) is calculated by the formula: tD3 (ns) = (the propagation delay between OUTR0 to OUTB7 = on)/23 tD4 (OUTRn to OUTGn = off, OUTGn to OUTBn = off, OUTBn to OUTRn + 1 = off ) is calculated by the formula: tD4 (ns) = (the propagation delay between OUTR0 to OUTB7 = off)/23 Output on-time error is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low-level pulse width. tOUT_ON is the actual on-time of the constant current output. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 FUNCTIONAL BLOCK DIAGRAM 24-Bit LOD or 24-Bit LSD Data VCC VCC 1-Bit TEF Data LSB MSB SIN Common Shift Register 0 SOUT 24 Bit 24 SCLK 24 LSB MSB 24 Output On/Off Data Latch 0 23 24 LSB MSB Control Data Latch (Three Groups, 7-Bit Global Brightness Control LOD/LSD Voltage and Detection Type Select) LAT 0 24 23 3 LOD/LSD Holder BLANK 21 On/Off Control with Output Delay 24 TEF Holder Thermal Detector 7-Bit Global Brightness Control 7-Bit Global Brightness Control 7 IREF Reference Current Control 16 16 Channels Constant-Current Sink Driver ¼ GND Detection Voltage 7 ¼ 7-Bit Global Brightness Control 8 24 7 8 Channels Constant-Current Sink Driver ¼ LED Open Detection (LOD)/LED Short Detection (LSD) ¼ ¼ ¼ OUTR0 OUTR7 OUTG0 OUTG7 OUTB0 OUTB7 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 7 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com PIN CONFIGURATIONS DAP PACKAGE HTSSOP-32 PowerPAD (TOP VIEW) 8 OUTG2 OUTR2 OUTB1 OUTG1 OUTR1 OUTB0 OUTG0 OUTR0 32 31 30 29 28 27 26 25 RHB PACKAGE(1) 5 mm × 5 mm QFN-32 (TOP VIEW) GND 1 32 IREF SIN 2 31 VCC SCLK 3 30 SOUT LAT 4 29 BLANK OUTB2 1 24 LAT OUTR0 5 28 OUTB7 OUTR3 2 23 SCLK OUTG0 6 27 OUTG7 OUTG3 3 22 SIN OUTB0 7 26 OUTR7 OUTB3 4 21 GND OUTR1 8 25 OUTB6 OUTR4 5 20 IREF OUTG1 9 24 OUTG6 OUTG4 6 19 VCC OUTB1 10 23 OUTR6 OUTB4 7 18 SOUT OUTR2 11 22 OUTB5 OUTR5 8 17 BLANK OUTG2 12 21 OUTG5 OUTB2 13 20 OUTR5 OUTR3 14 19 OUTB4 OUTG3 15 18 OUTG4 OUTB3 16 17 OUTR4 9 10 11 12 13 14 15 16 OUTG5 OUTB5 OUTR6 OUTG6 OUTB6 OUTR7 OUTG7 OUTB7 Thermal Pad (Bottom Side) Thermal Pad (Bottom Side) (1) Product preview device. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 TERMINAL FUNCTIONS TERMINAL NO. NAME SIN DAP RHB (1) I/O 2 22 I Serial data input for the 25-bit common shift register DESCRIPTION SCLK 3 23 I Serial data shift clock. Data present on SIN are shifted to the LSB of the common shift register with the rising edge of SCLK. Data in the shift register are shifted toward the MSB at each rising edge of SCLK. The MSB data of the common shift register appear on SOUT. LAT 4 24 I Edge triggered latch. The rising edge of LAT latches the data from the common shift register into the output on/off data latch. See the Output On/Off Data Latch section for more details. BLANK 29 17 I All outputs are blank. When BLANK is high, all constant-current outputs (OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7) are forced off. When BLANK is low, all constant current outputs are controlled by the on/off control data in the data latch. IREF 32 20 I/O Reference current terminal. The maximum current for the outputs OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7 is set with a resistor from IREF to GND. SOUT 30 18 O Serial data output. The MSB of the 25-bit common shift register is shifted out at the rising edge of SCLK. OUTR0OUTR7 5, 8, 11, 14, 17, 20, 23, 26 2, 5, 8, 11, 14, 25, 28, 31 O Constant-current outputs for the RED LED group. Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. These outputs are turned on/off by the BLANK signal and the data in the output on/off control data latch. OUTG0OUTG7 6, 9, 12, 15, 18, 21, 24, 27 3, 6, 9, 12, 15, 26, 29, 32 O Constant-current outputs for the GREEN LED group. Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. These outputs are turned on/off by the BLANK signal and the data in the output on/off control data latch. OUTB0OUTB7 7, 10, 13, 16, 19, 22, 25, 28 1, 4, 7, 10, 13, 16, 27, 30 O Constant-current outputs for the BLUE LED group. Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. These outputs are turned on/off by the BLANK signal and the data in the output on/off control data latch. VCC 31 19 — Power-supply voltage GND 1 21 — Power ground (1) Product preview device. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 9 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC INPUT SOUT GND GND Figure 1. SIN, SCLK, LAT, BLANK Figure 2. SOUT OUTn GND Figure 3. OUTR0/G0/B0 Through OUTR7/G7/B7 TEST CIRCUITS RL VCC VCC OUTXn IREF RIREF VCC (2) (1) GND VLED SOUT VCC CL GND (1) CL includes measurement probe and jig capacitance. (1) CL (1) CL includes measurement probe and jig capacitance. (2) X = R, G, or B; n = 0-7. Figure 5. Rise Time and Fall Time Test Circuit for SOUT Figure 4. Rise Time and Fall Time Test Circuit for OUTRn/Gn/Bn IREF OUTXn (1) ¼ RIREF OUTR0 ¼ VCC VCC GND OUTB7 VOUTfix VOUTRn/Gn/Bn (1) X = R, G, or B; n = 0-7. Figure 6. Constant-Current Test Circuit for OUTRn/Gn/Bn 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 TIMING DIAGRAMS TWH0, TWL0, TWH1, TWH2, TWL2: VCC INPUT 50% GND TWH TWL TSU0, TSU1, TH0, TH1: VCC CLOCK (1) INPUT 50% GND TSU TH VCC DATA/CONTROL (1) INPUT 50% GND (1) Input pulse rise and fall time is 1 ns to 3 ns. Figure 7. Input Timing tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5: VCC INPUT (1) 50% GND tD VOH or VOUTRn/Gn/BnH 90% OUTPUT 50% 10% VOL or VOUTRn/Gn/BnL tR or tF (1) Input pulse rise and fall time is 1 ns to 3 ns. Figure 8. Output Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 11 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com TIMING DIAGRAMS (continued) Output On/Off Data Write SIN 0A On Low B7B On R7B On G7B On Control Data Write B6B On R6B On G6B On B0B On R0B On G0B On High 23 Cont 22 Cont 1 2 3 21 Cont 1 Cont 2 Cont 0 Cont fCLK (SCLK) TSU0 TH0 TWH0 TSU1 SCLK 1 2 3 4 5 6 23 24 25 TWL0 TH1 23 24 25 TWH1 LAT TWL2 TWH2 BLANK LOD G0A Common Shift Register Bit 23 (Internal) LOD B7A B7B On G7B On R7B On B6B On G6B On B0B On G0B On R0B On LOD R0B High 23 Cont 22 Cont 2 Cont 1 Cont 0 Cont Low B7B On G7B On R7B On B6B On R1B On B0B On G0B On LOD G0B LOD R0B High 23 Cont 3 Cont 2 Cont 1 Cont LOD R7A LOD B6A LOD G6A LOD R6A LOD B5A LOD R0A Low B7B On LOD B7B LOD G7B LOD R7B LOD B6B LOD G0B LOD R0B 23 Cont ¼ LOD G7A ¼ Common Shift Register Bit 1 (Internal) Low ¼ LOD R0A ¼ Common Shift Register Bit 0 (Internal) On/Off Data Latch (Internal) Previous Data Control Data Latch (Internal) Current Data Previous Data Current Data tD0 SOUT (Common Shift Register Bit 24) TEF A tR0/tF0 LOD G7A LOD B7A LOD R7A tD2 OUTR0 OUTG0 (VOUTRn/Gn/BnH) tF1 ON (VOUTRn/Gn/BnL) LOD G0A LOD R0A Low TEF B LOD B7B LOD G7B LOD R7B LOD G0B LOD R0B tD1 High tD5 tR1 RED outputs are turned off by output on/off data. tD4 tD3 Output current is changed by BC data. tD3 tD4 ON OFF OUTR1 LOD R6A ON OFF OUTB0 LOD G6A tD2 OFF OFF LOD B6A tD4 tD3 ON ¼ ¼ ¼ ¼ OFF OUTR7 ON OFF OUTG7 ON OFF OUTB7 ON Figure 9. Timing Diagram 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 TYPICAL CHARACTERISTICS At TA = +25°C and VCC = 3.3 V, unless otherwise noted. REFERENCE RESISTOR vs OUTPUT CURRENT (RED and GREEN Color Group) REFERENCE RESISTOR vs OUTPUT CURRENT (BLUE Color Group) 100 RIREF, Reference Resistor (kW) RIREF, Reference Resistor (kW) 100 24000 9600 10 4800 3200 2400 1920 24000 18000 10 3600 2400 0 5 10 15 25 20 1440 1 0 35 30 5 Output Current (mA) 30 POWER DISSIPATION RATE OUTPUT CURRENT vs OUTPUT VOLTAGE (RED and GREEN Color Group) 40 5000 TA = +25°C, VCC = 3.3 V, BCR/G = 7Fh 35 Output Current (mA) Power Dissipation Rate (mW) 25 20 Figure 11. TLC5952RHB 3000 TLC5952DAP PowerPAD Not Soldered 1000 35 IO = 35 mA IO = 30 mA 30 25 IO = 20 mA 20 15 IO = 10 mA 10 IO = 2 mA IO = 5 mA 5 0 0 -40 -20 0 20 40 60 0 100 80 0.5 40 2.5 OUTPUT CURRENT vs OUTPUT VOLTAGE (BLUE Color Group) OUTPUT CURRENT vs OUTPUT VOLTAGE (RED and GREEN Color Group) 40 IO = 26.2 mA 20 IO = 22.5 mA 15 IO = 15 mA IO = 7.5 mA IO = 3.75 mA IO = 1.5 mA 3.0 IO = 35 mA TA = +25°C, VCC = 5 V, BCR/G = 7Fh 35 25 10 2.0 Figure 13. 5 Output Current (mA) 30 1.5 Figure 12. TA = +25°C VCC = 3.3 V BCB = 7Fh 35 1.0 Output Voltage (V) Free-Air Temperature (°C) Output Current (mA) 15 Output Current (mA) TLC5952DAP PowerPAD Soldered 2000 10 Figure 10. 6000 4000 1374 1800 1600 1371 1 7200 IO = 30 mA 30 25 IO = 20 mA 20 15 IO = 10 mA 10 IO = 2 mA IO = 5 mA 5 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 Output Voltage (V) Output Voltage (V) Figure 14. Figure 15. 2.5 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 3.0 13 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VCC = 3.3 V, unless otherwise noted. OUTPUT CURRENT vs OUTPUT VOLTAGE (BLUE Color Group) 40 40 TA = +25°C VCC = 5 V BCB = 7Fh 30 IO = 26.2 mA 25 20 IO = 22.5 mA IO = 15 mA 15 10 IO = 7.5 mA IO = 3.75 mA IO = 1.5 mA IOLCMax = 35 mA VCC = 3.3 V BCR/G = 7Fh 39 38 Output Current (mA) 35 Output Current (mA) OUTPUT CURRENT vs OUTPUT VOLTAGE (RED and GREEN Color Group) 37 36 35 34 33 TA = -40°C TA = +25°C TA = +85°C 32 5 31 0 30 0 31 1.0 1.5 2.0 2.5 0 3.0 2.5 Figure 17. OUTPUT CURRENT vs OUTPUT VOLTAGE (BLUE Color Group) OUTPUT CURRENT vs OUTPUT VOLTAGE (RED and GREEN Color Group) 40 38 28 27 26 25 24 TA = -40°C TA = +25°C TA = +85°C 37 36 35 34 33 TA = -40°C TA = +25°C TA = +85°C 32 31 21 3.0 IOLCMax = 35 mA VCC = 5 V BCR/G = 7Fh 39 22 30 0 31 0.5 1.0 1.5 2.0 2.5 0 3.0 29 0.5 1.0 1.5 2.0 2.5 3.0 Output Voltage (V) Output Voltage (V) Figure 18. Figure 19. OUTPUT CURRENT vs OUTPUT VOLTAGE (BLUE Color Group) CONSTANT-CURRENT ERROR vs OUTPUT CURRENT (Channel-to-Channel in RED Color Group) 4 IOLCMax = 26.2 mA VCC = 5 V BCB = 7Fh 30 TA = +25°C BCR = 7Fh 3 2 28 27 DIOLC (%) Output Current (mA) 2.0 Figure 16. 23 26 25 24 22 1 0 -1 -2 TA = -40°C TA = +25°C TA = +85°C 23 VCC = 3.3 V -3 VCC = 5 V -4 21 0 14 1.5 Output Voltage (V) Output Current (mA) 29 1.0 0.5 Output Voltage (V) IOLCMax = 26.2 mA VCC = 3.3 V BCB = 7Fh 30 Output Current (mA) 0.5 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 Output Voltage (V) Output Current (mA) Figure 20. Figure 21. Submit Documentation Feedback 25 30 35 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VCC = 3.3 V, unless otherwise noted. CONSTANT-CURRENT ERROR vs OUTPUT CURRENT (Channel-to-Channel in GREEN Color Group) CONSTANT-CURRENT ERROR vs OUTPUT CURRENT (Channel-to-Channel in BLUE Color Group) 4 4 TA = +25°C BCG = 7Fh 2 2 1 1 0 -1 -2 10 15 20 25 0 35 30 10 5 15 20 Figure 22. Figure 23. CONSTANT-CURRENT ERROR vs AMBIENT TEMPERATURE (Channel-to-Channel in RED Color Group) CONSTANT-CURRENT ERROR vs AMBIENT TEMPERATURE (Channel-to-Channel in GREEN Color Group) 4 IOLCMax = 35 mA BCR = 7Fh IOLCMax = 35 mA BCG = 7Fh 3 1 1 0 -1 -2 30 25 Output Current (mA) 2 0 -1 -2 VCC = 3.3 V -3 VCC = 3.3 V -3 VCC = 5 V -4 VCC = 5 V -4 -40 3 VCC = 5 V Output Current (mA) DIOLC (%) DIOLC (%) 5 2 4 VCC = 3.3 V -4 0 -20 0 20 40 60 80 100 -40 0 -20 20 40 60 80 100 Ambient Temperature (°C) Ambient Temperature (°C) Figure 24. Figure 25. CONSTANT-CURRENT ERROR vs AMBIENT TEMPERATURE (Channel-to-Channel in BLUE Color Group) GLOBAL BRIGHTNESS CONTROL LINEARITY (RED and GREEN Color Group) 40 IOLCMax = 26.2 mA BCB = 7Fh IO = 35 mA (R = 1.37 kW) TA = +25°C 35 Output Current (mA) 2 DIOLC (%) -1 -3 VCC = 5 V -4 3 0 -2 VCC = 3.3 V -3 4 TA = +25°C BCB = 7Fh 3 DIOLC (%) DIOLC (%) 3 1 0 -1 -2 VCC = 3.3 V -3 VCC = 5 V -4 VCC = 3.3 V 30 VCC = 5 V IO = 20 mA (R = 2.4 kW) 25 20 IO = 10 mA (R = 4.8 kW) 15 10 5 IO = 2 mA, (R = 24 kW) 0 -40 -20 0 20 40 60 80 100 0 16 32 48 64 80 96 Ambient Temperature (°C) Brightness Control Data (dec) Figure 26. Figure 27. 112 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 128 15 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C and VCC = 3.3 V, unless otherwise noted. GLOBAL BRIGHTNESS CONTROL LINEARITY (BLUE Color Group) 30 TA = +25°C IO = 26.6 mA (R = 1.371 kW) Output Current (mA) 35 VCC = 3.3 V 30 VCC = 5 V IO = 15 mA (R = 2.4 kW) 25 20 IO = 7.5 mA (R = 4.8 kW) 20 15 15 10 IO = 1.5 mA (R = 24 kW) 10 5 5 VCC = 5 V 0 32 16 48 64 96 80 112 128 0 20 25 SUPPLY CURRENT vs AMBIENT TEMPERATURE 35 30 R = 1.37 kW, IO (Rn/Gn) = 35 mA IO (Bn) = 26.2 mA VCC = 3.3 V VCC = 5 V 25 10 20 R = 2.4 kW, IO (Rn/Gn) = 20 mA, IO (Bn) = 15 mA 15 10 5 VCC = 3.3 V SIN = 17.5 MHz, SCLK = 35 MHz, BCR/G/B = 7Fh, All Group Output = On 5 VCC = 5 V 0 R = 24 kW, IO (Rn/Gn) = 2 mA, IO (Bn) = 1.5 mA 0 10 35 30 Figure 29. 15 5 15 Figure 28. TA = +25°C SIN = 17.5 MHz SCLK = 35 MHz BCR/G/B = 7Fh All Group Output = On 0 10 OUTRn/Gn Output Current (mA) ICC (mA) ICC (mA) 20 5 Brightness Control Data (dec) SUPPLY CURRENT vs OUTPUT CURRENT (BLUE Color Group) 25 VCC = 3.3 V 0 0 30 TA = +25°C SIN = 17.5 MHz SCLK = 35 MHz BCR/G/B = 7Fh All Group Output = On 25 ICC (mA) 40 SUPPLY CURRENT vs OUTPUT CURRENT (RED and GREEN Color Group) 15 20 25 30 -40 -20 0 20 40 60 OUTBn Output Current (mA) Ambient Temperature (°C) Figure 30. Figure 31. 80 100 CONSTANT-CURRENT OUTPUT VOLTAGE WAVEFORM CH1 (2 V/div) CH2 (2 V/div) CH3 (2 V/div) CH1-BLANK (15 ns) CH2-OUTR0 (BLANK = 15 ns) IOLCMax (R) = 32 mA IOLCMAX (B) = 24 mA RIREF = 1.5 kW, TA = +25°C RL = 120 W, CL = 15 pF VCC = 3.3 V, VLED = 5 V CH3-OUTB0 (BLANK = 15 ns) Time (12.5 ns/div) Figure 32. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 DETAILED DESCRIPTION MAXIMUM CONSTANT SINK CURRENT VALUE The maximum output current per channel, IOLCMax, is programmed by a single resistor, RIREF, which is placed between the IREF and GND pins. The voltage on IREF is set by an internal band-gap VIREF, with a typical value of 1.20 V. The maximum channel current is equivalent to the current flowing through RIREF multiplied by a factor of 40 for OUTRn/Gn and 30 for OUTBn. The maximum output current per channel can be calculated by Equation 1. RIREF (kW) = = VIREF (V) ´ 40 (for OUTRn/Gn) IOLCMax (mA) VIREF (V) ´ 30 (for OUTBn) IOLCMax (mA) (1) Where: VIREF = the internal reference voltage on IREF (1.20 V, typical) IOLCMax = 2 mA to 35 mA at OUTRn/Gn and 1.5 mA to 26.2 mA at OUTBn IOLCMax is the largest current for each output. Each output sinks the IOLCMax current when it is turned on and the global brightness control data are set to the maximum value of 7Fh (127d). Each output sink current can be reduced by lowering the output global brightness control (BC) value. RIREF must be between 1.37 kΩ and 24 kΩ to hold IOLCMax between 35 mA (typ) and 2 mA (typ) for OUTRn/Gn and between 26.2 mA (typ) and 1.5 mA (typ) for OUTBn. Otherwise, the output may be unstable. Output currents lower than 2 mA (or 1.5 mA for OUTBn) can be achieved by setting IOLCMax to 2 mA or higher and then using global brightness control to lower the output current. Table 1 shows the characteristics of the constant-current sink versus the external resistor, RIREF. Table 1. Maximum Constant Current Output versus External Resistor Value IOLCMax (mA) OUTRn, OUTGn OUTBn RIREF (kΩ) 35 26.28 1.37 30 22.5 1.6 25 18.75 1.92 20 15 2.4 15 11.25 3.2 10 7.5 4.8 5 3.75 9.6 2 1.5 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 17 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION: SINK CURRENT CONTROL The TLC5952 is able to adjust the output current of each of the three color groups OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7. This function is called global brightness control (BC). The BC function allows users to adjust the global brightness of LEDs connected to the three output groups (OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7). All color group output currents can be adjusted in 128 steps from 0% to 100% of the maximum output current, IOLCMax. The brightness control data are entered into the TLC5952 via the serial interface. When the BC data change, the output current also changes immediately. When the IC is powered on, the data in the common shift register and the control data latch are not set to any default values. Therefore, BC data must be written to the control data latch before turning on the constant-current output. Equation 2 determines the output sink current for each color group. Table 2 summarizes the BC data versus current ratio and set current value. IOUT (mA) = IOLCMax (mA) ´ BCR/G/B 127d (2) Where: IOLCMax = the maximum channel current for each channel determined by RIREF BCR/G/B = the global brightness control value in the control data latch for each output color group Table 2. BC Data versus Current Ratio and Set Current Value BC DATA (Binary) BC DATA (Decimal) BC DATA (Hex) RATIO OF OUTPUT CURRENT TO IOLCMax (mA, Typical) 000 0000 0 00 0 0 0 000 0001 1 01 0.8 0.28 0.02 000 0010 2 02 1.6 0.55 0.03 — — — — — — 111 1101 125 7D 98.4 34.45 1.97 111 1110 126 7E 99.2 34.72 1.98 111 1111 127 7F 100.0 35.00 2.00 IOUT, mA (IOLCMax = 35 mA, Typical) IOUT, mA (IOLCMax = 2 mA, Typical) CONSTANT-CURRENT OUTPUT ON/OFF CONTROL When BLANK is low, each output is controlled by the data in the output on/off data latch. When data corresponding to an output are equal to '1', the output turns on; when the data corresponding to an output are equal to '0', the output turns off. When BLANK is high, all outputs are forced off. When the IC is powered on, the data in the output on/off data latch are not set to any default values. Therefore, on/off data must be written to the output on/off data latch before turning on the constant-current output and pulling BLANK low. If there are any OUTRn/Bn/Bn outputs not connected to an LED, including open for short-to-ground failures, the on/off data corresponding to the unconnected output should be set to '0' before the LED is turned on. Otherwise, the VCC supply current (ICC) increases while the LEDs are on. A truth table for the on/off control data is shown in Table 3. Table 3. On/Off Control Data Truth Table 18 ON/OFF CONTROL DATA CONSTANT-CURRENT OUTPUT STATUS 0 Off 1 On Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 REGISTER AND DATA LATCH CONFIGURATION The TLC5952 has two writable data latches: the output on/off data latch and the control data latch. Both data latches are 24 bits in length. If the common shift register MSB is '0', the least significant 24 bits of data from the 25-bit common shift register are latched into the output on/off data latch. If the MSB is '1', the data are latched into the control data latch. Figure 33 shows the common shift register and the control data latch configuration. Common Shift Register (25 Bits) MSB 24 SOUT Latch Select Bit 23 22 21 20 19 Common Common Common Common Common Data Data Data Data Data Bit 23 Bit 19 Bit 22 Bit 20 Bit 21 4 5 ¼ 3 2 1 Common Common Common Common Common Data Data Data Data Data Bit 5 Bit 2 Bit 4 Bit 1 Bit 3 LSB 0 Common Data Bit 0 SIN SCK 24 24 Output On/Off Data Latch (24 Bits) MSB 23 22 21 20 19 OUTB7 On OUTG7 On OUTR7 On OUTB6 On OUTG6 On ¼ 5 4 3 2 1 LSB 0 OUTB1 On OUTG1 On OUTR1 On OUTB0 On OUTG0 On OUTR0 On 7 6 The latch pulse comes from LAT when the MSB of the common shift register is ‘0’. 24 To Output On/Off Control Circuit 24 Control Data Latch (24 Bits) MSB 23 22 21 Detection Detection Detection OUTB0-7 Voltage Voltage Voltage Bright Select 2 Select 1 Select 0 Bit 6 3 To LSD/LOD Circuit 14 20 ¼ 13 OUTB0-7 OUTG0-7 Bright Bright Bit 0 Bit 6 7 To Global Brightness Control Circuit for OUTB0-OUTB7 ¼ LSB 0 OUTG0-7 OUTR0-7 Bright Bright Bit 6 Bit 0 7 To Global Brightness Control Circuit for OUTG0-OUTG7 ¼ OUTR0-7 Bright Bit 0 The latch pulse comes from LAT when the MSB of the common shift register is ‘1’. 7 To Global Brightness Control Circuit for OUTR0-OUTR7 Figure 33. Grayscale Shift Register and Data Latch Configuration Output On/Off Data Latch The output on/off data latch is 24 bits long. This latch is used to turn each output current sink (OUTRn/Gn/Bn) on or off. When the MSB of the common shift register is set to '0', the lower 24 bits are written to the output on/off data latch on the rising edge of LAT. If the output on/off data latch bit corresponding to an output is '0', the output is turned off; if the bit is a '1', the output is turned on. When the IC is powered on, the data in the output on/off data latch are not set to any default value. Therefore, the on/off control data should be written to the data latch before the constant-current outputs are turned on. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 19 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com Control Data Latch The control data latch is 24 bits long and is used to adjust the LED current for each color group (OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7). The LED current for each group can be adjusted between 0% and 100% of IOLCMAX in 128 steps (7-bit resolution). This data latch is also used to select the error detection type, LED open detection (LOD) or LED short detection (LSD), and the threshold voltage. When the MSB of the common shift register is set to '1', the lower 24 bits are written to the control data latch on the rising edge of LAT. Table 4 shows the control data latch bit assignment. When the IC is powered on, the data in the control data latch are not set to a default value. Therefore, the control data latch data should be written to the latch before the constant-current outputs are turned on. Table 4. Data Bit Assignment BITS 20 DESCRIPTION 6-0 Global brightness control data for RED group (OUTR0-OUTR7, data = 00h to 7Fh) 13-7 Global brightness control data for GREEN group (OUTG0-OUTG7, data = 00h to 7Fh) 20-14 Global brightness control data for BLUE group (OUTB0-OUTB7, data = 00h to 7Fh) 23-21 Detection voltage and type select (data = 0h to 7h) 0 = LED open detection with 0.3 V (typ) threshold 1 = LED open detection with 0.6 V (typ) threshold 2 = LED open detection with 0.9 V (typ) threshold 3 = LED open detection with 1.2 V (typ) threshold 4 = LED short detection with VCC × 60% (typ) threshold 5 = LED short detection with VCC × 70% (typ) threshold 6 = LED short detection with VCC × 80% (typ) threshold 7 = LED short detection with VCC × 90% (typ) threshold Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 Figure 34 shows the operation to write data into the common shift register and control data latch. Output On/Off Data Write SIN 0A On Low B7B On G7B On 1 2 3 R7B On Control Data Write B6B On G6B On 5 6 R6B On B0B On R0B On G0B On High 23 Cont 22 Cont 1 2 3 21 Cont 1 Cont 2 Cont 0 Cont SCLK 4 23 24 25 23 24 25 LAT The data in the common shift register are copied to the on/off data latch at the rising edge of LAT. BLANK LOD G0A Common Shift Register Bit 23 (Internal) LOD B7A B7B On G7B On R7B On B6B On G6B On B0B On G0B On R0B On LOD R0B High 23 Cont 22 Cont 2 Cont 1 Cont 0 Cont Low B7B On G7B On R7B On B6B On R1B On B0B On G0B On LOD G0B LOD R0B High 23 Cont 3 Cont 2 Cont 1 Cont LOD R7A LOD B6A LOD G6A LOD R6A LOD B5A LOD R0A Low B7B On LOD B7B LOD G7B LOD R7B LOD B6B LOD G0B LOD R0B 23 Cont ¼ LOD G7A ¼ Common Shift Register Bit 1 (Internal) Low ¼ LOD R0A ¼ Common Shift Register Bit 0 (Internal) On/Off Data Latch (Internal) Previous Data Control Data Latch (Internal) Previous Data SOUT (Common Shift Register Bit 24) TEF A LOD B7A LOD G7A LOD R7A LOD B6A LOD G6A LOD R6A LOD G0A LOD R0A Current Data Current Data TEF B Low OFF (VOUTRn/Gn/BnH) ON (VOUTRn/Gn/BnL) LOD B7B LOD G7B LOD R7B LOD G0B LOD R0B RED outputs are turned off by the output on/off data. Output current is changed by BC data. OFF OUTG0 High SID data are copied to the 25-bit common shift register at the rising edge of LAT. The LOD/LSD result of each LED comes from SOUT. OUTR0 The data in the common shift register are copied to the control data latch at the rising edge of LAT. ON OFF OUTB0 ON OFF OUTR1 ON ¼ ¼ ¼ ¼ OFF OUTR7 ON OFF OUTG7 ON OFF OUTB7 ON Figure 34. Data Write Operation Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 21 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com STATUS INFORMATION DATA (SID) The 25-bit word status information data (SID) contains the status of the LED open detection (LOD) or LED short detection (LSD), and thermal error flag (TEF). When the MSB of the common shift register is set to '0', the SID overwrites the common shift register data at the rising edge of LAT after the data in the common shift register are copied to the output on/off data latch. If the common shift register MSB is '1', the SID data are not copied to the common shift register. After being copied into the common shift register, new SID data are not available until new data are written into the common shift register. If new data are not written, the LAT signal is ignored. To recheck SID data without changing the constant-current output on/off data, reprogram the common shift register with the same data that are currently programmed into the output on/off data latch. When LAT goes high, the output on/off data do not change, but new SID data are loaded into the common shift register. LOD, LSD, and TEF are shifted out of SOUT with each rising edge of SCLK. LOD/LSD Holder (24 Bits) and TEF Holder (1 Bit) Thermal Error Flag LOD or LSD for OUTB7 LOD or LSD for OUTG7 LOD or LSD for OUTR7 LOD or LSD for OUTB6 LOD or LSD for OUTG6 ¼ LOD or LSD for OUTB1 LOD or LSD for OUTG1 LOD or LSD for OUTR1 LOD or LSD for OUTB0 LOD or LSD for OUTG0 LOD or LSD for OUTR0 SID are loaded to the common shift register at the rising edge of LAT when the common shift register MSB is ‘0’. SIN SOUT Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 ¼ Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCK MSB LSB Common Shift Register (25 Bits) Figure 35. SID Load Assignment LED OPEN DETECTION (LOD), LED SHORT DETECTION (LSD), AND THERMAL ERROR FLAG (TEF) LOD detects a fault caused by an LED open circuit or a short from OUTRn/Gn/Bn to ground by comparing the OUTRn/Gn/Bn voltage to the LOD detection threshold voltage level set in the control data latch (Table 4). If the OUTRn/Gn/Bn voltage is lower than the programmed voltage, that output LOD bit is set to '1' to indicate an open LED. Otherwise, the LOD bit is set to '0'. LOD data are only valid for outputs programmed to be on. LOD data for outputs programmed to be off are always '0'. LSD data detects a fault caused by a shorted LED by comparing the OUTRn/Gn/Bn voltage to the LSD detection threshold voltage level set in the control data latch (Table 4). If the OUTRn/Gn/Bn voltage is higher than the programmed voltage, that output LOD bit is set to '1' to indicate a shorted LED. Otherwise, the LSD bit is set to '0'. LSD data are only valid for outputs programmed to be on. LSD data for outputs programmed to be off are always '0'. LOD/LSD data are not valid until 1 µs after the falling edge of BLANK. Therefore, BLANK must be low for at least 1 µs before going high. At the rising edge of BLANK, the LOD/LSD detection data are latched in the LOD/LSD holder. Changes in the LOD/LSD data while BLANK is low are directly connected to the output of the LOD/LSD holder, but are only valid 1 µs after the change. The rising edge of LAT transfers the output data of the LOD/LSD holder to the common shift register. 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 As shown in Table 5, LOD and LSD data cannot be checked simultaneously. LOD/LSD data are not valid when TEF is active because all outputs are forced off. The TEF bit indicates that the IC junction temperature exceeds the temperature threshold (TTEF = +165°C, typ). The TEF bit also indicates that the IC has turned off all drivers to avoid overheating. The IC automatically turns the drivers back on when the IC temperature decreases to less than TTEF – THYS. The TEF data are held in the TEF holder latch until the TEF data are loaded into the common shift register by the rising edge of LAT. If the IC temperature falls below TTEF – THYS when LAT goes high, the TEF data in the TEF holder become '0'. If the IC temperature is not below TTEF – THYS when LAT goes high, then the TEF data remain '1'. Table 5 shows a truth table for LOD/LSD and TEF. Figure 36 to Figure 39 show different examples of LOD/LSD/TEF operation. Table 5. LOD/LSD/TEF Truth Table CONDITION LED OPEN DETECTION (LOD, Voltage Select Data = 0h to 3h) LED SHORT DETECTION (LSD, Voltage Select Data = 4h to 7h) THERMAL ERROR FLAG (TEF) 0 LED is not open or the output is off (VOUTRn/Gn/Bn is greater than the voltage selected by the detection voltage select bit in the control data latch) LED is not shorted or the output is off (VOUTRn/Gn/Bn is less than or equal to the voltage selected by the detection voltage select bit in the control data latch) Junction temperature is lower than the detect temperature (TTEF) before TEF is undetected or the detect temperature (TTEF – THYS) after TEF is detected 1 LED is open or shorted to GND (VOUTRn/Gn/Bn is less than or equal to the voltage selected by the detection voltage select bit in the control data latch) LED terminal is short or OUTn is short to higher voltage (VOUTn is greater than The selected voltage by detection voltage select bit in the control data latch) Junction temperature is higher than the detect temperature (TTEF) SID DATA THERMAL SHUTDOWN (TSD) The thermal shutdown (TSD) function turns off all constant-current outputs when the IC junction temperature (TJ) exceeds the temperature threshold (TTEF = +165°C, typ). The outputs remain disabled as long as the over-temperature condition exists. The outputs are turned on again after the IC junction temperature drops below (TTEF – THYS). NOISE REDUCTION Large surge currents may flow through the IC and the board on which the device is mounted if all 24 LED channels turn on simultaneously when BLANK goes low. These large current surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5952 turns the LED channels on in a series delay to provide a circuit soft-start feature. A small delay circuit is implemented between each output. When all bits of the on/off data latch are set to '1', each constant-current output turns on in order (OUTR0, OUTG0, OUTB0, OUTR1, OUTG1, OUTB1, OUTR2-OUTB6, OUTR7, OUTG7, and OUTB7) with a small delay between each output after BLANK goes low or LAT goes high; see Figure 34. Both turn-on and turn-off are delayed. CAPACITOR SELECTION Connect at least one 10-nF ceramic capacitor as close as possible between the VCC pin and ground. Additional capacitors are needed on the LED power supply to reduce ripple on the LED power supply to a minimum. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 23 TLC5952 SBVS129 – MAY 2009........................................................................................................................................................................................................ www.ti.com 0A On SIN 22B On 23B On Low 21B On 20B On 3B On 2B On 1B On 0B On Low 23C On 22C On 21C On 20C On 1 2 3 4 5 18C On 19C On 17C On 16C On SCLK 1 2 3 4 5 22 23 24 25 6 7 The data in the common shift register are copied to the control data latch at the rising edge of LAT. SID data (LOD or LSD and TEF) are loaded into the common shift register at the same time. LAT BLANK SOUT (Common Shift Register) (Bit 24) TEF A LOD B7A LOD G7A LOD B6A LOD R7A LOD G6A LOD B0A LOD R1A LOD R0A LOD G0A TEF B Low (LSD Voltage) LOD B6B LOD R7B LOD G6B LOD R6B LOD B5B LOD G5B SID data are copied to the 25-bit common shift register at the rising edge of LAT with the common shift register MSB low. OFF OUTXn LOD G7B LOD B7B ON ON (LOD Voltage) 0V LOD/LSD Data For OUTXn (Internal) '0' '0' Figure 36. LOD/LSD/TEF Operation (No LED Error) SIN 0A On 23B On Low 22B On 21B On 20B On 3B On 2B On 1B On 0B On Low 23C On 22C On 21C On 20C On 1 2 3 4 5 19C On 18C On 17C On 16C On SCLK 1 2 3 4 5 22 23 24 25 6 7 The data in the common shift register are copied to the control data latch at the rising edge of LAT. SID data (LOD or LSD and TEF) are loaded into the common shift register at the same time. LAT BLANK SOUT (Common Shift Register) (Bit 24) TEF A LOD G7A LOD B7A LOD R7A LOD B6A LOD G6A LOD R1A LOD B0A LOD G0A LOD R0A TEF B Low LOD B7B LOD G7B LOD R7B LOD B6B LOD G6B LOD R6B LOD B5B LOD G5B SID data are copied to the 25-bit common shift register at the rising edge of LAT with the common shift register MSB low. OFF (LSD Voltage) OUTXn ON (LOD Voltage) ON 0V LED is Open At This Time LOD Circuit Output For OUTXn (Internal) '1' (LED is Open) '1' (LED is Open) '0' (LED is Not Open) LOD output becomes '0' when the output is off. '1' (LED is Open) '1' (LED is Open) LOD Data In LOD/LSD Holder (Internal) LOD data are immediately updated with the LOD circuit output when BLANK is low. LOD data are not updated while BLANK is high. Therefore, LOD data in previous display periods can be read even if BLANK is high. Figure 37. LOD/LSD/TEF Operation (LED Open Error) 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 0A On SIN 22B On 23B On Low 21B On 20B On 3B On 2B On 1B On 0B On Low 23C On 22C On 21C On 20C On 1 2 3 4 5 18C On 19C On 17C On 16C On SCLK 1 2 3 4 5 22 23 24 25 6 7 The data in the common shift register are copied to the control data latch at the rising edge of LAT. SID data (LOD or LSD and TEF) are loaded into the common shift register at the same time. LAT BLANK SOUT (Common Shift Register) (Bit 24) TEF A LOD B7A LOD G7A LOD B6A LOD R7A LOD G6A LOD B0A LOD R1A LOD R0A LOD G0A TEF B Low LOD G7B LOD B7B LOD B6B LOD R7B LOD G6B LOD R6B LOD B5B LOD G5B SID data are copied to the 25-bit common shift register at the rising edge of LAT with the common shift register MSB low. OFF OUTXn ON (LSD Voltage) ON 0V LED is Shorted At This Time '1' (LED is Shorted) '1' (LED is Shorted) LSD Circuit Output For OUTXn (Internal) '0' (LED is Not Shorted) LSD output becomes '0' when the output is off. '1' (LED is Shorted) '1' (LED is Shorted) LSD Data In LOD/LSD Holder (Internal) LSD data are immediately updated with the LSD circuit output when BLANK is low. LSD data are not updated while BLANK is high. Therefore, LSD data in previous display periods can be read even if BLANK is high. Figure 38. LOD/LSD/TEF Operation (LED Short Error) SIN 0A On Low 23B On 22B On 21B On 20B On 3B On 2B On 1B On 0B On Low 23C On 22C On 21C On 20C On 1 2 3 4 5 19C On 18C On 17C On 16C On SCLK 1 2 3 4 5 22 23 24 25 6 7 The data in the common shift register are copied to the control data latch at the rising edge of LAT. SID data (LOD or LSD and TEF) are loaded into the common shift register at the same time. LAT BLANK SOUT (Common Shift Register) (Bit 24) TEF A LOD B7A LOD G7A LOD R7A LOD B6A LOD G6A LOD R1A LOD B0A LOD G0A LOD R0A Low TEF B LOD B7B LOD G7B LOD R7B LOD B6B LOD G6B LOD R6B LOD B5B LOD G5B SID data are copied to the 25-bit common shift register at the rising edge of LAT with the common shift register MSB low. '1' (Temperature is Higher Than TTEF) Thermal Detector Output (Internal) '0' (Temperature is Normal) TEF Data In TEF Holder (Internal) '0' (Temperature is Normal) '1' (Temperature is Higher Than TTEF) The output becomes '0' because the temperature drops below TTEF - THYS when the output is off. '1' (Temperature is Higher Than TTEF) TEF data are immediately updated when BLANK is low. '1' (Temperature is Higher Than TTEF) TEF data are set to '1' when the junction temperature exceeds TTEF. The TEF data are held in the TEF holder until the SID data are loaded into the common shift register. The TEF data are reset to '0' at the rising edge of LAT if the junction temperature is below TTEF - THYS. Figure 39. LOD/LSD/TEF Operation (Thermal Error) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC5952 25 PACKAGE OPTION ADDENDUM www.ti.com 15-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5952DAP ACTIVE HTSSOP DAP 32 TLC5952DAPR ACTIVE HTSSOP DAP 32 46 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC5952DAPR Package Package Pins Type Drawing SPQ HTSSOP 2000 DAP 32 Reel Reel Diameter Width (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 11.5 1.6 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5952DAPR HTSSOP DAP 32 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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