ETC NT3980

NT3980
TFT LCD Source Driver
Features
n Output: 384 output channels
n 8-bit resolution /256 gray scales
n Dot inversion with polarity control
n V1 ~ V10 for adjusting Gamma correction
n Power for analog circuit: 7 ~ 10V
n Output dynamic range: 0.1V ~ AVDD-0.1
n Power consumption of analog circuit: 6mA
n Operating frequency: 70MHz(Vcc:3.0V~3.6V)
45MHz(Vcc:2.5V~3.0V)
n Output deviation: ±2mv
n Data inversion for reducing EMI
n Cascade function with bi-direction shift control
n CMOS silicon gate ( p-type substrate )
n TCP package
General Description
The NT3980 is a data driver IC for a color TFT LCD panel, XGA and SXGA applications. It receives 8 bit per-pixel digital display
data,and generates output voltage for 256 grayscales ,enabling a maximum of 16.77M display colors . For better performance,
dot inversion and a wide range voltage output, 10V, are designed in this chip, and for reducing EMI, data inversion control is
used. This chip supplies 10 sections of voltage -reference for Gamma correction.
Block diagram
OUT1
OUT2
OUT3
OUT384
OUT383
Out Driver Buffer ( 384 channels )
10
V1 ~ V10
8
8
8
8
REV1
REV2
D00 ~ D07
D10 ~ D17
D20 ~ D27
D30 ~ D37
D40 ~ D47
D50 ~ D57
8
Level Shift
8
8
8
8
8
8
8
8
8
48
Line Latch ( 384 X 8 bits X 2 )
Decoder
LD
8
8
1
64
64 Shift Registers
DIO1
Vcc
Version 1.0
POL
Digital to Analog Converter
GND
AVDD
AVSS
CLK
1
DIO2
SHL
October 16, 2001
NT3980
TFT LCD Source Driver
NT3980 TCP ( Top view )
DIO2
D57
D56
D55
D54
D53
D52
D51
D50
D47
D46
D45
D44
D43
D42
D41
D40
D37
D36
D35
D34
D33
D32
D31
D30
Vcc
SHL
V10
V9
V8
V7
V6
AVDD
AVSS
V5
V4
V3
V2
V1
GND
NC
CLK
LD
POL
REV1
REV2
D27
D26
D25
D24
D23
D22
D21
D20
D17
D16
D15
D14
D13
D12
D11
D10
D07
D06
D05
D04
D03
D02
D01
D00
DIO1
NT3980
Version 1.0
OUT384
OUT383
OUT382
OUT381
OUT380
OUT5
OUT4
OUT3
OUT2
OUT1
2
October 16, 2001
NT3980
TFT LCD Source Driver
Pin Description
Designation
D07 ~ D00
D17 ~ D10
D27 ~ D20
D37 ~ D30
D47 ~ D40
D57 ~ D50
REV1
REV2
I/O
V1 ~ V10
I
OUT1 ~
OUT384
SHL
O
DIO1
DIO2
LD
CLK
I
I
Controls whether data are inverted or not.
When “REVx”=1 the data will be inverted. EX. “00” à “ FF”, “07”à “ F8”, “15”à “EA”, and so on.
REV1: control D0x to D2x ,REV2: control D3x to D5x .
(These two pins can be connected together on TCP.)
Gamma correction reference voltage. The voltage of these pins must be AVSS< V10< V9<
V8<V7<V6; V5<V4<V3<V2<V1< AVDD
Output drive signals;
I
Selects left or right shift;
SHL=“1” : DIO1 →OUT1,2,3,4,5,6→OUT7,8,9,10,11,12--→OUT379,380,381,382,383,384= DIO2
SHL=“0” : DIO1=OUT1,2,3,4,5,6←OUT7,8,9,10,11,12←-- OUT379,380,381,382,383,384←DIO2
SHL
DIO1
DIO2
SHIFT
1
Input
Output
Right
0
Output
Input
Left
I/O Start pulse signal input/output
When SHL is applied high (SHL=”1”), a start high-pulse on DIO1 is latched at the rising edge of the
CLK. Then the data are latched serially onto internal latches at the rising edge of the CLK. After all
line latches are filled with data, 64 clocks , a pulse is shifted out through the DIO2 pin at the rising
edge of the CLK. This function can cascade two or more devices for dot expansion. In normal
applications, the DIO2 signal of the first device is connected to the DIO1 of the second stage, the
DIO2 of the second one is connected to the DIO1 of the third, and so on, like a daisy chain.
In contrast, when SHL is applied low, a start pulse inputs on DIO2, and a pulse outputs through
DIO1.
*Remark : The input pulse-width of DIO1/2 may exceed 1 clock-cycle.
I Latches the polarity of outputs and switches the new data to outputs.
1.At the rising edge, the pin latches the “POL” signal to control the polarity of the outputs.
2.This pin also controls the switch of the line registers that switches the new incoming data
to outputs.
*Remark: The LD may switch the new data to outputs at anytime even if the line data are not
completely full.
I Clock input; latching data onto the line latches at the rising edge .
After a start pulse input, display data latching is halted automatically after 64 clock cycles.
*Remark: At least one CLK cycle is necessary during the high -level period of LD.
POL
I
AVDD
AVSS
Vcc
GND
I
I
I
I
Version 1.0
Description
Data input. For six 8-bit data,2 pixels, of color data (R, G, B)
DX7 : MSB; DX0 : LSB
Polarity selector for the dot-inversion control. Available at the rising edge of LD.
“POL” value is latched at the rising edge of “LD” to control the polarity of the even or odd outputs.
“POL=1” indicates that even outputs are of positive polarity with a voltage range from V1~V5, and
odd outputs are of negative polarity with a voltage range from V6 to V10. On the other hand, if LD
receives low level “POL”, even outputs are of negative polarity and odd outputs are of positive
polarity.
POL=1: Even outputs range from V1 ~ V5
Odd outputs range from V6 ~ V10
POL=0: Even outputs range from V6 ~ V10
Odd outputs range from V1 ~ V5
Power supply for analog circuit;
Ground pin for analog circuit
Power supply for digital circuit
Ground pin for digital circuit
3
October 16, 2001
NT3980
TFT LCD Source Driver
Power on/off sequence:
This IC is a high-voltage LCD driver, so it may be damaged by a large current flow when an incorrect power sequence is used.
The recommended connection sequence is to first connect the logical power, Vcc & GND and then connect the drive power,
AVDD&AVSS with V1~V10. When shutting off the power, first shut off the drive power and then the logic system, or turn off all
power simultaneously.
Relationship between the order of input data and output channels
(1) SHL=”1”, shift right, a start pulse from DIO1
Output
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
Order
First data
Data D07~D00 D17~D10 D27~D20 D37~D30 D47~D40 D57~D50
- ---à
- --
OUT384
Last data
D57~D50
(2) SHL=”0” , shift left, a start pulse from DIO2
Output OUT379 OUT380 OUT381 OUT382 OUT383 OUT384
Order
First data
Data D07~D00 D17~D10 D27~D20 D37~D30 D47~D40 D57~D50
- ---à
- --
OUT6
Last data
D57~D50
Relationship between input data and output voltage
The figure below shows the relationship among the input data and the output voltage and the polarity. The range of V1~V5 is
for positive polarity, and V6 ~ V10 for negative polarity. Please refer to the following page to get the relative resistors value and
voltage calculation method.
Gamma correction diagram
Vout
AVDD
V1
V2
Positive polarity
V3
V4
V5
Vcom
V6
V7
V8
Negative polarity
V9
V10
AVSS
00
31
63
95
127
159
191
223
255
Input Data
Remark : AVDD-0.1>V1>V2>V3>V4>V5>AVDD/2; AVDD/2>V6>V7>V8>V9>V10>0.1
Version 1.0
4
October 16, 2001
NT3980
TFT LCD Source Driver
Gamma correction resistor
V1,V10 NAME
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
2880 ohm R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
Version 1.0
Resistor
210
210
150
150
110
110
80
80
80
80
80
80
50
50
50
50
40
40
40
40
40
40
40
40
30
30
30
30
30
30
30
30
30
30
30
30
30
30
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
V2,V9
NAME
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
R94
R95
R96
R97
640 ohm
R98
R99
R100
R101
R102
R103
R104
R105
R106
R107
R108
R109
R110
R111
R112
R113
R114
R115
R116
R117
R118
R119
R120
R121
R122
R123
R124
R125
R126
R127
Resistor
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
V3,V8
640 ohm
5
NAME
R128
R129
R130
R131
R132
R133
R134
R135
R136
R137
R138
R139
R140
R141
R142
R143
R144
R145
R146
R147
R148
R149
R150
R151
R152
R153
R154
R155
R156
R157
R158
R159
R160
R161
R162
R163
R164
R165
R166
R167
R168
R169
R170
R171
R172
R173
R174
R175
R176
R177
R178
R179
R180
R181
R182
R183
R184
R185
R186
R187
R188
R189
R190
R191
Resistor
V4,V7 NAME
10
R192
10
R193
10
R194
10
R195
10
R196
10
R197
10
R198
10
R199
10
R200
10
R201
10
R202
10
R203
10
R204
10
R205
10
R206
10
R207
10
R208
10
R209
10
R210
10
R211
10
R212
10
R213
10
R214
10
R215
10
R216
10
R217
10
R218
10
R219
10
R220
10
R221
10
R222
10
R223
10
R224
10
R225
10
1910 ohm R226
10
R227
10
R228
10
R229
10
R230
10
R231
10
R232
10
R233
10
R234
10
R235
10
R236
10
R237
10
R238
10
R239
10
R240
10
R241
10
R242
10
R243
10
R244
10
R245
10
R246
10
R247
10
R248
10
R249
10
R250
10
R251
10
R252
10
R253
10
R254
V5,V6
10
Resistor
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
30
30
30
30
30
30
30
30
40
40
40
50
50
80
100
130
190
290
October 16, 2001
NT3980
TFT LCD Source Driver
Output Voltage VS Input Data
Data(h)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Version 1.0
Positive polarity Output Voltage
V1
V2 + ( V1 – V2) X 267/288
V2 + ( V1 – V2) X 246/288
V2 + ( V1 – V2) X 231/288
V2 + ( V1 – V2) X 216/288
V2 + ( V1 – V2) X 205/288
V2 + ( V1 – V2) X 194/288
V2 + ( V1 – V2) X 186/288
V2 + ( V1 – V2) X 178/288
V2 + ( V1 – V2) X 170/288
V2 + ( V1 – V2) X 162/288
V2 + ( V1 – V2) X 154/288
V2 + ( V1 – V2) X 146/288
V2 + ( V1 – V2) X 141/288
V2 + ( V1 – V2) X 136/288
V2 + ( V1 – V2) X 131/288
V2 + ( V1 – V2) X 126/288
V2 + ( V1 – V2) X 122/288
V2 + ( V1 – V2) X 118/288
V2 + ( V1 – V2) X 114/288
V2 + ( V1 – V2) X 110/288
V2 + ( V1 – V2) X 106/288
V2 + ( V1 – V2) X 102/288
V2 + ( V1 – V2) X 98/288
V2 + ( V1 – V2) X 94/288
V2 + ( V1 – V2) X 91/288
V2 + ( V1 – V2) X 88/288
V2 + ( V1 – V2) X 85/288
V2 + ( V1 – V2) X 82/288
V2 + ( V1 – V2) X 79/288
V2 + ( V1 – V2) X 76/288
V2 + ( V1 – V2) X 73/288
V2 + ( V1 – V2) X 70/288
V2 + ( V1 – V2) X 67/288
V2 + ( V1 – V2) X 64/288
V2 + ( V1 – V2) X 61/288
V2 + ( V1 – V2) X 58/288
V2 + ( V1 – V2) X 55/288
V2 + ( V1 – V2) X 52/288
V2 + ( V1 – V2) X 50/288
V2 + ( V1 – V2) X 48/288
V2 + ( V1 – V2) X 46/288
V2 + ( V1 – V2) X 44/288
V2 + ( V1 – V2) X 42/288
V2 + ( V1 – V2) X 40/288
V2 + ( V1 – V2) X 38/288
V2 + ( V1 – V2) X 36/288
V2 + ( V1 – V2) X 34/288
V2 + ( V1 – V2) X 32/288
V2 + ( V1 – V2) X 30/288
V2 + ( V1 – V2) X 28/288
V2 + ( V1 – V2) X 26/288
V2 + ( V1 – V2) X 24/288
V2 + ( V1 – V2) X 22/288
V2 + ( V1 – V2) X 20/288
V2 + ( V1 – V2) X 18/288
V2 + ( V1 – V2) X 16/288
V2 + ( V1 – V2) X 14/288
V2 + ( V1 – V2) X 12/288
V2 + ( V1 – V2) X 10/288
V2 + ( V1 – V2) X 8/288
V2 + ( V1 – V2) X 6/288
V2 + ( V1 – V2) X 4/288
V2 + ( V1 – V2) X 2/288
Negative polarity Output Voltage
V10
V10 + ( V 9 – V10) X 21/288
V10 + ( V 9 – V10) X 42/288
V10 + ( V 9 – V10) X 57/288
V10 + ( V 9 – V10) X 72/288
V10 + ( V 9 – V10) X 83/288
V10 + ( V 9 – V10) X 94/288
V10 + ( V 9 – V10) X 102/288
V10 + ( V 9 – V10) X 110/288
V10 + ( V 9 – V10) X 118/288
V10 + ( V 9 – V10) X 126/288
V10 + ( V 9 – V10) X 134/288
V10 + ( V 9 – V10) X 142/288
V10 + ( V 9 – V10) X 147/288
V10 + ( V 9 – V10) X 152/288
V10 + ( V 9 – V10) X 157/288
V10 + ( V 9 – V10) X 162/288
V10 + ( V 9 – V10) X 166/288
V10 + ( V 9 – V10) X 170/288
V10 + ( V 9 – V10) X 174/288
V10 + ( V 9 – V10) X 178/288
V10 + ( V 9 – V10) X 182/288
V10 + ( V 9 – V10) X 186/288
V10 + ( V 9 – V10) X 190/288
V10 + ( V 9 – V10) X 194/288
V10 + ( V 9 – V10) X 197/288
V10 + ( V 9 – V10) X 200/288
V10 + ( V 9 – V10) X 203/288
V10 + ( V 9 – V10) X 206/288
V10 + ( V 9 – V10) X 209/288
V10 + ( V 9 – V10) X 212/288
V10 + ( V 9 – V10) X 215/288
V10 + ( V 9 – V10) X 218/288
V10 + ( V 9 – V10) X 221/288
V10 + ( V 9 – V10) X 224/288
V10 + ( V 9 – V10) X 227/288
V10 + ( V 9 – V10) X 230/288
V10 + ( V 9 – V10) X 233/288
V10 + ( V 9 – V10) X 236/288
V10 + ( V 9 – V10) X 238/288
V10 + ( V 9 – V10) X 240/288
V10 + ( V 9 – V10) X 242/288
V10 + ( V 9 – V10) X 244/288
V10 + ( V 9 – V10) X 246/288
V10 + ( V 9 – V10) X 248/288
V10 + ( V 9 – V10) X 250/288
V10 + ( V 9 – V10) X 252/288
V10 + ( V 9 – V10) X 254/288
V10 + ( V 9 – V10) X 256/288
V10 + ( V 9 – V10) X 258/288
V10 + ( V 9 – V10) X 260/288
V10 + ( V 9 – V10) X 262/288
V10 + ( V 9 – V10) X 264/288
V10 + ( V 9 – V10) X 266/288
V10 + ( V 9 – V10) X 268/288
V10 + ( V 9 – V10) X 270/288
V10 + ( V 9 – V10) X 272/288
V10 + ( V 9 – V10) X 274/288
V10 + ( V 9 – V10) X 276/288
V10 + ( V 9 – V10) X 278/288
V10 + ( V 9 – V10) X 280/288
V10 + ( V 9 – V10) X 282/288
V10 + ( V 9 – V10) X 284/288
V10 + ( V 9 – V10) X 286/288
6
October 16, 2001
NT3980
TFT LCD Source Driver
Output Voltage VS Input Data
Data(h)
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Version 1.0
Positive polarity Output Voltage
V2
V3+(V2-V3) X 63/64
V3+(V2-V3) X 62/64
V3+(V2-V3) X 61/64
V3+(V2-V3) X 60/64
V3+(V2-V3) X 59/64
V3+(V2-V3) X 58/64
V3+(V2-V3) X 57/64
V3+(V2-V3) X 56/64
V3+(V2-V3) X 55/64
V3+(V2-V3) X 54/64
V3+(V2-V3) X 53/64
V3+(V2-V3) X 52/64
V3+(V2-V3) X 51/64
V3+(V2-V3) X 50/64
V3+(V2-V3) X 49/64
V3+(V2-V3) X 48/64
V3+(V2-V3) X 47/64
V3+(V2-V3) X 46/64
V3+(V2-V3) X 45/64
V3+(V2-V3) X 44/64
V3+(V2-V3) X 43/64
V3+(V2-V3) X 42/64
V3+(V2-V3) X 41/64
V3+(V2-V3) X 40/64
V3+(V2-V3) X 39/64
V3+(V2-V3) X 38/64
V3+(V2-V3) X 37/64
V3+(V2-V3) X 36/64
V3+(V2-V3) X 35/64
V3+(V2-V3) X 34/64
V3+(V2-V3) X 33/64
V3+(V2-V3) X 32/64
V3+(V2-V3) X 31/64
V3+(V2-V3) X 30/64
V3+(V2-V3) X 29/64
V3+(V2-V3) X 28/64
V3+(V2-V3) X 27/64
V3+(V2-V3) X 26/64
V3+(V2-V3) X 25/64
V3+(V2-V3) X 24/64
V3+(V2-V3) X 23/64
V3+(V2-V3) X 22/64
V3+(V2-V3) X 21/64
V3+(V2-V3) X 20/64
V3+(V2-V3) X 19/64
V3+(V2-V3) X 18/64
V3+(V2-V3) X 17/64
V3+(V2-V3) X 16/64
V3+(V2-V3) X 15/64
V3+(V2-V3) X 14/64
V3+(V2-V3) X 13/64
V3+(V2-V3) X 12/64
V3+(V2-V3) X 11/64
V3+(V2-V3) X 10/64
V3+(V2-V3) X 9/64
V3+(V2-V3) X 8/64
V3+(V2-V3) X 7/64
V3+(V2-V3) X 6/64
V3+(V2-V3) X 5/64
V3+(V2-V3) X 4/64
V3+(V2-V3) X 3/64
V3+(V2-V3) X 2/64
V3+(V2-V3) X 1/64
Negative polarity Output Voltage
V9
V9+(V8-V9) X 1/64
V9+(V8-V9) X 2/64
V9+(V8-V9) X 3/64
V9+(V8-V9) X 4/64
V9+(V8-V9) X 5/64
V9+(V8-V9) X 6/64
V9+(V8-V9) X 7/64
V9+(V8-V9) X 8/64
V9+(V8-V9) X 9/64
V9+(V8-V9) X 10/64
V9+(V8-V9) X 11/64
V9+(V8-V9) X 12/64
V9+(V8-V9) X 13/64
V9+(V8-V9) X 14/64
V9+(V8-V9) X 15/64
V9+(V8-V9) X 16/64
V9+(V8-V9) X 17/64
V9+(V8-V9) X 18/64
V9+(V8-V9) X 19/64
V9+(V8-V9) X 20/64
V9+(V8-V9) X 21/64
V9+(V8-V9) X 22/64
V9+(V8-V9) X 23/64
V9+(V8-V9) X 24/64
V9+(V8-V9) X 25/64
V9+(V8-V9) X 26/64
V9+(V8-V9) X 27/64
V9+(V8-V9) X 28/64
V9+(V8-V9) X 29/64
V9+(V8-V9) X 30/64
V9+(V8-V9) X 31/64
V9+(V8-V9) X 32/64
V9+(V8-V9) X 33/64
V9+(V8-V9) X 34/64
V9+(V8-V9) X 35/64
V9+(V8-V9) X 36/64
V9+(V8-V9) X 37/64
V9+(V8-V9) X 38/64
V9+(V8-V9) X 39/64
V9+(V8-V9) X 40/64
V9+(V8-V9) X 41/64
V9+(V8-V9) X 42/64
V9+(V8-V9) X 43/64
V9+(V8-V9) X 44/64
V9+(V8-V9) X 45/64
V9+(V8-V9) X 46/64
V9+(V8-V9) X 47/64
V9+(V8-V9) X 48/64
V9+(V8-V9) X 49/64
V9+(V8-V9) X 50/64
V9+(V8-V9) X 51/64
V9+(V8-V9) X 52/64
V9+(V8-V9) X 53/64
V9+(V8-V9) X 54/64
V9+(V8-V9) X 55/64
V9+(V8-V9) X 56/64
V9+(V8-V9) X 57/64
V9+(V8-V9) X 58/64
V9+(V8-V9) X 59/64
V9+(V8-V9) X 60/64
V9+(V8-V9) X 61/64
V9+(V8-V9) X 62/64
V9+(V8-V9) X 63/64
7
October 16, 2001
NT3980
TFT LCD Source Driver
Output Voltage VS Input Data
Data(h)
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
Version 1.0
Positive polarity Output Voltage
V3
V4+(V3-V4) X 63/64
V4+(V3-V4) X 62/64
V4+(V3-V4) X 61/64
V4+(V3-V4) X 60/64
V4+(V3-V4) X 59/64
V4+(V3-V4) X 58/64
V4+(V3-V4) X 57/64
V4+(V3-V4) X 56/64
V4+(V3-V4) X 55/64
V4+(V3-V4) X 54/64
V4+(V3-V4) X 53/64
V4+(V3-V4) X 52/64
V4+(V3-V4) X 51/64
V4+(V3-V4) X 50/64
V4+(V3-V4) X 49/64
V4+(V3-V4) X 48/64
V4+(V3-V4) X 47/64
V4+(V3-V4) X 46/64
V4+(V3-V4) X 45/64
V4+(V3-V4) X 44/64
V4+(V3-V4) X 43/64
V4+(V3-V4) X 42/64
V4+(V3-V4) X 41/64
V4+(V3-V4) X 40/64
V4+(V3-V4) X 39/64
V4+(V3-V4) X 38/64
V4+(V3-V4) X 37/64
V4+(V3-V4) X 36/64
V4+(V3-V4) X 35/64
V4+(V3-V4) X 34/64
V4+(V3-V4) X 33/64
V4+(V3-V4) X 32/64
V4+(V3-V4) X 31/64
V4+(V3-V4) X 30/64
V4+(V3-V4) X 29/64
V4+(V3-V4) X 28/64
V4+(V3-V4) X 27/64
V4+(V3-V4) X 26/64
V4+(V3-V4) X 25/64
V4+(V3-V4) X 24/64
V4+(V3-V4) X 23/64
V4+(V3-V4) X 22/64
V4+(V3-V4) X 21/64
V4+(V3-V4) X 20/64
V4+(V3-V4) X 19/64
V4+(V3-V4) X 18/64
V4+(V3-V4) X 17/64
V4+(V3-V4) X 16/64
V4+(V3-V4) X 15/64
V4+(V3-V4) X 14/64
V4+(V3-V4) X 13/64
V4+(V3-V4) X 12/64
V4+(V3-V4) X 11/64
V4+(V3-V4) X 10/64
V4+(V3-V4) X 9/64
V4+(V3-V4) X 8/64
V4+(V3-V4) X 7/64
V4+(V3-V4) X 6/64
V4+(V3-V4) X 5/64
V4+(V3-V4) X 4/64
V4+(V3-V4) X 3/64
V4+(V3-V4) X 2/64
V4+(V3-V4) X 1/64
Negative polarity Output Voltage
V8
V8+(V7-V8) X 1/64
V8+(V7-V8) X 2/64
V8+(V7-V8) X 3/64
V8+(V7-V8) X 4/64
V8+(V7-V8) X 5/64
V8+(V7-V8) X 6/64
V8+(V7-V8) X 7/64
V8+(V7-V8) X 8/64
V8+(V7-V8) X 9/64
V8+(V7-V8) X 10/64
V8+(V7-V8) X 11/64
V8+(V7-V8) X 12/64
V8+(V7-V8) X 13/64
V8+(V7-V8) X 14/64
V8+(V7-V8) X 15/64
V8+(V7-V8) X 16/64
V8+(V7-V8) X 17/64
V8+(V7-V8) X 18/64
V8+(V7-V8) X 19/64
V8+(V7-V8) X 20/64
V8+(V7-V8) X 21/64
V8+(V7-V8) X 22/64
V8+(V7-V8) X 23/64
V8+(V7-V8) X 24/64
V8+(V7-V8) X 25/64
V8+(V7-V8) X 26/64
V8+(V7-V8) X 27/64
V8+(V7-V8) X 28/64
V8+(V7-V8) X 29/64
V8+(V7-V8) X 30/64
V8+(V7-V8) X 31/64
V8+(V7-V8) X 32/64
V8+(V7-V8) X 33/64
V8+(V7-V8) X 34/64
V8+(V7-V8) X 35/64
V8+(V7-V8) X 36/64
V8+(V7-V8) X 37/64
V8+(V7-V8) X 38/64
V8+(V7-V8) X 39/64
V8+(V7-V8) X 40/64
V8+(V7-V8) X 41/64
V8+(V7-V8) X 42/64
V8+(V7-V8) X 43/64
V8+(V7-V8) X 44/64
V8+(V7-V8) X 45/64
V8+(V7-V8) X 46/64
V8+(V7-V8) X 47/64
V8+(V7-V8) X 48/64
V8+(V7-V8) X 49/64
V8+(V7-V8) X 50/64
V8+(V7-V8) X 51/64
V8+(V7-V8) X 52/64
V8+(V7-V8) X 53/64
V8+(V7-V8) X 54/64
V8+(V7-V8) X 55/64
V8+(V7-V8) X 56/64
V8+(V7-V8) X 57/64
V8+(V7-V8) X 58/64
V8+(V7-V8) X 59/64
V8+(V7-V8) X 60/64
V8+(V7-V8) X 61/64
V8+(V7-V8) X 62/64
V8+(V7-V8) X 63/64
8
October 16, 2001
NT3980
TFT LCD Source Driver
Output Voltage VS Input Data
Data(h)
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
Version 1.0
Positive polarity Output Voltage
V4
V5+(V4-V5) X 190/191
V5+(V4-V5) X 189/191
V5+(V4-V5) X 188/191
V5+(V 4-V5) X 187/191
V5+(V4-V5) X 186/191
V5+(V4-V5) X 185/191
V5+(V4-V5) X 184/191
V5+(V4-V5) X 183/191
V5+(V4-V5) X 182/191
V5+(V4-V5) X 181/191
V5+(V4-V5) X 180/191
V5+(V4-V5) X 179/191
V5+(V4-V5) X 178/191
V5+(V4-V5) X 177/191
V5+(V4-V5) X 176/191
V5+(V4-V5) X 175/191
V5+(V4-V5) X 174/191
V5+(V4-V5) X 173/191
V5+(V4-V5) X 172/191
V5+(V4-V5) X 171/191
V5+(V4-V5) X 170/191
V5+(V4-V5) X 169/191
V5+(V4-V5) X 168/191
V5+(V4-V5) X 167/191
V5+(V4-V5) X 165/191
V5+(V4-V5) X 163/191
V5+(V4-V5) X 161/191
V5+(V4-V5) X 159/191
V5+(V4-V5) X 157/191
V5+(V4-V5) X 155/191
V5+(V4-V5) X 153/191
V5+(V4-V5) X 151/191
V5+(V4-V5) X 149/191
V5+(V4-V5) X 147/191
V5+(V4-V5) X 145/191
V5+(V4-V5) X 143/191
V5+(V4-V5) X 141/191
V5+(V4-V5) X 139/191
V5+(V4-V5) X 137/191
V5+(V 4-V5) X 135/191
V5+(V4-V5) X 133/191
V5+(V4-V5) X 131/191
V5+(V4-V5) X 129/191
V5+(V4-V5) X 127/191
V5+(V4-V5) X 125/191
V5+(V4-V5) X 122/191
V5+(V4-V5) X 119/191
V5+(V4-V5) X 116/191
V5+(V4-V5) X 113/191
V5+(V4-V5) X 110/191
V5+(V4-V5) X 107/191
V5+(V4-V5) X 104/191
V5+(V4-V5) X 101/191
V5+(V4-V5) X 97/191
V5+(V4-V5) X 93/191
V5+(V4-V5) X 89/191
V5+(V4-V5) X 84/191
V5+(V4-V5) X 79/191
V5+(V4-V5) X 71/191
V5+(V4-V5) X 61/191
V5+(V4-V5) X 48/191
V5+(V4-V5) X 29/191
V5
Negative polarity Output Voltage
V7
V7+(V6-V7) X 1/191
V7+(V6-V7) X 2/191
V7+(V6-V7) X 3/191
V7+(V6-V7) X 4/191
V7+(V6-V7) X 5/191
V7+(V6-V7) X 6/191
V7+(V6-V7) X 7/191
V7+(V6-V7) X 8/191
V7+(V6-V7) X 9/191
V7+(V6-V7) X 10/191
V7+(V6-V7) X 11/191
V7+(V6-V7) X 12/191
V7+(V6-V7) X 13/191
V7+(V6-V7) X 14/191
V7+(V6-V7) X 15/191
V7+(V6-V7) X 16/191
V7+(V6-V7) X 17/191
V7+(V6-V7) X 18/191
V7+(V6-V7) X 19/191
V7+(V6-V7) X 20/191
V7+(V6-V7) X 21/191
V7+(V6-V7) X 22/191
V7+(V6-V7) X 23/191
V7+(V6-V7) X 24/191
V7+(V6-V7) X 26/191
V7+(V6-V7) X 28/191
V7+(V6-V7) X 30/191
V7+(V6-V7) X 32/191
V7+(V6-V7) X 34/191
V7+(V6-V7) X 36/191
V7+(V6-V7) X 38/191
V7+(V6-V7) X 40/191
V7+(V6-V7) X 42/191
V7+(V6-V7) X 44/191
V7+(V6-V7) X 46/191
V7+(V6-V7) X 48/191
V7+(V6-V7) X 50/191
V7+(V6-V7) X 52/191
V7+(V6-V7) X 54/191
V7+(V6-V7) X 56/191
V7+(V6-V7) X 58/191
V7+(V6-V7) X 60/191
V7+(V6-V7) X 62/191
V7+(V6-V7) X 64/191
V7+(V6-V7) X 66/191
V7+(V6-V7) X 69/191
V7+(V6-V7) X 72/191
V7+(V6-V7) X 75/191
V7+(V6-V7) X 78/191
V7+(V6-V7) X 81/191
V7+(V6-V7) X 84/191
V7+(V6-V7) X 87/191
V7+(V6-V7) X 90/191
V7+(V6-V7) X 94/191
V7+(V6-V7) X 98/191
V7+(V6-V7) X 102/191
V7+(V6-V7) X 107/191
V7+(V6-V7) X 112/191
V7+(V6-V7) X 120/191
V7+(V6-V7) X 130/191
V7+(V6-V7) X 143/191
V7+(V6-V7) X 162/191
V6
9
October 16, 2001
NT3980
TFT LCD Source Driver
Absolute Maximum Ratings*
Supply voltage, Vcc
Supply voltage, AVDD
Input voltage, V1~ V10
Input range(digital inputs)
Storage temperature
Operating temperature
*Comments
-0.3V to 5V
-0.3V to +12V
-0.3 to AVDD+0.3
-0.3 to Vcc+0.3
-55℃ to 110℃
-30℃ to 75 ℃
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or under any other conditions above those
indicated in the operational sections of this specification are
not implied and exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DC Electrical Characteristics (V cc =3.3V , AV DD=10V, AVSS=GND=0V, TA = -30℃~ 75 ℃)
(For the digital circuit)
Parameter
Supply Voltage
Low Level Input Voltage
High Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Gamma correction Current
Digital Operating Current
Symbol
Min.
Vcc
2.5
Vil
0
Vih
0.7xVcc
Voh
0.7xVcc
Vol
-Ii
-1
Iref
-Icc
-
Typ.
-800
3
Max.
3.6
0.3xVcc
Vcc
-0.3Vcc
1
1000
6
Unit
V
V
V
V
V
µA
µA
mA
Typ.
-±6
±2
±5
Max.
10
AVDD-0.1
AVDD/2
±12
±5
±10
Unit
V
V
V
mV
mV
mV
Conditions
Digital power
For the digital circuit
For the digital circuit
DIO1(O), DIO2(O), Ioh=-0.4mA
DIO1(O), DIO2(O), Iol=0.4mA
For LD,CLK,SHL,Dxx,POL,REV1/2,DIO1/2
For V1-V5=4.75V or V6-V10=4.75V
Vcc=3.6V, AVDD=9.5V,fld=50kHz,fclk=45MHz
No load
(For the analog circuit)
Parameter
Supply Voltage
Input level of V1 ~ V5
Input level of V6 ~ V10
Output Voltage Deviation
Symbol
AVDD
Vref
Vref
Vvd
Average output voltage
dispersion
Dynamic Range of Output
Low-Level Output Current
High-Level Output Current
Analog Operating Current
Vod
Min.
7.0
AVDD/2
0.1
----
Vdr
IOL
IOH
IDD
0.1
-150
150
-
-300
300
6
AVDD-0.1
12
V
µA
µA
mA
Input capacitance1
Input capacitance2
C1
C2
---
5
10
10
15
pF
pF
Conditions
For the analog circuit power
Gamma correction voltage
Gamma correction voltage
Input data ‘without’ offset cancellation
Input data ‘with’ offset cancellation (Note1)
OUT1 ~ OUT384,input data 00 to FF.
OUT1 ~ OUT384
OUT1 ~ OUT384; Vo=0.1V V.S 1.0V
OUT1 ~ OUT384; Vo=9.9V V.S 9V
Vcc=3.6V,AVDD=9.5V,fld=50kHz,fclk=45MHz
No load
For Input pins ,except DIO1,DIO2
For DIO1,DIO2
(Note 1) This chip needs 253 CLK cycles to use its 'offset cancellation' function to get a precision output voltage.
Please refer to the timing chart below :
LD
1
2
3
4
5
252
253
254
CLK
Outputs
Finish 'offset
cancellation'
Version 1.0
10
October 16, 2001
NT3980
TFT LCD Source Driver
AC Electrical Characteristics 1 (Vcc =3.0V , AV DD=10V, AVSS=GND=0V, TA = -30 ~ 75℃,Tr=Tf=2ns)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
CLK frequency
Fclk
45
70
MHz Vcc=3.0~3.6V
CLK period cycle
Tcph
14
ns
CLK pulse width
Tcw
4
ns
Data set-up time
Tsu
2
ns
D00 ~ D57, REV to CLK
Data hold time
Thd
2
ns
D00 ~ D57, REV to CLK
Start pulse setup time
Tss
2
--ns
DIO1,DIO2 to CLK
Start pulse hold time
Tsh
2
--ns
DIO1,DIO2 to CLK
LD high-level width
Tld
1
--us
Propagation delay of DIO2/1
Tplh
6
-12
ns
CL=25pF ( Output )
Time that the last data to LD
Tldt
1
Tcph
Time that LD to DIO1/2(In)
Tlds
2
Tcph
POL set-up time
Tpsu
5
ns
POL to LD
POL hold time
Tphd
5
ns
POL to LD
Output stable time
Tst
4
6
us
Final value precision below 30mV,
CL=150pF,R=5k ohm ,AVDD=10V
Slew rate of outputs
Tsr
3
5
V/us 5% to 95% at 10V swing,
CL=150pF,R=5k ohm
Output loading
CL
pF
150
AC Electrical Characteristics 2 (Vcc =2.5V , AV DD=10V, AVSS=GND=0V, TA = -30~75℃,Tr=Tf=3ns)
Parameter
CLK frequency
CLK period cycle
CLK pulse width
Data set-up time
Data hold time
Start pulse setup time
Start pulse hold time
LD high-level width
Propagation delay of DIO2/1
Time that the last data to LD
Time that LD to DIO1/2(In)
POL set-up time
POL hold time
Output stable time
Symbol
Fclk
Tcph
Tcw
Tsu
Thd
Tss
Tsh
Tld
Tplh
Tldt
Tlds
Tpsu
Tphd
Tst
Min.
22
7
4
4
4
4
1
6
1
2
5
5
-
Typ.
35
----4
Max.
45
---18
6
Unit
MHz
ns
ns
ns
ns
ns
ns
us
ns
Tcph
Tcph
ns
ns
us
Slew rate of outputs
Tsr
3
5
-
V/us
Output loading
CL
-
-
150
pF
Version 1.0
11
Conditions
Vcc=2.5~3.0V
D00 ~ D57, REV to CLK
D00 ~ D57, REV to CLK
DIO1,DIO2 to CLK
DIO1,DIO2 to CLK
CL=25pF ( Output )
POL to LD
POL to LD
Final value precision below 30mV,
CL=150pF,R=5k ohm ,AVDD=10V
5% to 95% at 10V swing,
CL=150pF,R=5k ohm
October 16, 2001
NT3980
TFT LCD Source Driver
Timing Diagram
Tr
Tf
Tcph
0.8Vcc
CLK
0
0.2Vcc
Tss
1
0.5Vcc
0.7Vcc
2
63
0.3Vcc
Tcw
Tsh
64
Tcw
DIO1/2
( Input )
Tsu
Data
REV1
REV2
Thd
First data
Second data
Last data
Tplh
Tplh
DIO1/2
( Output )
CLK
Last
Tld
Tldt
LD
Tlds
DIO1/2
( Input )
LD
Tpsu Tpdh
POL
95%
Odd outputs
5%
Positive
Tsr
High-Z
Even outputs
final value precision
below 30mV
High-Z
Tst
final value precision
below 30mV
Test point
Output load condition :
1K
High-Z
Tst
1K
1K
1K
Negative
1K
Output
30P
30P
30P
30P
30P
Vcom
Version 1.0
12
October 16, 2001
NT3980
TFT LCD Source Driver
Function operation
CLK
2CLK ( min.)
DIO1/2
( Input )
1CLK ( min.)
LD
1CLK
Data,
REV1
REV2
N-2
N-1
N
1
Last Data
2
3
First Data
LD
POL
Odd Outputs
Vcom
V1 ~V5
V6 ~V10
Even Outputs
Vcom
V1 ~V5
V6 ~V10
Version 1.0
13
October 16, 2001