SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
8 - Bit Micro-controller
with 8KB flash & 256 Bytes RAM embedded
Product List
SM79108L25, 25 MHz 8KB internal memory MCU
SM79108C40, 40 MHz 8KB internal memory MCU
Features
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version
Description
General 8052 family compatible
12 clocks per machine cycle
The SM79108 series product is an 8 - bit single chip micro
controller with 8 KB flash & 256 bytes RAM embedded. It
has 4-channel, 8-bit ADC function build-in, 1-channel
SPWM and 1-channel PWM build-in and A14(segment) x
4(common) LCD driver. It provides hardware features and
a powerful instruction set necessary to make it a versatile
and cost effective controller for those applications demand
up to 32 I/O pins for PDIP package or up to 36 I/O pins for
PLCC/QFP package, or applications which need up to 64K
byte flash memory for program and/or for data.
8 KB internal flash memory
To program the flash block, a commercial programmer
is capable to do it.
Full duplex serial channel
256 bytes on-chip data RAM
Three 16 bit timers/counters
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or
QFP package
A14 x 4 LCD driver (P0, P2, ALE, PSEN)
1 Channel SPWM (P1.2)
1 Channel PWM (P1.5)
Bit operation instruction
Industrail Level
Ordering Information
8-bit unsigned division
8-bit unsigned multiply
yywwv: production date code identifier
SM79108ihhk
BCD arithmetic
Direct addressing
yy: year, ww: weak, v: version
i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin/Pad
Configuration
page 2
page 2
page 2
Indirect addressing
Nested interrupt
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and power down mode
Dimension
page 22
page 23
page 24
Code protection function
One watch dog timer (WDT)
Low EMI (inhibit ALE)
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-578-3344 #2667
886-3-579-2987
FAX: 886-3-5792960
886-3-5780493
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
P2.6/A14/SEG2
P2.5/A13/SEG1
P2.7/A15/SEG3
#PSEN/SEG4
P0.7/AD7/SEG6
#EA
P0.6/AD6/SEG7
P0.5/AD5/SEG8
P0.4/AD4/SEG9
Pin Configurations
39
P0.0/AD0/SEG13
SPWM/P1.2
3
38
P0.1/AD1/SEG12
P1.3
4
37
P0.2/AD2/SEG11
P1.4
5
36
P0.3/AD3/SEG10
PWM/P1.5
6
35
P0.4/AD4/SEG9
SEG10/AD3/P0.3
P0.5/AD5/SEG8
SEG11/AD3/P0.2
P1.6
7
34
P0.6/AD6/SEG7
P1.7
32
P0.7/AD7/SEG6
RES
RXD/P3.0
9
10
31
#EA
SEG12/AD3/P0.1
SEG13/AD3/P0.0
VDD
36
8
33
39
TXD/P3.1
11
30
ALE/SEG5
#INT/P3.2
12
29
#PSEN/SEG4
P4.2
T2/P1.0
T2EX/P1.1
42
14
#INT1/P3.3
13
28
P2.7/A15/SEG3
43
13
ADC0/T0/P3.4
14
27
P2.6/A14/SEG2
SPWM/P1.2
P1.3
P1.4
ADC1/T1/P3.5
15
26
P2.5/A13/SEG1
ADC2/#WR/P3.6
16
25
P2.4/A12/SEG0
ADC3/#RD/P3.7
17
24
P2.3/A11/COM3
XTAL2
XTAL1
VSS
18
23
P2.2/A10/COM2
19
22
P2.1/A9/COM1
20
21
P2.0/A8/COM0
6
4
3
2
1 44 43 42 41 40
8
9
10
11
12
13
SM79108 jhhJ
39
P0.4/AD4/SEG9
38
37
P0.5/AD5/SEG8
P0.6/AD6/SEG7
36
P0.7/AD7/SEG6
35
33
#EA
P4.1
ALE/SEG5
32
#PSEN/SEG4
31
30
P2.7/A15/SEG3
P2.6/A14/SEG2
29
P2.5/A13/SEG1
44L PLCC
34
(Top View)
21
20
SM79108 jhhQ
37
38
19
18
44L QFP
(Top View)
40
41
17
16
15
44
12
XTAL1
XTAL2
P3.7/#RD/ADC3
P3.6/#WR/ADC2
8
9
#INT1/P3.3
ADC0/T0/P3.4
ADC1/T1/P3.5
7
#INT0/P3.2
5
P2.3/A11/COM3
P2.2A10/COM2
P2.1/A9/COM1
P2.0A8/COM0
P4.0
VSS
10 11
6
P4.3
4
TXD/P3.1
3
P1.7
RES
RXD/P3.0
2
PWM/P1.5
P1.6
1
P2.4/A12/SEG0
SEG0/A12/P2.4
COM3/A11/P2.3
COM1/A9/P2.1
COM2/A10/P2.2
P4.0
COM0/A8/P2.0
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
XTAL2
XTAL1
VSS
33 32 31 30 29 28 27 26 25 24 23
22
P0.3/AD3/SEG10
P1.1/T2EX
P1.0/T2
P4.2
VDD
P0.0/AD0/SEG13
P0.1/AD1/SEG12
P1.3
P1.2/SPWM
5
7
ADC2/#WR/P3.6
ADC3/#RD/P3.7
PWM/P1.5
P1.6
P1.7
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
ADC0/T0/P3.4
ADC1/T1/P3.5
34
35
P4.1
ALE/SEG5
VDD
2
P0.2/AD2/SEG11
40
T2EX/P1.1
P1.4
1
SM79108 ihhP
40L PDIP
(Top View)
T2/P1.0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
Block Diagram
Timer 1
Timer 2
Decoder &
Register
Stack
Pointer
Timer 0
256
bytes RAM
Buffer
WDT
RES
to pertinent blocks
Reset
Circuit
Vdd
PC
Incrementer
to whole chip
Power
Circuit
Vss
DPTR
Acc
Buffer2
to pertinent blocks
Interrupt
Circuit
Buffer1
Program
Counter
ALU
Register
PSW
XTAL2
XTAL1
#EA
Timing
to whole system
Generator
ALE/SEG5
#PSENSEG4
Instruction
Register
8K
bytes
ADC
Port 0
Latch
Port 1
Latch
Port 2
Latch
Flash
Memory
Port 3
Latch
SPWM
PWM
LCD
Driver
(14 x 4)
Port 0
Driver & Mux
8
Port 1
Port 2
Port 3
Driver & Mux Driver & Mux Driver & Mux
8
8
8
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
Pin Descriptions
40L
44L
44L
PDIP QFP PLCC
Symbol
Pin# Pin# Pin#
1
40
2
P1.0/T2
2
41
3
P1.1/T2EX
3
42
4
P1.2/SPWM
4
43
5
P1.3
5
44
6
P1.4
6
1
7
P1.5/PWM
7
2
8
P1.6
8
3
9
P1.7
9
4
10
RES
10
5
11
P3.0/RXD
11
7
13
P3.1/TXD
12
8
14
P3.2/#INT0
13
9
15
P3.3/#INT1
14
10
16
P3.4/T0/ADC0
15
11
17
P3.5/T1/ADC1
16
12
18
P3.6/#WR/ADC2
17
13
19
P3.7/#RD/ADC3
18
14
20
XTAL2
19
15
21
XTAL1
20
16
22
VSS
21
18
24
P2.0/A8/COM0
22
19
25
P2.1/A9/COM1
23
20
26
P2.2/A10/COM2
24
21
27
P2.3/A11/COM3
25
22
28
P2.4/A12/SEG0
26
23
29
P2.5/SEG1
27
24
30
P2.6/SEG2
28
25
31
P2.7/SEG3
29
26
32
#PSEN/SEG4
30
27
33
ALE/SEG5
31
29
35
#EA
32
30
36
P0.7/AD7/SEG6
33
31
37
P0.6/AD6/SEG7
34
32
38
P0.5/AD5/SEG8
35
33
39
P0.4/AD4/SEG9
36
34
40
P0.3/AD3/SEG10
37
35
41
P0.2/AD2/SEG11
38
36
42
P0.1/AD1/SEG12
39
37
43
P0.0/AD0/SEG13
40
38
44
VDD
17
23 P4.0
28
34 P4.1
39
1 P4.2
6
12 P4.3
Active
H
-/L
-/L
L
I/O
(GPIO)
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
Names
bit 0 of port 1 & timer 2 clock out
bit 1 of port 1 & timer 2 control
bit 2 of port 1 & SPWM channel
bit 3 of port 1
bit 4 of port 1
bit 5 of port 1 & PWM channel
bit 6 of port 1
bit 7 of port 1
Reset
bit 0 of port 3 & receive data
bit 1 of port 3 & transmit data
bit 2 of port 3 & low true interrupt 0
bit 3 of port 3 & low true interrupt 1
bit 4 of port 3 & ADC channel 0 & Timer 0
bit 5 of port 3 & ADC channel 1 &Timer 1
bit 6 of port 3 & ADC channel 2 & external memory write
bit 7 of port 3 & ADC channel 3 & external memory read
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of external memory address & LCCD common 0 output
bit 1 of port 2 & bit 9 of external memory address & LCCD common 1 output
bit 2 of port 2 & bit 10 of external memory address & LCCD common 2 output
bit 3 of port 2 & bit 11 of external memory address & LCCD common 3 output
bit 4 of port 2 & bit 12 of external memory address & LCCD seg 0 output
bit 5 of port 2 & LCCD seg 1 output
bit 6 of port 2 & LCCD seg 2 output
bit 7 of port 2 & LCCD seg 3 output
program storage enable & LCCD seg 4 output
address latch enable & LCCD seg 5 output
external access
bit 7 of port 0 & data/address bit 7 of external memory & LCCD seg 6 output
bit 6 of port 0 & data/address bit 6 of external memory & LCCD seg7 output
bit 5 of port 0 & data/address bit 5 of external memory & LCCD seg 8 output
bit 4 of port 0 & data/address bit 4 of external memory & LCCD seg 9 output
bit 3 of port 0 & data/address bit 3 of external memory & LCCD seg 10 output
bit 2 of port 0 & data/address bit 2 of external memory & LCCD seg 11 output
bit 1 of port 0 & data/address bit 1 of external memory & LCCD seg 12 output
bit 0 of port 0 & data/address bit 0 of external memory & LCCD seg 13 output
Drive Voltage, Vcc
bit 0 of Port 4
bit 1 of Port 4
bit 2 of Port 4
bit 3 of Port 4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/26
Preliminary
Ver 1.0
SM79108 01/03
SFR Memory MAP
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
SFR Memory MAP
0F8H
0F0H
0E8H
0FFH
0F7H
0EFH
B
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
ACC
LCDB0
LCDB1
LCDB2
LCDB3
LCDB4
LCDB5
LCDB6
P4
LCDCON
PSW
T2CON
IP
PWMC0
RCAP2L
T2MOD
RCAP2H
IE
PWMD0
IE1
IFR
SBUF
P0CON
SPWMC
SPWMD0
P1CON
P2CON
P3CON
WDTC
P1
88H
80H
0C7H
0BFH
0B7H
SCONF
P2
SCON
TH2
IP1
P3
0B0H
0A8H
0A0H
98H
90H
TL2
WDTKEY
TCON
TMOD
TL0
TL1
TH0
P0
SP
DPL
DPH
(Reserved)
TH1
ADSCR
0E7H
0DFH
0D7H
0CFH
ADCD
PCON
0AFH
0A7H
9FH
97H
8FH
87H
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM79108
Addr
SFR
Reset
7
6
5
4
3
2
1
0
8EH
ADSCR
0000_00**
COM
CON
ADCSS1
ADCSS0
CH1
CH0
Reserved
Reserved
8FH
ADCD
00H
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
97H
WDTKEY
00H
9AH
P0CON
00H
WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
SEG6
SEG7
SEG8
SEG9
SEG10
COME3
SGE12
SEG13
COME2
COME1
COME0
PS0
9BH
P1CON
**0*_*0**
9CH
P2CON
00H
SEG3
SEG2
SEG1
SEG0
9DH
P3CON
00H
ADCE3
ADCE2
ADCE1
ADCE0
9FH
WDTC
000*_*000
WDTE
R
CLEAR
PS2
PS1
SPFS1
SPFS0
SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00
BRM02
BRM01
BRM00
PWMD02
PWMD01
PWMD00
PBS
PFS1
PFS0
P4.2
P4.1
P4.1
LS2
LS1
LS0
SEG1
SEG1
SEG1
0A3H
SPWMC0 ****_**00
0A4H
SPWMD0
00H
PWME0
SEG11
SPWME0
0A9H
IE1
****_0***
EADC
0AAH
IFR
****_0***
ADCIF
0B3H
PWMD0
00H
0B9H
IP1
****_0***
0BFH
SCONF
0***_***0
0D3H
PWMC0
****_*000
P4
****_1111
0D8H
0DFH
0E1H
LCDCON 000*_*000
LCDB0
00H
PWMD07
PWMD06
PWMD05
PWMD04
PWMD03
PADC
WDR
Reserved
P4.3
Lout_en
Lcd_en
SEG
SEG0
SEG0
SEG0
SEG0
SEG1
ALEI
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
Addr
SFR
Reset
7
6
5
4
3
2
1
0
0E2H
LCDB1
00H
SEG2
SEG2
SEG2
SEG2
SEG3
SEG3
SEG3
SEG3
0E3H
LCDB2
00H
SEG4
SEG4
SEG4
SEG4
SEG5
SEG5
SEG5
SEG5
0E4H
LCDB3
00H
SEG6
SEG6
SEG6
SEG6
SEG7
SEG7
SEG7
SEG7
0E5H
LCDB4
00H
SEG8
SEG8
SEG8
SEG8
SEG9
SEG9
SEG9
SEG9
0E6H
LCDB5
00H
SEG10
SEG10
SEG10
SEG10
SEG11
SEG11
SEG11
SEG11
0E7H
LCDB6
00H
SEG12
SEG12
SEG12
SEG12
SEG13
SEG13
SEG13
SEG13
1. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the
WDT counter. User should check WDR bit of SCONF register whenever unpracticed reset happened
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is independent to the system frequency.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count
with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when
SM79108 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of
the 16-bit counter and let the counter re-start to count from the beginning.
1.1 Watch Dog Timer Registers:
Watch Dog Key Register - (WDTKEY, 97H)
bit-7
bit-0
WDT
WDT
WDT
WDT
WDT
WDT
WDT
WDT
KEY7
KEY6
KEY5
KEY4
KEY3
KEY2
KEY1
KEY0
Read / Write:
W
W
W
W
W
W
W
W
Reset value:
0
0
0
0
0
0
0
0
By default, the WDTC is read only. User need to write values 1EH, 0E1H sequentially to the WDTKEY(97H) register to
enable the WDTC write attribute, That is
MOV WDTKEY, # 1EH
MOV WDTKEY, # E1H
When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY(97H) register to disable the
WDTC write attribute, That is
MOV WDTKEY, # E1H
MOV WDTKEY, # 1EH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
Watch Dog Timer Registers - WDT Control Register (WDTC, 9FH)
bit-7
bit-0
WDTE
R
CLEAR
Unused
Unused
PS2
PS1
PS0
Read / Write:
R/W
-
R/W
-
-
R/W
R/W
R/W
Reset value:
0
0
0
*
*
0
0
0
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS[2:0] : Overflow period select bits
PS [2:0]
Overflow Period (ms)
000
2.048
001
4.096
010
8.192
011
16.384
100
32.768
101
65.536
110
131.072
111
262.144
System Control Register (SCONF, 0BFH)
bit-7
bit-0
WDR
Unused
Unused
Unused
Unused
Reserved
Unused
ALEI
Read / Write:
R/W
-
-
-
-
-
-
R/W
Reset value:
0
*
*
*
*
*
*
0
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
ALEI : ALE output inhibit bit, to reduce EMI
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow.
User should check WDR bit whenever unpredicted reset happened.
2. Reduce EMI Function
The SM79108 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
3. Port 4 for PLCC or QFP package:
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is
located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, 0D8H)
bit-7
bit-0
Unused
Unused
Unused
Unused
P4.3
P4.2
P4.1
P4.0
Read / Write:
-
-
-
-
R/W
R/W
R/W
R/W
Reset value:
*
*
*
*
1
1
1
1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
4. SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary
rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of
the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The
number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to
generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock
speed. The SPFS[1:0] settings of SPWMC (0A3H) register are divided of Fosc to be SPWM clock, Fosc/
2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/
2^(SPFS[1:0]+1)]/32.
4.1 SPWM Registers - P1CON, SPWMC0, SPWMD0
SPWM Registers - Port1 Configuration Register (P1CON, 9BH)
bit-7
bit-0
Unused
Unused
PWME0
Unused
Unused
SPWME0
Unused
Unused
Read / Write:
-
-
R/W
-
-
R/W
-
-
Reset value:
*
*
0
*
*
0
*
*
SPWME0 : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset
to zero, the corresponding SPWM pin is active as I/O pin. Four bits are cleared upon reset.
PWME0 : When the bit set to one, the corresponding PWM pin is active as PWM function. When the bit reset
to zero, the corresponding PWM pin is active as I/O pin. Four bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, 0A3H)
bit-7
bit-0
Unused
Unused
Unused
Unused
Unused
Unused
SPFS1
SPFS0
Read / Write:
-
-
-
-
-
-
R/W
R/W
Reset value:
*
*
*
*
*
*
0
0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SPFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
SPFS1
SPFS0
Divider
SPWM clock, Fosc=20MHz
SPWM clock, Fosc=24MHz
0
0
2
10MHz
12MHz
0
1
4
5MHz
6MHz
1
0
8
2.5MHz
3MHz
1
1
16
1.25MHz
1.5MHz
SPWM Registers - SPWM Data Register (SPWMD0, 0A4H)
bit-7
bit-0
SPWMD04
SPWMD03
SPWMD02
SPWMD01
SPWMD00
BRM02
BRM01
BRM00
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value:
0
0
0
0
0
0
0
0
SPWMD0[4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame
N = BRM[2:0]
Number of SPWM cycles inserted in an 8-cycle frame
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Example of SPWM timing diagram:
MOV SPWMD0 , #83H
MOV P1CON , #04H
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM0[2:0] = 3
; Enable P1.2 as SPWM output pin
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1st cycle frame
2nd cycle frame 3rd cycle frame
32T
32T
32T
32T
6th cycle frame 7th cycle frame
32T
16T
1T
1T
(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
8th cycle frame
32T
32T
16T
16T
16T
16T
16T
4th cycle frame 5th cycle frame
16T
32T
16T
1T
SPWM clock = 1 / T = Fosc / 2^(SPFS[1:0]+1)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32
If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
5. PWM Function Description:
Each PWM channel contains a 8-bit wide PWM data register (PWMDR) to decide number of continuous pulses within a
PWM frame cycle. The value programmed in the register will determine the pulse length of the output. The PWM channel
can be configured as 5-bit or 8-bit resolution. If a channel is configured as 5-bit resolution, only LSB 5 bits are available.
The value of each PWM Data Register (PWMDR) is continuously compared with the content of an internal counter to determine the state of each PWM channel output pin.
5.1 PWM Registers - PWMC0, PWMD0
PWM Registers - PWM Control Register (PWMC0, 0D3H)
bit-7
bit-0
Unused
Unused
Unused
Unused
Unused
PBS
PFS1
PFS0
Read / Write:
-
-
-
-
-
R/W
R/W
R/W
Reset value:
*
*
*
*
*
0
0
0
PFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
PBS: This bit decides channel bit resolution. If PBS is set, the channel is 5-bit resolution.
PFS1
PFS0
Divider
PWM clock, Fosc=12MHz
PWM clock, Fosc=24MHz
0
0
16
750KHz
1.5MHz
0
1
32
375KHz
750KHz
1
0
64
187.5KHz
375KHz
1
1
128
93.75KHz
187.5KHz
Example : If user use Fosc = 20MHz, PFS[1:0] of PWMC = #03H, PBS = 0, then
PWM Clock = 20MHz / 128 = 156.25KHz
PWM Output cycle frame frequency = 156.25KHz / 256 = 610 Hz
Note : For bzzer application
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PWM Registers - PWM Data Register (PWMD0, 0B3H)
bit-7
bit-0
PWMD07
PWMD06
PWMD05
PWMD04
PWMD03
PWMD02
PWMD01
PWMD00
Read /Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value:
0
0
0
0
0
0
0
0
PWM[7:0]: content of PWM Data Register. If PBS is set, only PWM[4:0] are available.
Example of PWM timing diagram:
For 5-bit resolution channel, M = content of PWMD0:
M = 00H
32T
M = 01H
M = 0FH
M = 1FH
For 8-bit resolution channel:
M = 00H
256T
M = 01H
M = 7FH
M = 0FFH
PWM clock = 1/T = Fosc / 2^ ( PFS [1:0] + 1 )
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6. Analog-to-Digital Converter (ADC)
The SM79108 equips with 4-channels, 8-bit ADC which is available at P3.4~P3.7. S/W can select one of the 4 ADC channels by setting SFR ADC Status and Control Register (ADSCR, 8EH) bit CH0~CH1. The ADC can do single conversion or
continuously conversion. When the conversion is completed, ADC puts the result in the ADC Data Register (ADCD, 8FH)
and sets COM bit of ADSCR (ADSCR.7). After channel selection bit CH[1:0] of ADSCR and P3CON been set, the selected
pin of P3.4~P3.7 will function as ADC input pin instead of general purpose I/O pin which is due to priority of ADC function is
higher than I/O function. The rest of the P3.4~P3.7 pin will still function as general purpose I/O pin. Writes to the port register
will have no affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return the
value in the port which is been read.
6.1 Straight line conversion
The ADC conversion relationship of input analog signal to digital output value is a linear straight line conversion relationship.
It will convert input signal in +Vdd V or above to 0FFH (full scale) and convert input signal +0V or below to 00H. The +Vdd is
the voltage applied to the IC.
6.2 ADC input clock frequency range
ADC input clock frequency range = 500KHz ~ 2.5MHz. User need to be aware of this frequency range limitation when using
ADC function. The frequency range limitation was induced by the sample-and-hold and DAC converter circuits inside of the
ADC submodule. If the ADC input clock frequency resides outside of the range then ADC function may not work.
ADC input clock frequency = oscillator frequency / divider. Divider elected by ADCSS[1:0] setting of ADSCR
One conversion time = 20 ADC clock cycles / ADC input clock frequency
Maximum sample rate of ADC = ADC input clock frequency / 20
6.3 ADC registers - ADSCR, ADR
ADC Registers - ADSCR, 8EH)
bit-7
bit-0
COM
CON
ADCSS1
ADCSS0
CH1
CH0
R
R
Read /Write:
R
R/W
R/W
R/W
R/W
R/W
-
-
Reset value:
0
0
0
0
0
0
*
*
COM: ADC conversion complete bit. This bit is a read only bit which is set each time conversion is completed. It is
cleared whenever ADSCR is written or ADCD is read. Reset clears this bit.
COM = 1 means conversion completed
COM = 0 means conversion not completed
CON: ADC continuous conversion bit. When set, the ADC will convert samples continuously and update the ADCD
register at the end of each conversion. When reset, only one conversion is allowed. Reset clears this bit.
CON = 1 means continuous mode
CON = 0 means signal mode
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ADCSS[1:0]: ADCSS channel select bit.
ADCSS1
ADCSS0
ADC_CLK
0
0
Fosc / 8 (below 20MHz)
0
1
Fosc / 16
1
0
Fosc / 32
1
1
Fosc / 64
CH[1:0] : ADC channel select bit. These bits are used to select one of the ADC channels.
CH1
CH0
Input select
0
0
CH0
0
1
CH1
1
0
CH2
1
1
CH3
Note: ADC_CLK frequency range 500KHz ~ 2.5MHz
ADC registers - ADC Data Register (ADCD, 8FH)
bit-7
bit-0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Read /Write:
R
R
R
R
R
R
R
R
Reset value:
0
0
0
0
0
0
0
0
ADC puts the result in the ADC Data Register (ADCD, 8FH) after each conversion. The ADCD register is read only register. The content of the ADCD will be 00H after reset.
Ex : Osc = 20MHz ADCSS[1:0] = 00
ADC input clock = 20/8 = 2.5MHz (Max)
One conversion time = 20 / 2.5MHz = 8us
ADC Max sample reta = 2.5MHz / 20 = 125KHz
Port 3 Configuration Register (P3CON, 9DH)
bit-7
bit-0
ADCE3
ADCE2
ADCE1
ADCE0
Unused
Unused
Unused
Unused
Read /Write:
R/W
R/W
R/W
R/W
-
-
-
-
Reset value:
0
0
0
0
*
*
*
*
Set ADCE3
= 1 enables the ADC function on pin P3.7/A15/ADC3,
ADCE3
= 0 disables the ADC function on pin P3.7/A15/ADC3,
Set ADCE2
= 1 enables the ADC function on pin P3.6/A14/ADC2,
ADCE2
= 0 disables the ADC function on pin P3.6/A14/ADC2,
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Set ADCE1
= 1 enables the ADC function on pin P3.5/A13/ADC1,
ADCE1
= 0 disables the ADC function on pin P3.5/A13/ADC1,
Set ADCE0
= 1 enables the ADC function on pin P3.4/A12/ADC0,
ADCE0
= 0 disables the ADC function on pin P3.4/A12/ADC0,
User may compare bits ADCE[3:0] of P3CON with bits CH[1:0] of ADSCR. User may consider P3CON as register for distinguish general purpose I/O function from other specific functions. After bit ADCE[3:0] been set, the corresponding I/O pin
will be assigned as high impedance input pins for signal input. On the other hand, the setting of CH[1:0] will select ADC
channels accordingly.
6.4 ADC Interrupt
The ADC module will generate one interrupt once one analog-to-digital conversion is completed. The ADC interrupt vector
locates at 4BH. There are three SFRs for configuring ADC interrupt: IP1, IE1 and IFR. To use ADC interrupt is the same
as to use other generic 8052 interrupts. That means using EADC of IE1 for enable/disable ADC interrupt, using PADC for
assign ADC interrupt priority. Whenever ADC interrupt occurs, ADCIF will be set to 1. After ADC interrupt subroutine (vector) been executed, ADCIF will be cleared to 0.
Interrupt Priority I Register (IP1, 0B9H)
bit-7
bit-0
Unused
Unused
Unused
Unused
PADC
Unused
Unused
Unused
Read /Write:
-
-
-
-
R/W
-
-
-
Reset value:
*
*
*
*
0
*
*
*
Interrupt priority bit PADC = 1 assigns high interrupt priority of ADC interrupt
Interrupt priority bit PADC = 0 assigns low interrupt priority of ADC interrupt
Interrupt Enable I Register (IE1, 0A9H)
bit-7
bit-0
Unused
Unused
Unused
Unused
EADC
Unused
Unused
Unused
Read /Write:
-
-
-
-
R/W
-
-
-
Reset value:
*
*
*
*
0
*
*
*
Interrupt enable bit EADC = 1 enables the ADC interrupt
Interrupt priority bit EADC = 0 disables the ADC interrupt
Interrupt Flag Register (IFR, 0AAH)
bit-7
bit-0
Unused
Unused
Unused
Unused
ADCIF
Unused
Unused
Unused
Read /Write:
-
-
-
-
R/W
-
-
-
Reset value:
*
*
*
*
0
*
*
*
Interrupt flag bit ADCIF will be set to 1 when ADC interrupt occurs. Interrupt flag bit ADCIF will be clear to 0 if ADC
Interrupt subroutine executed.
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7. LCD Driver
SM79108 incorporates an on-chip LCD driver which generates segment and common signals output according to the display data saved in LCD buffer registers (0E1H~0E7H) and incorporates segment and common drivers which can drive the
LCD panel directly.
The on chip LCD Driver has the following features:
1/4 duty (time multiplexing by 4) and 1/3 bias LCD segment driver
0.88 mA operation current (1.2 uA in power down mode)
56 bits of display data buffer
14 segment driver and 4 common driver outputs
A frames frequency can be selected
7.1 LCD Control register (LCDCON, 0DFH)
bit-7
bit-0
LCD_ON
LCD_EN
SEG
Unused
Unused
LS2
LS1
LS0
Read /Write:
R/W
R/W
R/W
-
-
R/W
R/W
R/W
Reset value:
0
0
0
*
*
0
0
0
LCDCON7~LCDCON0: LCD control register is used to control LCD driver operation
LCD_ON: LCD display bit
= 1:LCD display ON
= 0:LCD display OFF
LCD_EN: LCD enable bit
SEG: = 1:enables the LCD function on pin #PSEN/SEG4 and ALE/SEG5
= 0:no operation
LS[2:0]: Frequency prescaler select, determine the clock frequency of LCD driver, Fclk_lcd
LS2
LS1
LS0
PRESCALER SELECT
0
0
0
1
0
0
1
2
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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The clock frequency of LCD driver is obtained using the following formula:
Fclk_lcd = { [Fosc / 2 ] / 32 x PRESCALER }
The frame of LCD driver is determined as follows:
Frame = Fclk_lcd / 256
The typical range of Fframe is:
1026HZ ~ 8HZ at 16MHz (Fosc = 8MHz)
7.2 LCD Buffer Registers (LCDB0 ~ LCDB6, 0E1H ~ 0E7H)
Addressing Map of the LCD buffer registers is shown as following:
com3
com2
com1
com0
com3
com2
com1
com0
Mnemonic
address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LCDB0
E1H
SEG0
SEG0
SEG0
SEG0
SEG1
SEG1
SEG1
SEG1
LCDB1
E2H
SEG2
SEG2
SEG2
SEG2
SEG3
SEG3
SEG3
SEG3
LCDB2
E3H
SEG4
SEG4
SEG4
SEG4
SEG5
SEG5
SEG5
SEG5
LCDB3
E4H
SEG6
SEG6
SEG6
SEG6
SEG7
SEG7
SEG7
SEG7
LCDB4
E5H
SEG8
SEG8
SEG8
SEG8
SEG9
SEG9
SEG9
SEG9
LCDB5
E6H
SEG10
SEG10
SEG10
SEG10
SEG11
SEG11
SEG11
SEG11
LCDB6
E7H
SEG12
SEG12
SEG12
SEG12
SEG13
SEG13
SEG13
SEG13
7.3 Timing chart of LCD driver output
The 14 segment drivers and the 4 common drivers are 4-level outputs that switch between Vcc and the V1, V2
and Vss LCD driver voltages levels.
The output states are determined by the display data values which stored in the LCD buffer registers (0E1H
~0E7H).
The LCD driver's outputs are used to drive a 1/3-bias, 1/4-duty LCD panel.
7.4 The Output Control of Segments and Commons
Port 2 Configuration Register (P2CON) control COM0 ~ COM3 and SEG0 ~ SEG3 output; Port 0 Configuration
Register (P0CON) controls SEG6 ~ SEG13 outputs.
The bit 5 of LCD Control Register control the SEG4 and SEG5 outputs.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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Figure 6.1 Output states determination
Frame period
Vcc
V1
COM0 V2
VSS
Vcc
V1
COM1 V2
VSS
Vcc
V1
COM2 V2
VSS
Vcc
V1
COM3 V2
VSS
Vcc
V1
SEG0 V2
VSS
COM0 COM1 COM2 COM3
0
Vcc
V1
SEG1 V2
VSS
0
0
0
All segments are OFF
1
0
0
0
Segments connected to COM0
are ON
Vcc
V1
SEG2 V2
VSS
0
Vcc
V1
SEG3 V2
VSS
1
0
0
Segments connected to COM1
are ON
1
1
1
1
All segments are ON
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
TA
Operating temperature
-40
25
85
oC
TS
Storage temperature
-55
25
155
oC
Supply voltage
4.5
5.0
5.5
V
VCC5
Remarks
Ambient temperature under bias
VCC3
Supply voltage
3
3.3
3.6
Fosc 25
Oscillator Frequency
3.0
25
25
MHz For 5V, 3.3V application
V
Fosc 40
Oscillator Frequency
3.0
40
40
MHz For 5V application
DC Characteristics
(TA = -40 oC to 85 oC, Vcc = 5V)
Symbol
Parameter
Valid
Min.
Max.
Unit
Test Conditions
-0.5
1.0
V
Vcc = 5V
0
0.8
V
“
2.0
Vcc+0.5
V
“
70%Vcc Vcc+0.5
V
“
VIL1
Input Low Voltage
port 0,1,2,3,4,#EA
VIL2
Input Low Voltage
RES, XTAL1
VIH1
Input High Voltage
port 0,1,2,3,4,#EA
VIH2
Input High Voltage
RES, XTAL1
VOL1
Output Low Voltage
port 12,3,4
0.4
V
IOL = 1.6mA
VOL2
Output Low Voltage
port 0,2,port 3.0~port 3.3, ALE, #PSEN
0.4
V
IOL = 3.2mA
VOH1
Output High Voltage
port 1, 2, 3, ALE, #PSEN
2.4
V
IOH = -60uA
90%Vcc
V
IOH = -10uA
2.4
V
IOH = -800uA
90%Vcc
V
IOH = -80uA
VOH2
Output High Voltage
port 0
IIL
Logical 0 Input Current
port 1,2,4, port 3.0~port 3.3
-50
uA
Vin = 0.45V
ITL
Logical Transition Current
port 1,2,4, port 3.0~ port3.3
-650
uA
Vin = 2.0V
ILI
Input Leakage Current
port 0, #EA
10
uA
Vin = 0.45V
10
uA
Vin = 5V
90
Kohm
10
pF
Freq=1MHz, Ta=25oC
20
mA
Active mode, 16MHz
10
mA
Idle mode, 16MHz
100
uA
down mode, 16MHz
R RST
Reset Pulldown Resistor
C IO
Pin Capacitance
I CC
Power Supply Current
18
Vdd
Note1: Under steady state (non-transient) conditions, IOL must be externally
Limited as follows: Maximum IOL per port pin : 10mA
Maximum IOL per 8-bit port : port 0
:26mA
port 1,2,3 :15mA
Maximum total IOL for all output pins : 71mA
If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
Note2 : Minimum VCC for Power-down is 2V.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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Preliminary
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AC Characteristics
(16/25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Output=80pF)
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
T LLPL
T PLPH
T PLIV
T PXIX
T PXIZ
T AVIV
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YALH
T CHCL
T CLCX
T CLCH
T CHCX
T, TCLCL
Parameter
ALE pulse width
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instruction In
ALE low to #PSEN low
#PSEN pulse width
#PSEN low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN low to Address Float
#RD pulse width
#WR pulse width
#RD low to Valid Data In
Data Hold after #RD
Data Float after #RD
ALE low to Valid Data In
Address to Valid Data In
ALE low to #WR High or #RD low
Address Valid to #WR or #RD low
Data Valid to #WR High
Data Valid to #WR transition
Data hold after #WR
#RD low to Address Float
#WR or #RD high to ALE high
clock fall time
clock low time
clock rise time
clock high time
clock period
Valid
Cycle
RD/WRT
RD/WRT
RD/WRT
RD
RD
RD
RD
RD
RD
RD
RD
RD
WRT
RD
RD
RD
RD
RD
RD/WRT
RD/WRT
WRT
WRT
WRT
RD
RD/WRT
ICC Active mode test circuit
fosc=16MHz
Min. Typ. Max
115
43
53
240
53
173
177
0
87
292
10
365
365
302
0
145
590
542
178
197
230
403
38
73
Variable fosc
Unit
Min.
Typ.
Max
2xT - 10
nS
T - 20
nS
T - 10
nS
4xT - 10 nS
T - 10
nS
3xT - 15
nS
3xT - 10 nS
0
nS
T + 25 nS
5xT - 20 nS
10 nS
6xT - 10
nS
6xT - 10
nS
5xT - 10 nS
0
nS
2xT + 20 nS
8xT - 10 nS
9xT - 20 nS
3xT - 10
3xT + 10 nS
4xT - 20
nS
7xT - 35
nS
T - 25
nS
T + 10
nS
5 nS
72
T -10
T + 10 nS
nS
nS
nS
nS
1/fosc
nS
53
63
ICC
Vcc
Remarks
Vcc
VCC
RST
SM79108
(NC)
Clock Signal
PO
EA
8
XTAL2
XTAL1
VSS
Specifications subject to change without notice,contact your sales representatives for the most recent information.
19/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
20%Vdd-0.1V
0.45V
TCLCX
TCHCL
TCHCX
TCLCH
Tm.I External Program Memory Read Cycle
TPLPH
#PSEN
ALE
TLHLL
TLLPL
TAVLL
TPXIZ
TPLAZ
TLLAX
TPXIX
TPLIV
Instruction. IN
A0 - A7
PORT 0
A0 - A7
TAVIV
Tm.II
A8 - A15
A8 - A15
PORT 2
External Data Memory Read Cycle
#PSEN
TYHLH
ALE
TLLDV
TRLRH
TLLYL
#RD
PORT 0
TAVLL
TLLAX
TRHDZ
TRLDV
TRLAZ
A0 - A7
from Ri or DPL
TRHDX
A0 - A7
from PCL
DATA IN
INSTRL
IN
TAVYL
TAVDV
PORT 2
A8 - A15 from PCH
P2.0 - P2.7 or A8 - A15 from DPH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
20/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
Tm.III External Data Memory Write Cycle
#PSEN
TYHLH
TLHLL
ALE
TLLYL
TWLWH
TAVLL
#WR
TLLAX
TQVWX
TQVWH
A0-A7
from Ri or DPL
PORT 0
TWHQX
A0-A7
From PCL
DATA OUT
INSTRL
IN
TAVYL
A8-A15 from PCH
P2.0-P2.7 or A8-A15 from DPH
PORT 2
Application Reference
Valid for SM79108
X’tal
3MHz
6MHz
12MHz
16MHz
C1
30pF
30pF
30pF
30pF
C2
30pF
30pF
30pF
30pF
R
open
open
open
open
X’tal
20MHz
25MHz
33MHz
40MHz
C1
22pF
15pF
5pF
2pF
C2
22pF
15pF
5pF
2pF
R
open
62KΩ
6.8KΩ
4.7KΩ
XI
NOTE: Oscillation circuit may differs with different crystal or ceramic
resonator in higher oscillation frequency which was due to each
X'tal
SM79108
crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator manufacturer
R
for appropriate value of external components.
X2
C1
C2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
21/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
40L 600mil PDIP Information
E
D
S
E1
A2
A1
C
A
L
e1
B1
eA
B
a
Note:
1. Dimension D Max & include mold flash or tie bar
burrs.
2. Dimension E1 does not include inter lead flash.
3. Dimension D & E1 include mold mismatch and are
determined at the mold parting line.
4. Dimension B1 does not include dambar protrusion/
intrusion.
5. Controlling dimension is inch.
6. General appearance spec. should base on final visual
inspection spec.
Symbol
A
A1
A2
B
B1
C
D
E
E1
e1
L
a
eA
S
Dimension in inch
minimal/maximal
- / 0.210
0.010 / 0.150 / 0.160
0.016 / 0.022
0.048 / 0.054
0.008 / 0.014
- / 2.070
0.590 / 0.610
0.540 / 0.552
0.090 / 0.110
0.120 / 0.140
0 / 15
0.630 / 0.670
- / 0.090
Dimension in mm
minimal/maximal
- / 5.33
0.25 / 3.81 / 4.06
0.41 / 0.56
1.22 / 1.37
0.20 / 0.36
- / 52.58
14.99 / 15.49
13.72 / 14.02
2.29 / 2.79
3.05 / 3.56
0 / 15
16.00 / 17.02
- / 2.29
Specifications subject to change without notice,contact your sales representatives for the most recent information.
22/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
44L Plastic Chip Carrier (PLCC)
L
6
7
E
HE
GE
y
D
A2
HD
A1
A
C
b1
θ
e
b
Symbol
A
A1
A2
b1
b
C
D
E
e
GD
GE
HD
HE
L
θ
GD
Note:
1. Dimension D & E does not include inter lead flash.
2. Dimension b1 does not include dambar protrusion/
intrusion.
3. Controlling dimension: Inch
4. General appearance spec. should base on final visual
inspection spec.
y
Dimension in inch
minimal/maximal
- / 0.185
0.020 / 0.145 / 0.155
0.026 / 0.032
0.016 / 0.022
0.008 / 0.014
0.648 / 0.658
0.648 / 0.658
0.050 BSC
0.590 / 0.630
0.590 / 0.630
0.680 / 0.700
0.680 / 0.700
0.090 / 0.110
- / 0.004
/
Dimension in mm
minimal/maximal
- / 4.70
0.51 / 3.68 / 3.94
0.66 / 0.81
0.41 / 0.56
0.20 / 0.36
16.46 / 16.71
16.46 / 16.71
1.27 BSC
14.99 / 16.00
14.99 / 16.00
17.27 / 17.78
17.27 / 17.78
2.29 / 2.79
- / 0.10
/
Specifications subject to change without notice,contact your sales representatives for the most recent information.
23/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
44L Plastic Quad Flat Package
C
L
L1
S
θ2
e
R1
D2 D1 D
Gage Plane
0.25 mm
b
θ3
A2
R2
A1
E2
E1
E
A
e1
seating plane
e
Note:
Dimension D1 and E1 do not include mold protrusion.
Allowance protrusion is 0.25mm per side.
Dimension D1 and E1 do include mold mismatch
and are determined datum plane.
Dimension b does not include dumber protrusion.
Allowance dumber protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material
condition. Dumber cannot be located on the lower
radius or the lead foot.
C
Symbol
A
A1
A2
b
c
D
D1
D2
E
E1
E2
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
C
Dimension in Inch
minimal/maximal
- / 0.100
0.006 / 0.014
0.071 / 0.087
0.012 / 0.018
0.004 / 0.009
0.520 BSC
0.394 BSC
0.315
0.520 BSC
0.394 BSC
0.315
0.031 BSC
0.029 / 0.041
0.063
0.005 / 0.005 / 0.012
0.008 / 0° / 7°
0° / 10° REF
7° REF
0.004
Dimension in mm
minimal/maximal
- / 2.55
0.15 / 0.35
1.80 / 2.20
0.30 / 0.45
0.09 / 0.20
13.20 BSC
10.00 BSC
8.00
13.20 BSC
10.00 BSC
8.00
0.80 BSC
0.73 / 1.03
1.60
0.13 / 0.13 / 0.30
0.20 / as left
as left
as left
as left
0.10
Specifications subject to change without notice,contact your sales representatives for the most recent information.
24/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
eMCU Writer List
Company
Advantech
7F, No.98, Ming-Chung Rd.,
Shin-Tien City, Taipei, Taiwan,
ROC
Web site:
http://www.aec.com.tw
Hi-Lo
4F, No. 20, 22, LN, 76,
Rui Guang Rd., Nei Hu, Taipei,
Taiwan, ROC.
Web site:
http://www.hilosystems.com.tw
Leap
6th F1-4, Lane 609,
Chunghsin Rd., Sec. 5, Sanchung,
Taipei Hsien, Taiwan, ROC
Web site:
http://www.leap.com.tw
Xeltek Electronic Co., Ltd
338 Hongwu Road, Nanjing, China
210002
Web site:
http://www.xeltek-cn.com
Contact info
Tel:02-22182325
Fax:02-22182435
E-mail:
[email protected]
Programmer Model Number
LabTool - 48 (1 * 1)
LabTool - 848 (1*8)
* Note: Not yet, about 3/E’03
Tel:02-87923301
Fax:02-87923285
E-mail:
[email protected]
All - 11 (1*1)
Gang - 08 (1*8)
* Note: Not yet, about 3/E’03
Tel:02-29991860
Fax:02-29990015
E-mail:
[email protected]
SU - 2000 (1*8)
* Note: Not yet, about 3/E’03
Tel:+86-25-4408399, 4543153-206
E-mail:
[email protected],
[email protected]
Superpro/2000 (1*1)
Superpro/680 (1*1)
Superpro/280 (1*1)
Superpro/L+(1*1)
* Note: Not yet, about 3/E’03
Specifications subject to change without notice,contact your sales representatives for the most recent information.
25/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
SM79108
Preliminary
January 2003
Feedback / Inquiry:
To
Attn
Fax
Tel
:SyncMOS Technologies, Inc.
:MKT / Customer Service Dept.
:886-3-579-2960
:886-3-578-0493
:886-3-579-2987
:886-3-578-3344 # 2667
From
:
Company :
Dept, Section :
Position Title :
Inquiry Date :
Ref No :
Description:
Specifications subject to change without notice,contact your sales representatives for the most recent information.
26/26
Preliminary
Ver 1.0
SM79108 01/03