ETC SM89S16R1

SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Product List
Feature
SM89S16R1L25, 25MHz 64KB internal flash MCU
SM89S16R1C25, 25MHz 64KB internal flash MCU
SM89S16R1C40, 40MHz 64KB internal flash MCU
z
z
Working Voltage: 3.3V or 5.0V.
80C51 Central Processor Unit (CPU).
z
64K x 8 bits on chip flash memory.
General Description
z
1024 x 8 bits RAM, expandable externally to
z
64KB.
Two standard 16-bits timers/counters
z
An additional 16-bits timer/counter coupled to
The SM89S16R1 is a single-chip 8-bits microcontroller manufactured in an advanced CMOS
process with on chip flash memory. It supports a
derivative of the 80C51 microcontroller family.
The SM89S16R1 has the same instructions set as
the 80C51.
The SM89S16R1 contains a 64K x 8 bits on chip
program flash, a volatile 1024 x 8 bits data RAM,
four 8-bits I/O ports, one 4-bits I/O port, two
16-bits timer/event counters, and an additional
16-bits timer coupled to capture and compare
latches, a two-priority-level, nested interrupt
structure, two PWM clock outputs, one serial
interfaces (UART bus). For system that requires
extra capability the SM89S16R1 can be expanded
using standard TTL and LVTTL compatible
memory and logic.
In addition, The SM89S16R1 has two software
selectable modes of power saving – IDLE mode
and POWER-DOWN mode. The IDLE mode
freezes the CPU while allowing the RAM, timer,
serial ports, and interrupt system to continue
functioning. The POWER-DOWN mode saves the
RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.
a capture and compare register.
z
Two 8-bits / 5-bits resolution
Pulse-Width-Modulation (PWM) outputs
z
Four 8-bits I/O ports.(For PDIP package)
z
Four 8-bits I/O ports plus one 4-bits I/O port.
z
(For PLCC or QFP package)
Full-duplex UART
z
z
8 interrupt sources with 2 priority levels
Extended temperature range (-40℃ to +85℃)
z
z
Software enable/disable ALE output pulse
Wake-up from POWER-DOWN mode by
INT0/INT1, RTCI or H/W RESET.
z
RTC (Real Time Clock) function.
z
Four channels 6-bits Analog to Digital
Converter (ADC).
Ordering Information
SM89S16R1ihhk
yymmv
i: process identifier {L=3.0V~3.6V,C=4.5V~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
yy: year mm: month
v: version identifier { , A, B, ...}
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-578-3344 #2667
886-3-579-2987
FAX: 886-3-5792960
886-3-5780493
Specifications subject to change without notice contact your sales representatives for the most recent information.
1
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Package Spec.
Package
44L PQFP
44L PLCC
40L PDIP
Pin / PAD
Figure 1
Figure 2
Figure 3
Frequency
25 MHz at 3.3V and 40MHz at 5V
25 MHz at 3.3V and 40MHz at 5V
25 MHz at 3.3V and 40MHz at 5V
Pin Configuration
19 P2.1/A9
VDD 38
18 P2.0/A8
P4.2 39
17 P4.0
T2/P1.0 40
16 VSS
T2EX/P1.1 41
15 XTAL1
6
7
8
9
10
11
T1/P3.5
5
T0/P3.4
4
TXD/P3.1
3
P4.3
2
RXD/P3.0
1
#INT1/P3.3
12 P3.6/#WE
#INT0/P3.2
PWM0/P1.4 44
RES
13 P3.7/#RD
P1.7
P1.3 43
P1.6
14 XTAL2
PWM1/P1.5
P1.2 42
P1.0/T2
P4.2
VDD
P0.0/AD0
P0.1/AD1
P0.3/AD3
P1.1/T2EX
P0.2/AD2
P1.2
40
39 P0.4/AD4
P1.6
8
38 P0.5/AD5
P1.7
9
37 P0.6/AD6
RES
10
36 P0.7/AD7
RXD/P3.0
11
35 #EA
P4.3
12
34 P4.1
TXD/P3.1
13
33 ALE/X32OUT
#INT0/P3.2
14
32 #PSEN/X32IN
#INT1/P3.3
15
31 P2.7/A15/ADC3
T0/P3.4
16
30 P2.6/A14/ADC2
T1/P3.5
17
29 P2.5/A13/ADC1
18
19
20
21
22
23
24
25
26
27
28
ADC0/A12/P2.4
AD0/P0.0 37
41
A11/P2.3
20 P2.2/A10
42
A10/P2.2
AD1/P0.1 36
43
A9/P2.1
21 P2.3/A11
44
A8/P2.0
22 P2.4/A12/ADC0
AD2/P0.2 35
1
P4.0
AD3/P0.3 34
2
VSS
23
P1.4/PWM0
P2.6/A14/ADC2
24
P2.5/A13/ADC1
P2.7/A15/ADC3
25
3
XTAL1
26
4
XTAL2
27
5
7
#RD/P3.7
28
#PSEN/X32IN
P4.1
29
ALE/X32OUT
#EA
30
6
PWM1/P1.5
#WE/P3.6
31
P0.7/AD7
P0.5/AD5
32
P0.6/AD6
P0.4/AD4
33
P1.3
Figure 2 44L PLCC Package
Figure 1 44L PQFP Package
P2.5/A13/ADC1
P2.4/A12/ADC0
P2.3/A11
26
25
24
23
22
15
16
17
18
19
T1/P3.5
#WE/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
20
21
P2.0/A8
P2.6/A14/ADC2
27
14
T0/P3.4
P2.1/A9
P2.7/A15/ADC3
28
13
#INT1/P3.3
P2.2/A10
#PSEN/X32IN
29
12
#INT0/P3.2
30
11
ALE/X32OUT
31
10
RXD/P3.0
TXD/P3.1
32
9
RES
#EA
33
8
P1.7
P0.7/AD7
34
7
P1.6
P0.6/AD6
35
6
PWM1/P1.5
P0.5/AD5
P0.3/AD3
36
5
P0.4/AD4
P0.2/AD2
37
4
P1.3
PWM0/P1.4
P0.0/AD0
38
3
P1.2
P0.1/AD1
39
2
T2EX/P1.1
T2/P1.0
1
40
VDD
Figure 3 40L PDIP Package
Specifications subject to change without notice contact your sales representatives for the most recent information.
2
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Block Diagram
TxD
PWM0
PWM1
(3)
(1)
(1)
UART
EA
RD
WR
Timer0
Timer1
Timer2
(3)
(3)
Ext-RAM
FLASH
64Kx8
256x8
768x8
C51
CORE
CPU
ALE
PSEN
Int-RAM
(2)(2)
(2)
ADC
PWM
Parallel I/O ports & Ext. Bus
INT
Port0
RTC
Port4
P0
INT1
(4)
X32IN
INT0
X32OUT
INT1
(4)
P4
(3)
Port3
P3
(3)
Port2
P2
(3)
Port1
P1
(3)
INT0
T2
T2EX
T1
T0
RES
Notes: (1): Alternate function of P1
(2): Alternate function of P2
(3): Alternate function of P3
(4): Alternate function of ALE, PSEN
(2)
iBUS
PDWU
(3) (3) (1) (1)
ADC0
ADC1
ADC2
ADC3
RxD
Xtal1
Xtal2
(3)
Specifications subject to change without notice contact your sales representatives for the most recent information.
3
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Pin Description
PDIP 40 pin
PQFP 44 Pin
PLCC 44 pin
VDD
MNEMONIC
40
38
44
P0.0 – P0.7
39,38,37,36
35,34,33,32
37,36,35,34
33,32,31,30
43,42,41,40
39,38,37,36
P1.0 – P1.7
1,2,3,4,
5,6,7,8
40,41,42,43,
44,1,2,3
2,3,4,5,
6,7,8,9
RST
9
4
10
P2.0 – P2.7
21,22,23,24,
25,26,27,28
18,19,20,21
22,23,24,25
24,25,26,27,
28,29,30,31
Names and Functions
Power supply:
+5V or +3.3V power supply pin during normal operations
and power saving modes.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins
that have 1s written to them become floating and can be
used as high- impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses
to external program and data memory. In this application, it
uses strong internal pull-ups when emitting 1s.
Port Pin
Alternative function
P0.0
AD0
P0.1
AD1
P0.2
AD2
P0.3
AD3
P0.4
AD4
P0.5
AD5
P0.6
AD6
P0.7
AD7
Port 1:
An 8-bits bidirectional I/O port with internal pull-ups on all
pins. Port 1 pins that have 1s written to them are pulled high
by the internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will source current
because of the internal pull-ups. (See DC Electrical
Characteristics: IIL).
Port Pin
Alternative function
P1.0
T2: TIMER2 clock output
P1.1
T2EX: TIMER2 reload/capture DIR.
P1.4
PWM0: PWM channel 0 output
P1.5
PWM1: PWM channel 1 output
Reset:
A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal resistor to
VSS permits a power-on reset using only an external
capacitor to VCC.
Port 2:
Port 2 is an 8-bits bidirectional I/O port with internal
pull-ups. Port 2 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will
source current because of the internal pull-ups. (See DC
Electrical Characteristics: IIL). Port 2 emits the high-order
address byte during fetches from external program memory
and during accesses to external data memory that uses
16-bits addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During
accesses to external data memory that uses 8-bits addresses
(MOV @Ri), port 2 emits the contents of the P2 special
function register.
Port Pin
Alternative function
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12/ADC0
P2.5
A13/ADC1
P2.6
A14/ADC2
P2.7
A15/ADC3
Specifications subject to change without notice contact your sales representatives for the most recent information.
4
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
PDIP 40 pin
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
PQFP 44 Pin PLCC 44 pin
Names and Functions
P3.0 – P3.7
10,11,12,13
14,15,16,17
5,7,8,9,
10,11,12,13
11, 13,14,15,
16,17,18,19
ALE/X32OUT
30
27
33
#PSEN/X32IN
29
26
32
#EA
31
29
35
X1
19
15
21
X2
18
14
20
MNEMONIC
Port 3:
Port 3 is an 8-bits bidirectional I/O port with internal
pull-ups. Port 3 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will
source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also serves the special features.
Port Pin
Alternative function
P3.0
RxD UART input
P3.1
TxD UART output
P3.2
#EX0 external interrupt 0
P3.3
#EX1 external interrupt 1
P3.4
T0: Timer 0 external input
P3.5
T1: Timer 1 external input
P3.6
#WR External data memory write strobe
P3.7
#RD External data memory read strobe
Address Latch Enable:
Output pulse for latching the low byte of the address during
an access to external memory. In normal operation, ALE is
emitted twice every machine cycle, and can be used for
external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. Setting
SFR SCONF.0 can disable ALE. With this bits set, ALE will
be active only during a MOVX instruction.
X32OUT: The 32.768KHz crystal output for RTC function.
Program Store Enable:
The read strobe to external program memory. When
executing code from the external program memory, #PSEN
is activated twice each machine cycle, except that two
#PSEN activations are skipped during each access to
external data memory. #PSEN is not activated during
fetches from internal program memory.
X32IN: The 32.768KHz crystal input for RTC
function.
External Access Enable:
#EA must be externally held low to enable the device to
fetch code from external program memory locations. If #EA
is held high, the device executes from internal program
memory.
Crystal 1:
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
Specifications subject to change without notice contact your sales representatives for the most recent information.
5
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
SFR Mapping
The special function register of SM89S16R1 fall into the following categories
z
z
C51 CORE register: ACC, B, DPL, DPH, PSW, SP
I/O ports: P0,P1, P2, P3, P4
z
Timer/Counter register: T2CON, T2MOD, TCON, TMOD, TH0, TH1, TH2, TL0, TL1, TL2, RCAP2L,
RCAP2H
z
z
UART I/O register: SBUF, SCON
Power and system control register: PCON, SCONF
z
Interrupt system register: IP, IE, IP1, IE1, IFR
z
PWM output register: PWMC0, PWMC1, PWMD0, PWMD1, P1CON
z
z
ADC register: ADCSC, ADCD, P2CON
RTC register: RTCC, RTCS
z
LED Driving Capability Control: LEDP0, LEDP1, LEDP2, LEDP3, LEDP4
Table 1 SFR Map
$FF
$F8
$F0
B
0000 0000
$F7
$EF
$E8
$E0
$D8
$D0
$C8
ACC
0000 0000
P4
xxxx 1111
PSW
0000 0000
T2CON
0000 0000
$E7
$DF
T2MOD
xxxx xx00
RCAP2L
0000 0000
PWMC0
0000 0000
RCAP2H
0000 0000
PWMC1
0000 0000
TL2
0000 0000
$D7
TH2
0000 0000
$CF
$C7
$C0
$B8
$B0
$A8
$A0
$98
$90
$88
$80
IP
0000 0000
P3
1111 1111
IE
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
IP1
0000 0000
SCONF
0000 0000
PWMD0
0000 0000
IE1
0000 0000
RTCS
0000 0000
SBUF
xxxx xxxx
TMOD
0000 0000
SP
0000 0111
$B7
PWMD1
0000 0000
$AF
IFR
0000 0000
RTCC
0000 0000
LEDP0
0000 0000
TL0
0000 0000
DPL
0000 0000
$BF
$A7
P1CON
0000 0000
LEDP1
0000 0000
TL1
0000 0000
DPH
0000 0000
P2CON
0000 0000
LEDP2
0000 0000
TH0
0000 0000
$9F
LEDP3
0000 0000
TH1
0000 0000
LEDP4
0000 0000
ADCSC
0000 0000
$97
ADCD
0000 0000
PCON
0000 0000
Specifications subject to change without notice contact your sales representatives for the most recent information.
6
SM89S16R1 V1.0 JANUARY 2005
$8F
$87
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Table 2 : All SFR list (8051, I/O, Timer, UART, System, Interrupt, RAM Control, PWM, RTC, ADC)
Symbol
Description
Direct
Bit 7
ACC*
B
SP
PSW*
DPTR
DPH
DPL
Accumulator
B register
Stack Pointer
Process Status
Data Pointer (2 Bytes)
Data Pointer High
Data Pointer Low
E0
F0
81H
D0H
P0*
P1*
P2*
P3*
P4*
P1CON
P2CON
Port 0
Port 1
Port 2
Port 3
Port 4
P1 Control
P2 Control
80H
90H
A0H
B0H
D8H
9BH
9CH
P0.7
P1.7
P2.7
P3.7
P0.6
P1.6
P2.6
P3.6
ADC3E
TCON*
THL0
TH0
TL0
THL1
TH1
TL1
T2CON*
T2MOD
RCAP2HL
RCAP2H
RCAP2L
THL2
TH2
TL2
Timer Control register
Timer 0 (2 Bytes)
Timer 0 High
Timer 0 Low
Timer 1 (2 Bytes)
Timer 1 High
Timer 1 Low
Timer 2 Control
Timer 2 Mode
Reload/Capture (2 bytes)
RCAP2 High
RCAP2 Low
Time 2 (2 bytes)
Timer 2 High
Time 2 Low
88H
TF1
ADC2E
ADC1E
ADC0E
TIMER / Counter
TF1
TF0
TR0
CBH
CAH
00H
00H
CDH
CCH
00H
00H
SCON*
SBUF
UART Control
UART Buffer
98H
99H
SM0
ADSCR
ADCD
ADC status & control
ADC data register
8EH
8FH
COM
AD.5
RTCS
RTCC
RTC Status
RTC Control
A1H
A2H
RTCen
Int_sel.1
PWMC0
PWMC1
PWMD0
PWMD1
PWM 0 Control
PWM 1 Control
PWM 0 Data
PWM 1 Data
D3H
D4H
B3H
B4H
PCON
SCONF
Power Control register
System Control
87H
BFH
SMOD
IE*
IE1
IFR
IP*
IP1
Interrupt Enable
Interrupt Enable 1
Interrupt Flag 1
Interrupt Priority
Interrupt Priority 1
A8H
A9H
AAH
B8H
B9H
EA
LEDP 0
LEDP 1
LEDP 2
LEDP 3
LEDP 4
LED output in P0
LED output in P1
LED output in P2
LED output in P3
LED output in P4
92H
93H
94H
95H
96H
CY
Bit 6
Bit 5
8051 Core
AC
F0
Bit 4
RS1
Bit 3
RS0
Bit 2
Bit 1
OV
Bit 0
RESET
P
00H
00H
07H
00H
82H
83H
00H
00H
I/O PORT
P0.5
P1.5
P2.5
P3.5
P0.4
P1.4
P2.4
P3.4
P0.3
P1.3
P2.3
P3.3
P4.3
PWM1E
P0.2
P1.2
P2.2
P3.2
P4.2
PWM0E
P0.1
P1.1
P2.1
P3.1
P4.1
-
P0.0
P1.0
P2.0
P3.0
P4.0
-
FFH
FFH
FFH
FFH
XFH
00H
00H
IE1
IT1
IE0
IT0
00H
8CH
8AH
00H
00H
8DH
8BH
C8H
C9H
00H
00H
00H
X0H
TF2
PWMD.7
PWMD.7
EXF2
RCLK
UART
SM2
SM1
TCLK
REN
A/D Converter
ADCSS1
ADCSS0
CON
AD.4
AD.3
AD.2
Real Timer Clock (RTC)
Stable
Sec.5
Sec.4
Int_sel.0
Min.5
Min.4
PWM output
PWMD.6
PWMD.6
PWMD.5
PWMD.5
PWMD.4
PWMD.4
EXEN2
TR2
TB8
RB8
CH1
AD.1
CH0
AD.0
Sec.3
Min.3
PWMD.3
PWMD.3
CT2
T2OE
TI
CPRL2
DCEN
RI
00H
XXH
00H
00H
Sec.2
Min.2
Sec.1
Min.1
Sec.0
Min.0
00H
00H
PBS
PBS
PFS1
PFS1
PFS0
PFS0
PWMD.2
PWMD.2
PWMD.1
PWMD.1
PWMD.0
PWMD.0
00H
00H
00H
00H
PD
OME
IDLE
ALEI
00H
00H
ET0
EX0
PT0
PX0
00H
00H
00H
00H
00H
Power and System
PDWUE
Interrupt system
ET2
ES0
PT2
PS0
ET1
EADC
ADCIF
PT1
PADC
EX1
ERTC
RTCIF
PX1
PRTC
LED Driving Capability Control
00H
00H
00H
00H
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
7
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Target Spec.
Absolute Rating
Symbol
TA
TS
VCC5
VCC3.3
Fosc 25
Fosc 40
Description
Operating temperature
Storage temperature
Supply voltage
Supply voltage
Oscillator Frequency
Oscillator Frequency
Min.
-40
-55
4.5
3.0
Typ.
25
25
5.0
3.3
Max.
85
155
5.5
3.6
25
40
Unit.
℃
℃
V
V
MHz
MHz
Remarks
Ambient temperature under bias
Damage to devices could occur
For 3.3V application
For 5.0V application
DC Characteristic
VCC = 5V (±10%), VSS=0V TA= -40℃ to 85℃
SYMBOL
VCC
Supply Voltage
ICC
Supply current operating
IID
Supply current IDLE Mode
IPD
TEST
CONDITIONS
PARAMETER
LIMITS
MIN
UNIT
MAX
4.5
See notes 1
fCLK = 12MHz VCC = 5.5V
See note 2
fCLK = 12MHz VCC = 5.5V
5.5
V
20
mA
6.5
mA
Supply current Power-Down MODE
RTC Disable
See note 3；VCC (= 5.5V)
30
µA
Supply current Power-Down MODE
RTC Enable
See note 3；VCC (= 5.5V)
80
µA
0.8
0.8
Vcc+0.5
Vcc+0.5
-75
-650
±10
V
V
V
V
µA
µA
µA
0.45
0.45
V
V
V
V
kΩ
pF
INPUT
VIL1
VIL2
VIH1
VIH2
IIL
ITL
ILI
Input LOW voltage, P0, P1, P2, P3, P4, /EA
Input LOW voltage, RES, XTAL1
Input HIGH voltage, P0, P1, P2, P3, P4, /EA
Input HIGH voltage, RES, XTAL1
Input current LOW level Port 1,2,3,4
Transition current High to Low Port 1,2,3,4
Input leakage current ,Port 0
VOL1
VOL2
VOH1
VOH2
RRST
CIO
Output LOW voltage, Port 0,ALE, /PSEN
Output LOW voltage, Port 1, 2, 3, 4
Output High voltage Port0 ALE, /PSEN
Output High voltage Port 1,2,3,4
Internal RESET pull-down resistor
Pin capacitance
-0.5
0
2.0
70%VCC
VIN = 0.45V
VIN = 2.0 V
0.45V < VIN < VCC-0.3V
OUTPUT
IOL = 8mA，VCC=5.0V
IOL = 6.5mA，VCC =5.0V
IOH = -800uA，VCC =5.0V
IOH = -60µA，VCC =5.0V
2.4
2.4
50
300
10
Test freq=1MHz, TA=25℃
VCC = 3.3V (±10%), VSS=0V , TA= -40℃ to 85℃
SYMBOL
VCC
Supply Voltage
ICC
Supply current operating
IID
Supply current IDLE Mode
IPD
TEST
CONDITIONS
PARAMETER
LIMITS
MIN
3.0
See note 1
fCLK = 12MHz VCC = 3.6V
See note 2
fCLK = 12MHz VCC = 3.6V
UNIT
MAX
3.6
V
10
mA
5
mA
Supply current Power-Down MODE
RTC Disable
See note 3；VCC (= 3.6V)
20
µA
Supply current Power-Down MODE
RTC Enable
See note 3；VCC (= 3.6V)
30
µA
INPUT
Specifications subject to change without notice contact your sales representatives for the most recent information.
8
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
VIL1
VIL2
VIL3
Input LOW voltage, P0, P1, P2, P3, P4, /EA
Input LOW voltage, RST
Input LOW voltage, XTAL1
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VIH1
Input HIGH voltage, P0, P1, P2, P3, P4, /EA
VCC = 3.6V
VIH2
Input HIGH voltage, RST
VCC = 3.6V
VIH3
Input HIGH voltage, XTAL1
IIN1
Input current LOW level Port 1,2,3,4
ITL
Transition current High to Low Port 1,2,3,4
ILI
Input leakage current P0, /EA
VOL1
VOL2
VOH1
VOH2
ISK1
ISK2
ISR1
ISR2
RRST
CIO
Output LOW voltage, Port 0,ALE, /PSEN
Output Low voltage Port 1,2,3,4
Output High voltage Port0, ALE, /PSEN
Output High voltage Port 1,2,3,4
Sink Current Port 1, 2, 3, 4
Sink Current Port 0,ALE, /PSEN
Source Current Port 1, 2, 3, 4
Source Current Port 0,ALE, /PSEN
Internal RESET pull-down resistor
Pin capacitance
VCC = 3.6V
VCC = 3.0V ~3.6V,
VIN = 0.45V.
See note 4
VCC = 3.6V, VIN = 2.0 V
VCC = 3.0V ~3.6V,
0.45V<VIN<VCC
OUTPUT
IOL = 6mA，VCC =3.3V
IOL = 5mA，VCC =3.3V
IOH =-300uA，VCC =3.3V
IOH =-20µA，VCC =3.3V
VCC = 3.3V, VIN = 0.4 V
VCC = 3.3V, VIN = 0.4 V
VCC = 3.3V, VIN = 2.4 V
VCC = 3.3V, VIN = 2.4 V
0
0
0
0.6 VCC
-0.4
0.6 VCC
-0.4
0.8 VCC
0.2 VCC -0.2
0.2 VCC -0.2
0.2 VCC -0.2
V
V
V
VCC + 0.2
V
VCC + 0.2
V
VCC + 0.2
V
-10
50
µA
-75
400
µA
-10
10
µA
0.4
0.4
V
V
V
V
mA
mA
uA
mA
kΩ
pF
2.4
2.4
50
Test freq=1MHz, TA=25℃
6
8
-80
-8
300
10
NOTES FOR DC ELECTRICAL CHARACTERISTICS
1.
The operating supply current is measured with all output disconnected;
XTAL1 driven with tr = tf = 5ns; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect;
/EA=RST=Port0=VDD;
2.
The IDLE MODE supply current is measured with all output pins disconnected;
XTAL1 driven with tr = tf = 5ns; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect;
/EA=Port0=VDD;
3.
The POWER-DOWN MODE supply current is measured with all output pins disconnected;
VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect; /EA= Port0=VDD;
4.
Port 1, 2, 3, and 4 sources a transition current when they are being externally driven from HIGH to LOW. The transition current reaches its
maximum value when VIN is approximately 2V.
5.
Capacities loading on port 0 and 2 may cause spurious noise to be superimposed on VOL of ALE and port 1, 3, and 4. The noise is due to external
bus capacitance discharging into port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases
(capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt
Trigger, or use an address latch with a Schmitt trigger STROBE input.
Specifications subject to change without notice contact your sales representatives for the most recent information.
9
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
AC Characteristic
VCC=3.3V±10%, VSS=0V, tclk min = 1/ fmax(maximum operating frequency)
TA= -40℃ to +85℃
CL=100pF for Port0, ALE and /PSEN; CL=80pF for all other outputs unless otherwise specified.
Symbol
FIGURE
PARAMETER
MIN
MAX
UNIT
40(1)
20
20
3.33
10
10
-
ns
ns
ns
ns
ns
Ns
MIN
MAX
UNIT
3.0
2tCLK-40
tCLK-40
tCLK-30
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External Clock drive into XTAL1
tCLK
4
tCLKH
4
tCLKL
4
tCLKR
4
tLLIV
4
tCYC
4
NOTES:
1. Operating at 25MHz.
Xtal1 Period
Xtal1 HIGH time
Xtal1 LOW time
XTAL1 rise time
XTAL1 fall time
Controller cycle time = tCLK / 4
Symbol
FIGURE
PARAMETER
1/tCLK
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
7
7
7
7
7
7
7
7
7
7
7
7
System clock frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE LOW to valid instruction in
ALE LOW to /PSEN LOW
/PSEN pulse width
/PSEN LOW to valid instruction in
Input instruction hold after /PSEN
Input instruction float after /PSEN
Address to valid instruction in
/PSEN low to address float
tAVLL
tLLAX
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
8,9
8,9
8
9
8
8
8
8
8
8,9
8,9
9
9
9
8
8,9
Address valid to ALE LOW
Address hold after ALE LOW
/RD pulse width
/WR pulse width
/RD LOW to valid data in
Data hold after /RD
Data float after /RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to /RD or /WR LOW
Address valid to /WR or /RD LOW
Data valid to /WR transition
Data before /WR
Data hold after /WR
/RD LOW to address float
/RD or /WR HIGH to ALE HIGH
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
10
10
10
10
10
Serial port clock time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Program Memory
4tCLK-100
tCLK-30
3tCLK-45
3tCLK-105
0
tCLK -25
5tCLK-105
10
Data Memory
tCLK-40
tCLK-35
6tCLK-100
6tCLK-100
0
tCLK+40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10tCLK-133
ns
ns
ns
ns
ns
5tCLK-165
0
3tCLK-50
4tCLK-130
tCLK-50
7tCLK-150
tCLK-50
tCLK-40
2tCLK-70
8tCLK-150
9tCLK-165
3tCLK+50
UART
12tCLK
10tCLK-133
2tCLK-117
0
Specifications subject to change without notice contact your sales representatives for the most recent information.
10
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
tCLKH
tCLKR
VIH1
tLLIV
0.8V
tCLKL
tCLK
Figure 4 External Clock Drive waveform
2.0V
2.0V
Test Points
0.8V
0.8V
Notes:
AC inputs during testing are driven at 2.4V for logic
“HIGH” and 0.45V for logic “LOW”. Timing
measurements are at 2.0V for logic “HIGH” and 0.8V
Figure 5 AC Testing Input/Output
Floating
2.0V
2.0V
0.8V
0.8V
Notes:
The float state is define as the point which PORT 0
pins sinks 3.2mA or source 400µA at the voltage
test level.
Figure 6 AC Testing, Floating Waveform
t LHLL
ALE
t LLPL
t PLPH
t AVLL
t PLIV
/PSEN
t PLAZ
t LLAX
t PXIZ
t LLIV
t PXIX
A0-A7
PORT0
INSTR IN
A0-A7
t AVIV
PORT2
A8-A15
A8-A15
A8-A15
Figure 7 External Program Memory Read Cycle
Specifications subject to change without notice contact your sales representatives for the most recent information.
11
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
ALE
t WHLH
/PSEN
t LLDV
t LLWL
t RLRH
/RD
t AVLL
t RLDV
t LLAX
PORT0
t RHDZ
t RLAZ
t RHDX
DATA IN
A0 - A7 (RI or DPL)
A0 - A7 (PCL)
INSTR IN
t AVDV
t AVWL
A8 - A15 of DPH or PORT2
PORT2
A8 - A15 (PCH)
Figure 8 External Data Memory read cycle
ALE
tWHLH
/PSEN
tLLWL
tWLWH
/WR
tQVWH
tAVLL
PORT0
tLLAX
tQVWX
tWHQX
DATA OUT
A0 - A7 (RI or DPL)
A0 - A7 (PCL)
INSTR IN
tAVWL
A8 - A15 of DPH or PORT2
PORT2
A8 - A15 (PCH)
Figure 9 External Data Memory write cycle
Instruction
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tQVXH
TXD
tXHQX
0
1
tXHDV
RxD
VALID
2
3
4
5
6
tXHDX
VALID
7
Set_RI
VALID
VALID
VALID
VALID
VALID
VALID
Figure10 UART waveform in Shift Register MODE
Specifications subject to change without notice contact your sales representatives for the most recent information.
12
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Function Description
The SM89S16R1 is a stand-alone high-performance microcontroller designed for use in many applications, such as
LCD monitor, instrumentation, or high-end consumer applications.
In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these
applications.
The SM89S16R1 is a control-oriented CPU with on-chip program and data memory. It can be extended with external
data memory up to 64K bytes. For system requiring extra capability, the SM89S16R1 can be enhanced by using
external memory and peripherals.
The SM89S16R1 has two software selectable modes of saving power consumption：IDLE and POWER-DOWN. The
IDLE mode freezes the CPU while allowing the RAM, timer, serial ports and interrupt system to continue functioning.
The POWER-DOWN mode save the RAM contents but freezes the oscillator causing all other chip functions to be
inoperative. The POWER-DOWN mode can be terminated by H/W reset, or by any one of the two external interrupt
or RTCI function.
CPU
The CPU of SM89S16R1 is compatible to standard 80C51. The structure of this CPU is shown as FIGURE 11. It
contains Instruction Register (IR), Instruction Decoder, and Program Counter (PC), Accumulator (ACC), B Register,
and control logic. This CPU provides a 8-bits bi-direction bus to communicate with other blocks in the chip. The
address and data are transferred through on the same 8-bits bus.
PROG.
ADDR.
IRQ
ACC
RES
CONTROL
LOGIC
Timing & Reset
TMP2
TMP1
CLK
PROGRAM
ADDR.REGISTER
BUFFER
CTRL.
BUS
INSTRUCTION
DECODER
PROGRAM
INCREMENT
ALU
SP
PROGRAM
COUNTER
B
Register
INSTRUCTION
REGISTER
PSW
DPTR
DATA
IN/OUT
PCON
POWER CTRL.Signal
Figure 11 The CPU structure
CPU Timing
The machine cycle consists of a sequence of 6 states, numbered S1 through S6. Each state time lasts for two oscillator
periods. Thus a machine cycle takes 12 oscillator periods. Each state is divided into a PHASE 1 half and a PHASE2
half. FIGURE 12 Shows relationships between oscillator, phase, and S1-S6.
Specifications subject to change without notice contact your sales representatives for the most recent information.
13
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
PHASE
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
OSC
(Xtal2)
SEQUENCE
S1
S2
S3
S4
S5
S6
S1
S2
Figure 12 Sequences and Phases
FIGURE 12 shows the fetch / execute sequences in states and phases for various kinds of instructions. Normally the
program fetches are generated during each machine cycle, even if the instruction being executed doesn’t require it. If
the instruction being executed doesn’t need more code bytes, the CPU simply ignores the extra fetch, and the
PROGRAM COUNTER is incremented accordingly.
Execution of a one-cycle instruction (FIGURE 13A and B) begins during S1 of the machine cycle, when the
OPCODE is latched into INSTRUCTION REGISTER. A second fetch occurs during S4 of the same machine cycle.
Execution is completed at the end of S6 of this machine cycle.
The MOVX instructions take two machine cycles to execute. No program fetch is generated during the second cycle
of a MOVX instruction. This is the only time program fetches are skipped. The fetch/execute sequence for MOVX
instructions is shown in FIGURE13 (D)
The fetch/execute sequences are the same whether the PROGRAM MEMORY is internal or external to the chip.
Execution times do not depend on whether the PROGRAM MEMORY is internal or external.
FIGURE 14 shows the signals and timing involved in program fetches when the program memory is external. If
PROGRAM MEMORY is external, the PROGRAM MEMORY READ STOBE (/PSEN) is normally activated twice
per machine cycle, as shown in FIGURE 14(A).
If an access external DATA MEMORY occurs, as shown in FIGURE 14(B), two (/PSEN) are SKIPPED, because the
address and data bus are being used for DATA MEMORY access.
Note that a DATA MEMORY bus cycle takes twice as much time as PROGRAM MEMORY bus cycle. FIGURE 14
shows the relative time of the address begin emitted at PORT0 and PORT2, and of ALE and /PSEN. ALE is used to
latch the low address byte form PORT0 into the address latch.
When CPU is executing from internal PROGRAM MEMORY, /PSEN is not activated, and program address is not
emitted. However, ALE continues to be activated twice per machine cycle and so is available as clock output signal.
Note, however, that ALE is skipped during the execution of the MOVX instruction.
Specifications subject to change without notice contact your sales representatives for the most recent information.
14
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
A.) 1 byte, 1 Cycle Instruction
S1
S2
S3
S4
S5
S6
Read next OPCODE
Discard
Read OPCODE
S1
S2
Read next OPCODE
again
1 machine cycle
B.) 2 byte, 1 Cycle Instruction
S1
S2
S3
S4
S5
S6
Read 2’nd Byte
Read OPCODE
S1
S2
Read next OPCODE
1 machine cycle
C.) 1 byte, 2 Cycle Instruction
S1
S2
S3
S4
Read OPCODE
S5
S6
S1
S2
S6
S3
S4
S5
Read next OPCODE
(Discard)
S1
S2
Read next
OPCODE
again
ACCESS external memory
ADDR
Read OPCODE
S5
2’nd cycle
D.) MOVX: 1 byte, 2 Cycle Instruction
S2
S4
Read next OPCODE (Discard)
1’st cycle
S1
S3
DATA
S6
S1
S2
S3
S5
S6
No Fetch
No Fetch
1’st cycle
S4
2’nd cycle
S1
S2
Read next
OPCODE
Again
Figure 13 Timing of various instructions
Specifications subject to change without notice contact your sales representatives for the most recent information.
15
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
A.) Without MOVX
One cycle
S1
S2
S3
S4
S5
S6
S1
One cycle
S3
S4
S2
S5
S6
S1
S2
ALE
/PSEN
/RD
P2
PCH OUT
PCL
OUT
P0
PCH OUT
INST.
IN
PCL
OUT
PCH OUT
INST.
IN
PCL
OUT
PCH OUT
INST.
IN
PCL
OUT
INST.
IN
PCL
OUT
A.) With MOVX
1’st cycle
S1
S2
S3
2’nd cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
ALE
/PSEN
/RD
P2
P0
P2 or DPH out
PCH OUT
PCL
OUT
INST.
IN
Addr.
OUT
PCH OUT
Data.
IN
PCL
OUT
INST.
IN
PCL
OUT
Figure 14: Bus cycle in external program memory mode
Instruction Set
The SM89S16R1 uses the powerful instruction set of 80C51. It consists of 49 single-byte, 42 two-byte, and 15 threebyte instructions. Among them 63 instruction are executed in 1 machine-cycle, 46 instructions in 2 machine-cycles,
and the multiply, 2 instructions in 4 machine-cycles.
A summary of the instruction set is given in Table 3.
Specifications subject to change without notice contact your sales representatives for the most recent information.
16
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Addressing Mode
Notes on instruction set and address modes:
Rn
direct
Register R7-R0 of the currently selected register bank.
8-bits internal data location’s address. This could be internal DATA RAM location (0-127) or a
SFR [i.e., I/O port, control register, status register, etc. (128-255)]
8-bits RAM location addressed indirectly through register R1 or R0 of the actual register bank
8-bits constant included in the instruction
16-bits constant included in the instruction
11-bits destination address. Used by ACALL and AJMP. The branch can be anywhere within the
same 2 Kbytes page of program memory as the first byte of the following instruction.
Signed (2’s complement) 8-bits offset byte. Used by SJMP and all conditional jumps. Range is
-128 to +127 bytes relative to first byte of the following instruction.
Direct addressed bit in internal data RAM or SFR
@Ri
#data
#data16
addr11
rel
bit
Table 3: A Summary of the instruction set
Mnemonic
Arithmetic Instructions
ADD
A,Rn
ADD
A,direct
ADD
A,@Ri
ADD
A,#data
ADDC
A,Rn
ADDC
A,direct
OPERATION
BYTE
CYCLE
A = A + Rn
A = A + direct
A = A + <@Ri>
A = A + #data
A = A + Rn + C
A = A + direct + C
1
2
1
2
1
2
1
1
1
1
1
1
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
DEC
DEC
DEC
DEC
INC
MUL
DIV
A = A + @Ri + C
A = A + #data + C
A = A － Rn － C
A = A － direct － C
A = A － <@Ri> － C
A = A－#data － C
A=A+1
Rn = Rn + 1
direct = direct + 1
<@Ri> = <@Ri> + 1
A=A － 1
Rn = Rn － 1
direct = direct － 1
<@Ri> = <@Ri> － 1
DPTR = DPTR － 1
B:A = A × B
A = INT (A/B)
B = MOD (A/B)
Decimal adjust ACC
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
1
A .AND. Rn
A .AND. direct
A .AND. <@Ri>
A .AND. #data
direct .AND. A
direct .AND. #data
A .OR. Rn
A .OR. direct
A .OR. <@Ri>
A .OR. #data
direct .OR. A
direct .OR. #data
A .XOR. Rn
A .XOR. direct
A .XOR. <@Ri>
A .XOR. #data
direct .XOR. A
direct .XOR. #data
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A
Rn
direct
@Ri
A
Rn
direct
@Ri
DPTR
AB
AB
DA
A
Logical Instructions
ANL
A,Rn
ANL
A,direct
ANL
A,@Ri
ANL
A,#data
ANL
direct,A
ANL
direct,#data
ORL
A,Rn
ORL
A,direct
ORL
A,@Ri
ORL
A,#data
ORL
direct,A
ORL
direct,#data
XRL
A,Rn
XRL
A,direct
XRL
A,@Ri
XRL
A,#data
XRL
direct,A
XRL
direct,#data
Specifications subject to change without notice contact your sales representatives for the most recent information.
17
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
SWAP
A
Data Transfers Instructions
MOV
A,Rn
MOV
A,direct
MOV
A,@Ri
MOV
A,#data
MOV
Rn,A
MOV
Rn,direct
MOV
Rn,#data
MOV
direct,A
MOV
direct,Rn
MOV
direct,direct
MOV
direct,@Ri
MOV
direct,#data
MOV
@Ri,A
MOV
@Ri,direct
MOV
@Ri,#data
MOV
DPTR,#data16
MOVC
A,@A+DPTR
MOVC
A,@A+PC
MOVX
A,@Ri
MOVX
A,@DPTR
MOVX
@Ri,A
MOVX
@DPTR,A
PUSH
direct
POP
direct
XCH
A,Rn
XCH
A,direct
XCH
A,@Ri
XCHD
A,@Ri
Boolean Instructions
CLR
C
CLR
bit
SETB
C
SETB
bit
CPL
C
CPL
bit
ANL
C,bit
ANL
C,/bit
ORL
C,bit
ORL
C,/bit
MOV
C,bit
MOV
bit,C
JC
rel
JNC
rel
JB
bit,rel
JNB
bit,rel
JBC
bit,rel
Jump Instructions
ACALL
addr11
LCALL
addr16
RET
RETI
AJMP
addr11
LJMP
addr16
SJMP
rel
JMP
@A+DPTR
JZ
rel
JNZ
rel
CJNE
A, direct,rel
A=0
A = /A
Rotate ACC Left 1 bit
Rotate Left through Carry
Rotate ACC Right 1 bit
Rotate Right through Carry
Swap Nibbles in A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A = Rn
A = direct
A = <@Ri>
A = #data
Rn = A
Rn = direct
Rn = #data
direct = A
direct = Rn
direct = direct
direct = <@Ri>
direct = #data
<@Ri> = A
<@Ri> = direct
<@Ri> = #data
DPTR = #data16
A = code memory[A+DPTR]
A = code memory[A+PC]
A = external memory[Ri] (8-bits address)
A = external memory[DPTR] (16-bits address)
external memory[Ri] = A (8-bits address)
external memory[DPTR] = A (16-bits address)
INC SP: MOV “@’SP’, < direct >
MOV < direct >, “@SP”: DEC SP
ACC and < Rn > exchange data
ACC and < direct > exchange data
ACC and < Ri > exchange data
ACC and @Ri exchange low nibbles
1
2
1
2
1
2
2
2
2
3
2
2
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
C=0
bit = 0
C=1
bit = 1
C = /C
bit = /bit
C = C .AND. bit
C = C .AND. /bit
C = C .OR. bit
C = C .OR. /bit
C = bit
bit = C
Jump if C= 1
Jump if C= 0
Jump if bit = 1
Jump if bit = 0
Jump if C = 1
1
2
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
1
1
1
1
1
1
2
2
2
2
1
2
2
2
2
2
2
Call Subroutine only at 2k bytes Address
Call Subroutine in max 64K bytes Address
Return from subroutine
Return from interrupt
Jump only at 2k bytes Address
Jump to max 64K bytes Address
Jump on at 256 bytes
Jump to A+ DPTR
Jump if A = 0
Jump if A ≠ 0
Jump if A ≠ < direct >
2
3
1
1
2
3
2
1
2
2
3
2
2
2
2
2
2
2
2
2
2
2
Specifications subject to change without notice contact your sales representatives for the most recent information.
18
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
CJNZ
CJNZ
CJNZ
DJNZ
DJNZ
NOP
A, #data,rel
Rn, #data,rel
@Ri, #data,rel
Rn,rel
direct,rel
3
3
3
2
3
1
Jump if A ≠ < #data >
Jump if Rn ≠ < #data >
Jump if @Ri ≠ < #data >
Decrement and jump if Rn not zero
Decrement and jump if direct not zero
No Operation
2
2
2
2
2
1
Memory organization
The central processing unit (CPU) manipulates operands in three memory spaces; there are 1024 bytes internal data
memory (consisting of 256 bytes standard RAM and 768 bytes AUX-RAM) and 64K bytes internal/external program
memory (see FIGURE 15)
64K
64K
Overlapped space
Internal
FLASH
memory
External
FLASH
memory
/EA=1
/EA=0
02FF
XRAM
OME=0
DIRECT
(SFR)
INDIRECT
ONLY
XRAM
(OME=1)
0080
DIRECT AND
INDIRECT
0000
0000
0000
Program memory
Internal DATA memory
External
DATA memory
Figure 15 Memory organization of SM89S16R1
Program memory
The program memory of SM89S16R1 consists of 64K bytes FLASH memory on chip. If during RESET, the /EA pin
was held high, the SM89S16R1 does not execute out of the internal program memory. If the /EA pin was held low
during RESET the SM89S16R1 fetch all instructions from the external program memory.
External writer can program it. The feature of FLASH memory is shown as following：
z
READ: byte-wise
WRITE: byte-wise within 30us (previously erased by a chip erase).
z
ERASE:
z
Page Erase (512 bytes) within 10 ms
Full Erase (64K bytes) within 2 sec.
Erased bytes contain FFH
z
Endurance :
10K erase and write cycles each byte at TA=25℃
z
Retention :
10 years
Specifications subject to change without notice contact your sales representatives for the most recent information.
19
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Internal Data memory
The data memory of SM89S16R1 consists of 1024 bytes internal data memory (256 bytes standard RAM and 768
bytes AUX-RAM). The AUX-RAM is enable by SCONF.1 ($BF.1), and read/write by MOVX
Analog to Digital Converter (ADC)
The ADC block diagram was shown as below:
Those are only 4 pins mirror to Port 2[7:4] at Vin<3:0>. The digital output DATA [11:4] were put into ADCD ($8FH).
And the ADC interrupt vector is 4BH.
The ADC SFR shown as below:
ADSCR ($8EH)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Com
Con
ADCSS1
ADCSS0
CH1
CH0
COM: Read only. When conversion complete, it will be set.
CON: when set, the ADC will conversion continuous, else it will conversion only once.
ADCSS [1:0]: ADC clock select. (ADC_CLK range 500 KHz~2.5 MHz).If over frequency of ADC_CLK, the
conversion data may be unstable.
ADCSS1 ADCSS0 ADC_CLK
0
0
FOSC/8
0
1
FOSC/16
1
0
FOSC/32
1
1
FOSC/64
CH [1:0]: ADC channel select.
CH1
CH0
Input select
0
0
CH0
0
1
CH1
1
0
CH2
1
1
CH3
ADCD ($8FH)
Bit7
AD.5
*Read Only.
Bit6
AD.4
Bit5
AD.3
Bit4
AD.2
Bit3
AD.1
Bit2
AD.0
Bit1
Bit0
V D D (= V re f)
A D C SS1 A D C SS0 A D C _C LK
0
0
F o sc /4
0
1
F o sc /8
1
0
F o sc /1 6
1
1
F o sc /3 2
A D C_CLK
6
6 -b it S A R A D C
D A T A < 5 :0 >
{ A D C D [7 :2 ]}
A D C S S [1 :0 ]= { A D S C R [5 :4 ]}
V A IN < 3 :0 > { P 2 .4 ~ P 2 .7 }
C H < 2 :0 > { A D S C R [3 :2 ]}
4
3
C o m p le te
{ A D S C R .7 }
C o n tin u o u s { A D S C R .6 }
VSS
Figure 16 ADC Block Diagram
Specifications subject to change without notice contact your sales representatives for the most recent information.
20
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Pulse Width Modulation (PWM)
The PWM output pins are P1.4 and P1.5.
The PWM clock is {Fosc/ (2xDivider)}, the PWM output frequency is {(PWM clock)/32} at 5 bits resolution and
{(PWM clock)/256} at 8 bits resolution.
The PWM SFR show as below:
PWMC ($D3H and $D4H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
PBS
Bit1
PFS1
Bit0
PFS0
Bit1
PWMD.1
Bit0
PWMD.0
PBS: when set, the PWM is 5 bits resolution.
PFS [1:0]: The PWM clock divider select.
PFS1
0
0
1
1
PFS0
0
1
0
1
PWM clock divider select
2
4
8
16
PWMD ($B3H and $B4H)
Bit7
PWMD.7
Bit6
PWMD.6
Bit5
PWMD.5
Bit4
PWMD.4
Bit3
PWMD.3
Bit2
PWMD.2
Real Time Clock (RTC)
The on-chip RTC keeps time of second and minute functions. Its time base is a 32.768 KHz crystal between pins
X32OUT (alternate function of ALE) and X32IN (alternate function of PSEN). The RTC maintains time to a second.
It also allows a user to read (and write) seconds and minute.
The RTC function used SFR descriptor as below:
RTCS ($A1H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RTCen
Stable
SEC.5
SEC.4
SEC.3
SEC.2
SEC.1
SEC.0
RTCen: When set to ‘1’, enable the enable RTC function. When this bit set, the ALE and PSEN pins output will
disable, and the ALE and PSEN pins will use for RTC function as X32OUT and X32IN.
Stable: Read only. The Stable bit will set to 1 when the RTC module stable. Please wait 2 seconds before used the
RTC function.
SEC [5:0]: show the current second counter at RTC function. The range is from 00H to 3BH.
RTCC ($A2H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
INT_SEL1
INT_SEL0
MIN.5
MIN.4
MIN.3
MIN.2
MIN.1
INT_SEL [1:0]: the interrupt distribution selection bit, the interrupt vector is 43H.
00: the interrupt is set as 0.5 second
01: the interrupt is set as 1 second
10: the interrupt is set as 30 second
11: the interrupt is set as 60 second
MIN [5:0]: show the current minute counter at RTC function. The range is from 00H to 3BH.
Bit0
MIN.0
Specifications subject to change without notice contact your sales representatives for the most recent information.
21
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Starting and stopping the RTC:
RTCS ($A1H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RTCen
Stable
SEC.5
SEC.4
SEC.3
SEC.2
SEC.1
SEC.0
The RTC Function is enable by set the RTCS.7 (RTCen=1), then the ALE and /PSEN pins will switch to X32OUT
and X32IN that for RTC function used, the ALE and PSEN signal output will disable; the crystal frequency is 32.768
KHz. See figure 17.
SW 1
R
1
2
J1
1
1
2
3 2 7 6 8 H z C lo c k in
RTCen
X 3 2 in (/P S E N )
Y1
32768H z
J2
In C h ip
1
X 3 2 o u t(A L E )
Figure 17 The RTC Crystal connect diagram
The stable bit (RTCS.6) will set to 1 when the RTC module stable. The design is about 31.25 ms; suggest waiting 2
second to use the RTC function. This bit will clear when RTCen bit set again.
The SEC [5:0] will show the second counter (range from 00H to 3BH), and the MIN [5:0] will show the minute
counter (range from 00H to 3BH) of RTC function. This two register will clear when RTCen bit set.
Interrupt:
IE1 ($A9H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EADC
ERTC
ERTC: When set to ‘1’, enable the RTC interrupt. If you want to use the RTC interrupt function, must enable the EA
bit in IE.7 and enable the ERTC bit in IE1.2.
EADC: When set to ‘1’, enable the ADC interrupt. If you want to use the ADC interrupt function, must enable the EA
bit in IE.7 and enable the EADC bit in IE1.3
RTCC ($A2H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
INT_SEL1
INT_SEL0
MIN.5
MIN.4
MIN.3
MIN.2
MIN.1
MIN.0
Then select the interrupt distribution in INT_SEL [1:0] in RTCC [7:6].
The RTC can select each of 4 interrupt sources: 0.5 second, 1 second, 0.5 minute, and 1 minute. The interrupt vector
is 43H, it can wake-up CPU from POWER-DOWN mode.
IFR ($AAH)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADCIF
RTCIF
ADCIF: When interrupt occupy the ADC interrupt flag (IFR.3) will set, and the CPU will execute the interrupt
subroutine at the interrupt vector 4BH. The ADC Interrupt Flag must clear by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
22
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
RTCIF: When interrupt occupy the RTC interrupt flag (IFR.2) will set, and the CPU will execute the interrupt
subroutine at the interrupt vector 43H. The RTC Interrupt Flag must clear by software.
IP1 ($B9H)
Bit7
Bit6
Bit5
Bit4
Bit3
PADC
Bit2
PRTC
Bit1
Bit0
The interrupt priority can be set at IP1.2 or IP1.3.
PADC: When set to ‘1’, enable the ADC interrupt priority.
PRTC: When set to ‘1’, enable the RTC interrupt priority.
U2
int 0.5sec
int 1sec
Divider 16384
Divider 2
int 0.5min
Divider 30
Divider 2
4
3
2
1
15
14
13
12
int 1min
32768Hz Clock in
<Value>
<Value>
<Value>
<Value>
int sel0
int sel1
RTCen
11
10
9
7
D0
D1
D2
D3
D4
D5
D6
D7
Y
Y
5
6
int out
A
B
C
G
74151
5 bits shif register
5 bits shif register
sec0
sec1
sec2
second register sec3
sec4
sec5
min0
min1
min2
minute register min3
min4
min5
<Value>
<Value>
Figure 18 The RTC Block Diagram
LED Driving Capability Control
This function is set the sink current more then 10 mA for each pin, 26 mA for whole Port 0, 15 mA for whole Port 1 or
whole Port2 or whole Port3 or whole Port4, and total 71 mA for whole chip.
The SFR show as below:
Port Name
Port0
Port1
Port2
Port3
Port4
SFR Address
$92H
$93H
$94H
$95H
$96H
Iol(max) for total port
26 mA
15 mA
15 mA
15 mA
15 mA
The Power Down Wake Up (PDWU) function
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this will be the
last instruction to be executed before the device goes into Power Down mode. In the Power Down mode, all the
clocks are stopped and the device comes to a halt. All activity is completely stopped and the power consumption is
reduced to the lowest possible value. In this state the ALE and PSEN pins are pulled low. The port pins output the
values held by their respective SFRs.
Specifications subject to change without notice contact your sales representatives for the most recent information.
23
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
The SM89S16R1 will exit the Power Down mode with a reset or by a RTC (Real Time Clock) interrupt or by an
external interrupts pin enabled as level detects.
1. An external reset can be used to exit the Power Down state. The high on RST pin terminates the Power Down mode,
and restarts the clock. The program execution will restart from 0000H.
2. An external interrupt pin and RTC interrupt can be used to exit the Power Down state when the external interrupt or
RTC interrupt actives and provided the corresponding interrupt is enabled, while the global enable (EA) bit is set and
the external input has been set to a level detect mode or RTC interrupt set. If these conditions are met, then the low
level on the external pin or RTC interrupt re-starts the oscillator. Then device executes the interrupt service routine for
the corresponding external interrupt or RTC interrupt. After the interrupt service routine is completed, the program
execution returns to the instruction after the one that put the device into Power Down mode and continues from there.
PCON ($87H)
Bit7
Bit6
Bit5
Bit4
Bit3
SMOD
SMOD: This bit set to ‘1’ to make the UART baud-rate double.
PD: When set to ‘1’ , the MCU will into Power Down mode
IDLE: When set to ‘1’ , the MCU will into IDLE mode
Bit2
Bit1
PD
Bit0
IDLE
Bit2
Bit1
OME
Bit0
ALEI
Bit3
ET1
Bit2
EX1
Bit1
ET0
Bit0
EX0
Bit3
IE1
Bit2
IT1
Bit1
IE0
Bit0
IT0
SCONF ($BFH)
Bit7
Bit6
Bit5
Bit4
Bit3
PDWUE
PDWUE: When set to ‘1’, enable the PDWU function.
OME: When set to ‘1’, enable the 768 bytes expanded RAM.
ALEI: When set to ‘1’, it will stop ALE clock output for EMI reduce.
IE ($A8H)
Bit7
Bit6
Bit5
Bit4
EA
ET2
ES0
EA: When set to ‘1’, enable interrupt global.
ET2: When set to ‘1’, enable Timer2 interrupt.
ES0: When set to ‘1’, enable UART interrupt.
ET1: When set to ‘1’, enable Timer1 interrupt.
EX1: When set to ‘1’, enable external interrupt 1.
ET0: When set to ‘1’, enable Timer0 interrupt.
EX0: When set to ‘1’, enable external interrupt 0.
TCON ($88H)
Bit7
Bit6
Bit5
TF1
TR1
TF0
TF1: Timer 1 overflow flag.
TR1: Timer 1 run control bit.
TF0: Timer 0 overflow flag.
TR0: Timer 0 run control bit.
IE1: External Interrupt 1 edge flag.
IT1: Interrupt 1 type control bit.
IE0: External Interrupt 0 edge flag.
IT0: Interrupt 0 type control bit.
Bit4
TR0
Specifications subject to change without notice contact your sales representatives for the most recent information.
24
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
IP ($B8H)
Bit7
Bit6
Bit5
PT2
Bit4
PS0
Bit3
PT1
Bit2
PX1
Bit1
PT0
Bit0
PX0
PT2: Timer2 interrupt priority.
PS0: UART interrupts priority.
PT1: Timer1 interrupt priority.
PX1: external interrupt 1 priority.
PT0: Timer0 interrupt priority.
PX0: external interrupt 0 priority.
The Priority structure and vector locations of interrupts:
Source
External interrupt 0
Timer 0 overflow
External interrupt 1
Timer 1 overflow
UART 0 interrupt
Timer 2 overflow
RTC interrupt
ADC interrupt
Flag
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
RTCIF
ADCIF
Priority level
1(highest)
2
3
4
5
6
7
8
Bit4
Bit3
Vector Address
03H
0BH
13H
1BH
23H
2BH
43H
4BH
T2MOD ($C9H)
Bit7
Bit6
Bit5
Bit2
Bit1
Bit0
T2OE
DCEN
T2CR: Timer 2 Capture Reset. In the Timer2 Capture Mode this bit enables/disables hardware automatically reset
Timer2 while the value in TL2 and TH2 have been transferred into the capture register.
T2OE: Timer2 clock Output Enable bit. If set to 1, the Timer2 clock will output to P1.0.
DCEN: Down Count Enable. When set this bit then allows Timer2 to be configured as an up/down counter.
Application Reference
X'tal
C1
C2
R
3MHz
30 pF
30 pF
open
Valid for SM89S16R1
6MHz
9MHz
30 pF
30 pF
30 pF
30 pF
open
open
XI
12MHz
22 pF
22 pF
open
X'tal
SM89S16R1
R
X2
X'tal
16MHz
25MHz
33MHz
40MHz
C1
C2
C1
30 pF
15 pF
5 pF
2 pF
C2
30 pF
15 pF
5 pF
2 pF
R
open
open
6.8K　4.7K　Note:
Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each
crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components.
Specifications subject to change without notice contact your sales representatives for the most recent information.
25
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
40L 600mil PDIP Information
E
E1
D
S
C
A2
A1
A
L
e1
eA
B1
B
a
Note:
1. Dimension D Max & include mold flash or tie bar
burrs.
2. Dimension E1 does not include inter lead flash.
3. Dimension D & E1 include mold mismatch and are
determined at the mold parting line.
4. Dimension B1 does not include dam bar protrusion/
infusion.
5. Controlling dimension is inch.
6. General appearance spec. should base on final visual
inspection spec.
Symbol
A
A1
A2
B
B1
C
D
E
E1
e1
L
a
eA
S
Dimension in inch
Minimal / maximal
- / 0.210
0.010 / 0.150 / 0.160
0.016 / 0.022
0.048 / 0.054
0.008 / 0.014
- / 2.070
0.590 / 0.610
0.540 / 0.552
0.090 / 0.110
0.120 / 0.140
0 / 15
0.630 / 0.670
- / 0.090
Dimension in inch
Minimal / maximal
- / 5.33
0.25 / 3.81 / 4.06
0.41 / 0.56
1.22 / 1.37
0.20 / 0.36
- / 52.58
14.99 / 15.49
13.72 / 14.02
2.29 / 2.79
3.05 / 3.56
0 / 15
16.00 / 17.02
- / 2.29
Specifications subject to change without notice contact your sales representatives for the most recent information.
26
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
L
44L Plastic Chip Carrier (PLCC)
6
7
GE
E
y
HE
A2
D
A
HD
C
θ
b1
e
Dimension in inch
Minimal / maximal
- / 0.185
0.020 / 0.145 / 0.155
0.026 / 0.032
0.016 / 0.022
0.008 / 0.014
0.648 / 0.658
0.648 / 0.658
0.050 BSC
0.590 / 0.630
0.590 / 0.630
0.680 / 0.700
0.680 / 0.700
0.090 / 0.110
- / 0.004
/
1. Dimension D & E does not include inter lead flash.
2. Dimension b1 does not include dam bar protrusion/
intrusion.
b
3. Controlling dimension: Inch
4. General appearance spec. should base on final visual
inspection spec.
GD
Symbol
A
A1
A2
b
b1
C
D
E
e
GD
GE
HD
HE
L
θ
y
A1
Dimension in inch
Minimal / maximal
- / 4.70
0.51 / 3.68 / 3.94
0.66 / 0.81
0.41 / 0.56
0.20 / 0.36
16.46 / 16.71
16.46 / 16.71
1.27 BSC
14.99 / 16.00
14.99 / 16.00
17.27 / 17.78
17.27 / 17.78
2.29 / 2.79
- / 0.10
/
Specifications subject to change without notice contact your sales representatives for the most recent information.
27
SM89S16R1 V1.0 JANUARY 2005
SyncMOS Technologies Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
C
44L Plastic Quad Flat Package
L
L1
S
θ2
e
R1
D2 D1D
b
A2
Gage Plane
0.25 mm
θ3
R2
A1
E2
E1
E
A
Note:
Dimension D1 and E1 do not include mold protrusion.
Allowance protrusion is 0.25mm per side.
Dimension D1 and E1 do include mold mismatch
e1
and are determined datum plane.
seating plane
Dimension b does not include dam bar protrusion.
C
Allowance dam bar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material
e
condition. Dam bar cannot be located on the lower
radius or the lead foot.
Symbol
A
A1
A2
b
c
D
D1
D2
E
E1
E2
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
C
Dimension in inch
Minimal / maximal
- / 0.100
0.006 / 0.014
0.071 / 0.087
0.012 / 0.018
0.004 / 0.009
0.520 BSC
0.394 BSC
0.315
0.520 BSC
0.394 BSC
0.315
0.031 BSC
0.029 / 0.041
0.063
0.005 / 0.005 / 0.012℃
0.008 / 0℃ / 7℃
0℃ / 10℃ REF
7℃ REF
0.004
Dimension in inch
Minimal / maximal
- / 2.55
0.15 / 0.35
1.80 / 2.20
0.30 / 0.45
0.09 / 0.20
13.20 BSC
10.00 BSC
8.00
13.20 BSC
10.00 BSC
8.00
0.80 BSC
0.73 / 1.03
1.60
0.13 / 0.13 / 0.30
0.20 / as left
as left
as left
as left
0.10
Specifications subject to change without notice contact your sales representatives for the most recent information.
28
SM89S16R1 V1.0 JANUARY 2005