ETC TA0102A

Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on
TA0102A
STEREO 150W (4Ω) CLASS-T DIGITAL AUDIO AMPLIFIER
DRIVER USING DIGITAL POWER PROCESSING (DPP T M )
TECHNOLOGY
Technical Information
Revision 3.1 – June 2000
GENERAL DESCRIPTION
The TA0102A is a 150W continuous average (4Ω), two channel Amplifier Driver
Module which uses Tripath’s proprietary Digital Power Processing (DPPTM)
technology.
Class-T amplifiers offer both the audio fidelity of Class-AB and
the power efficiency of Class-D amplifiers.
Applications
Audio/Video
Amplifiers/Receivers
Pro-audio Amplifiers
Automobile Power Amplifiers
Subwoofer Amplifiers
Benefits
Reduced system cost with smaller/less
expensive power supply and heat sink
Signal fidelity equal to high quality ClassAB amplifiers
High dynamic range compatible with digital
media such as CD and DVD
Features
Class-T architecture
Proprietary Digital Power Processing
technology
Supports wide range of output power levels
“Audiophile” Quality Sound
0.05% THD+N @ 20W, 8Ω
0.03% IHF-IM @ 30W, 8Ω
80W @ 8Ω, 0.1% THD+N, VS = +/-45V
150W @ 4Ω, 0.1% THD+N, VS = +/-45V
High Power
100W @ 8Ω, 1% THD+N, VS = +/-45V
170W @ 4Ω, 1% THD+N, VS = +/-45V
High Efficiency
90% @ 85W @ 8Ω, VS = +/-33.75V
88% @ 155W @ 4Ω, VS = +/-33.75V
Dynamic Range = 108 dB
Requires only N-Channel MOSFET output
transistors
High power supply rejection ratio
Mute input
Outputs short circuit protected
Over- and under-voltage protection
Bridgeable, single-ended outputs
38-pin quad package
Supports 100kHz BW of Super Audio CD and
DVD-Audio (refer to Application Note for specifics)
Typical Performance
THD+N versus Output Power
10
20Hz - 22kHz BW
f = 1kHz
BBM = 25nS
Vs = +/-45V
Av = 14.8
ST STP19NB20 MOSFET
5
2
THD+N (%)
1
0.5
0.2
RL = 8Ω
0.1
RL = 4Ω
0.05
0.02
0.01
1
2
5
10
20
50
100
200
Output Power (W)
1
TA102A –Rev.3.1/06.01
Tripath Technology, Inc. - Technical Information
Absolute Maximum Ratings
SYMBOL
PARAMETER
VALUE
UNITS
VS
Supply Voltage (VSPOS & VSNEG)
V5
Positive 5V Bias Supply
VN12
Supply Voltage: Nominal +12V referenced to VSNEG
18
V
TSTORE
Storage Temperature Range
-40 to 150
°C
TA
Operating Free-air Temperature Range
-20 to +80
°C
Notes:
+/-70
V
6
V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Damage will occur to the device if VN12 is not supplied or falls below the recommended
operating voltage when VS is within its recommended operating range.
SYMBOL
PARAMETER
Operating Conditions
MIN.
TYP.
+/-28
MAX.
UNITS
+/-49
V
VS
Supply Voltage (V spos & V sneg)
V5
Positive 5V Bias Supply
4.5
5
5.5
V
VN12
Supply Voltage: Nominal +12V referenced to V SNEG
10.8
12
13.2
V
Note: Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics
for guaranteed specific performance limits.
Electrical Characteristics
Unless otherwise specified, TA = 25°C. See Notes 1 & 2 for Operating Conditions and Test/Application
Circuit Setup.
SYMBOL
PARAMETER
TYP.
MAX.
UNITS
75
50
65
160
Source Current @ POUT = 150W, 4Ω +33.75V
-33.75V
Source Current for 5V Bias Supply @ POUT = 150W, RL = 4Ω
25
30
45
110
5.1
5.2
42
mA
mA
mA
mA
A
A
mA
IVN12
Source Current for VN12 Supply @ POUT = 150W, RL = 4Ω
46
VU
Under Voltage (V spos & V sneg)
VO
Over Voltage (V spos & V sneg)
V IH - MUTE
High-level Input Voltage (MUTE)
V IL - MUTE
Low -level Input Voltage (MUTE)
IDDMUTE
Mute Supply Current
(no load, 145nS delay)
Iq
Quiescent Current
(no load, BBM0=BBM1=0)
IS
I5
V OH
MIN.
+33.75V
-33.75V
+5V
VN12
+33.75V
-33.75V
+5V
VN12
High-level Output Voltage (HMUTE & OVERLOADB)
V OL
Low -level Output Voltage (HMUTE & OVERLOADB)
V TOC
Over Current Sense Voltage Threshold
AV
Gain Ratio V O/V I, RIN = 0Ω
Voffset
Offset Voltage, no load, MUTE = Logic low (before nulling)
mA
+/-28
V
+/-49
V
3.5
V
1
V
0.315
4
18
0.475
2
5
25
2
mA
mA
mA
mA
V
1
V
0.70
0.77
V
3.5
0.63
77
V/V
500
mV
Minimum and maximum limits are guaranteed but may not be 100% tested.
2
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Performance Characteristics – Single Ended, Vs = +45V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25°C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
PARAMETER
POUT
Output Pow er
(Continuous Average/Channel)
THD + N
IHF-IM
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
SNR
Signal-to-Noise Ratio
CONDITIONS
MIN.
TYP.
MAX.
UNITS
THD+N = 0.1%
RL = 8Ω
RL = 4Ω
THD+N = 1%
RL = 8Ω
RL = 4Ω
PO = 20W/Channel, RL = 8Ω
80
130
100
170
0.05
W
W
W
W
%
19kHz, 20kHz, 1:1 (IHF), RL = 4Ω
POUT = 30W/Channel
A-Weighted, POUT = 88W/Ch, RL = 8Ω
0.05
%
98.5
dB
CS
Channel Separation
0dBr = 30W, RL= 8Ω
85
dB
PSRR
Pow er Supply Rejection Ratio
f = 120Hz, Vripple = 100 mV
67
dB
η
Pow er Efficiency
POUT = 230W/Channel, RL = 4Ω
82
%
eNOUT
Output Noise Voltage
A-Weighted, no signal, input shorted,
DC offset nulled to zero
300
µV
Performance Characteristics – Single Ended, Vs = +33.75V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25°C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNITS
THD+N = 0.1%
RL = 8Ω
RL = 4Ω
THD+N = 1%
RL = 8Ω
RL = 4Ω
PO = 20W/Channel, RL = 8Ω
47
77
65
110
0.05
W
W
W
W
%
0.03
%
Signal-to-Noise Ratio
19kHz, 20kHz, 1:1 (IHF), RL = 4Ω
POUT = 30W/Channel
A-Weighted, POUT = 47W/Ch, RL = 8Ω
100
dB
Channel Separation
0dBr = 20W, RL= 8Ω
85
dB
PSRR
Pow er Supply Rejection Ratio
f = 120Hz, Vripple = 100 mV
67
dB
η
Pow er Efficiency
POUT = 85W/Channel, RL = 8Ω
90
%
eNOUT
Output Noise Voltage
A-Weighted, no signal, input shorted,
DC offset nulled to zero
195
µV
POUT
Output Pow er
(Continuous Average/Channel)
THD + N
IHF-IM
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
SNR
CS
Minimum and maximum limits are guaranteed but may not be 100% tested.
Notes:
1.
2.
3
V5 = +5V, VN12 = +12V referenced to VSNEG
Test/Application Circuit Values:
D = MUR120T3 diodes, RIN = 22.1KΩ
RD = 33ΩRS = 0.025ΩRG = 30Ω
ROCR1 = ROCR2 = 0Ω, LF = 18uH (Amidon core T200-2)
CF = 0.22uF, CD = 0.1uF, CIN = 1uF, CBY = 0.1uF
Power Output MOSFET, M = ST STP19NB20
BBM0 =BBM1 = 1
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Pin Description
1
AGND
2
OVERLOADB
3
V5
4
MUTE
5
35
34
33
32
31
30
29
28
PGND
36
FDBKN2
37
LO2COM
38
OCS2L-
NC
OCS2L+
36, 37, 38
Over-current threshold adjustment (Channel 1 & 2)
Over Current Sense resistor, Channel 1 low-side
Over Current Sense resistor, Channel 1 high-side
Kelvin connection to source of low-side transistor (Channel 1 & 2)
Feedback (Channel 1 & 2)
Voltage: +12 V from VSNEG. Refer to Application Information section.
Low side gate drive output (Channel 1 & 2)
Kelvin connection to source of high-side transistor (Channel 1 & 2)
High side gate drive output (Channel 1 & 2)
Positive supply voltage
Negative supply voltage
Power Ground
Over Current Sense resistor, Channel 2 low-side
Over Current Sense resistor, Channel 2 high-side
Logic output. When high, indicates that the output stages of both
amplifiers are shut off and muted.
Not Connected - Must Be Left Floating
OCS2H-
10, 11
13, 14
15, 16
17, 30
18, 29
19
20, 27
21, 26
22, 25
23
24
28
31, 32
33, 34
35
IN2, IN1
BBM0, BBM1
GNDKELVIN1,
GNDKELVIN2
OCR2, OCR1
OCS1L+, OCS1LOCS1H-, OCS1H+
LO1COM, LO2COM
FDBKN1;FDBKN2
VN12
LO1, LO2
HO1COM, HO2COM
HO1, HO2
VSPOS
VSNEG
PGND
OCS2L-, OCS2L+
OCS2H-, OCS2H+
HMUTE
OCS2H+
5, 6
7, 8
9, 12
HMUTE
V5
MUTE
NC
3
4
Description
Analog Ground
Logic output. When low, indicates that the level of the input signal has
overloaded the amplifier.
Positive 5 Volts
Logic input. When high, both amplifiers are muted. When low
(grounded), both amplifiers are fully operational.
Single-ended input (Channel 1 & 2)
Break-before-make timing control
Kelvin connection to speaker ground (Channel 1 & 2)
NC
Function
AGND
OVERLOADB
NC
Pin
1
2
LO2
27
HO2COM
26
HO2
25
BBM1
LO1
20
9
10
11
12
13
14
15
16
38 PIN QUAD MODULE PIN OUT
17
18
VN12
8
FDBKN1
21
LO1COM
H01COM
OCS1H+
BBM0
OCS1H-
22
7
OCS1L-
HO1
OCS1L+
IN1
GND KELVIN2
23
6
OCR1
VSPOS
OCR2
24
IN2
GND KELVIN1
VSNEG
19
TOP VIEW
FIGURE 1
4
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
TEST/APPLICATION CIRCUIT
TA0102A
18 FDBKN1
16 OCS1H+
VSPOS
RS
.1uF
100uF
15 OCS1HM
22
CIN
IN1
Processing
&
Modulation
6
RIN
21 HO1COM
10KΩ
LO1
13 OCS1L+
1MΩ
1MΩ
0.1 uF
MUTE
CBY
LF
D
RG
CBY
17 LO1COM
4
D
RG
M
20
V5
HO1
CF
RD
RL
CD
RS
14 OCS1L-
VSNEG
9 GNDKELVIN1
.1uF
OCR1
11
OCR2
10
2
ROCR1
35
HMUTE
29 FDBKN2
ROCR2
34 OCS2H+
VSPOS
7
BBM0
RS
M
25
CIN
IN2
Processing
&
Modulation
5
RIN
V5
HO2
26 HO2COM
LO2
32 OCS2L+
10KΩ
1MΩ
D
CBY
LF
D
RG
30 LO2COM
NC
100uF
RG
M
27
0.1 uF
.1uF
33 OCS2H-
8
BBM1
1MΩ
100uF
OVERLOADB
CBY
CF
RD
RS
31 OCS2L-
36
RL
CD
VSNEG
12 GNDKELVIN2
NC
NC
V5
0.1 uF
37
.1uF
23
38
24
3
19
AGnd
1
100uF
VSPOS
VSNEG
VN12
PGnd
28
NC - Not Connected (Must Be Left Floating)
Note - Heavy Lines Indicate High-Current Paths
Figure 2
5
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Typical Performance at Vs = +45V
THD+N versus Output Power
Efficiency versus Output Power
10
20Hz - 22kHz BW
f = 1kHz
BBM = 25nS
Vs = +/-45V
Av = 14.8
ST STP19NB20 MOSFET
5
RL = 4Ω
90
80
2
Efficiency (%)
70
THD+N (%)
1
0.5
0.2
RL = 8Ω
0.1
50
40
22Hz - 22kHz BW
f = 1kHz
BBM = 145nS
VS = +/-45V
Av = 20.75
ST STP19NB20 MOSFET
30
20
RL = 4Ω
0.05
60
10
0
0.02
0
0.01
1
2
5
10
20
50
100
50
100
Output Power (W)
THD+N versus Frequency
RL = 4Ω
+10
10 20Hz - 22kHz BW
5 BBM = 25nS
Pout = 30W/Channel
2 V = +/-45V
S
1 Av = 14.8
0.5 ST STP19NB20 MOSFET
200
250
Intermodulation Performance
RL = 4Ω
10Hz - 80kHz BW
+0 19kHz, 20kHz, 1:1
BBM = 25nS
-10 Pout = 30W/Channel
VS = +/-45V
-20 0dBr = 11Vrms
Av = 14.8
FFT (dBr)
THD+N (%)
150
Output Power (W)
200
0.2
0.1
0.05
0.02
-30 ST STP19NB20 MOSFET
-40
-50
-60
-70
0.01
-80
0.005
-90
0.002
0.001
10
-100
20
50
100
200
500
1k
2k
5k
10k
20k
60
100
200
500
1k
2k
5k
10k
20k 30k
Frequency (Hz)
Frequency (Hz)
Channel Separation versus Frequency
RL = 4Ω
+0
-10
-20
-30
-40
+0
-20
-30
-40
-50
-60
-70
-50
-60
-70
-80
-90
-80
-100
-110
-90
-120
-100
-130
-110
-120
20Hz - 22kHz BW
BBM = 25nS
Pout = 0
VS = +/-45V
RL = 4Ω
Av = 14.8
ST STP19NB20 MOSFET
-10
Noise (dBv)
Channel Separation (dBr)
A-Weighted Noise FFT
20Hz - 22kHz BW
BBM = 25nS
Pout = 30W/Channel
VS = +/-45V
Av = 14.8
ST STP19NB20 MOSFET
-140
20
20
50
100
200
500
1k
2k
5k
10k
20k
50
100
200
500
1k
2k
Frequency (Hz)
Frequency (Hz)
6
TA0102A, Rev. 3.1/06.01
5k
10k
20k
Tripath Technology, Inc. - Technical Information
Typical Performance at Vs = +33.75V
THD+N versus Output Power
10
2
100
90
RL = 8 Ω
80
8Ω
1
Efficiency (%)
5
THD+N (%)
Efficiency versus Output Power
20Hz - 22kHz BW
f = 1kHz
BBM = 25nS
VS = +/-33.75V
Av = 14.8
ST STP19NB20 MOSFET
4Ω
0.5
0.2
0.1
70
RL = 4 Ω
60
50
40
22Hz - 22kHz BW
f = 1kHz
BBM = 145nS
VS = +/-33.75V
Av = 14.8
ST STP19NB20 MOSFET
30
20
0.05
10
0.02
0.01
0
0
1
2
5
10
20
50
100
25
50
75
200
Output Power (W)
BBM = 25nS
Pout = 20W/Channel
VS = +/-33.75V
Av = 14.8
ST STP19NB20 MOSFET
5
2
2
1
1
0.5
0.2
30kHz BW
0.1
22kHz BW
0.02
0.5
0.2
30kHz BW
0.1
10
20
50
100
200
500
1k
2k
5k
10k
22kHz BW
0.02
20k
0.01
10
20
50
100
Frequency (Hz)
10
5
500
1k
10
5k
10k
20k
20Hz - 22kHz BW
Pout = 30W/Channel
VS = +/-33.75V
Av = 14.8
ST STP19NB20 MOSFET
5
2
1
1
THD+N (%)
2
0.5
145nS
105nS
0.1
0.5
145nS
0.2
105nS
0.1
65nS
65nS
0.05
0.05
25nS
25nS
0.02
0.01
10
2k
THD+N versus Frequency versus
Break Before Make, RL = 4Ω
20Hz - 22kHz BW
Pout = 20W/Channel
VS = +/-33.75V
Av = 14.8
ST STP19NB20 MOSFET
0.2
200
Frequency (Hz)
THD+N versus Frequency versus
Break Before Make, RL = 8Ω
THD+N (%)
175
0.05
0.05
0.01
150
BBM = 25nS
Pout = 30W/Channel
VS = +/-33.75V
Av = 14.8
ST STP19NB20 MOSFET
10
THD+N (%)
THD+N (%)
5
125
THD+N versus Frequency versus
Bandwidth, RL = 4Ω
THD+N versus Frequency versus
Bandwidth, RL = 8Ω
10
100
Output Power (W)
0.02
20
50
100
200
500
1k
Frequency (Hz)
7
2k
5k
10k
20k
0.01
10
20
50
100
200
500
1k
2k
5k
Frequency (Hz)
TA0102A, Rev. 3.1/06.01
10k
20k
Tripath Technology, Inc. - Technical Information
Typical Performance
THD+N versus Output Power
versus Supply Voltage
RL = 8Ω
THD+N (%)
10
10
20Hz - 22kHz BW
f = 1kHz
BBM = 25nS
Av = 14.8
ST STP19NB20 MOSFET
27V
THD+N (%)
1
50V
33.75V
0.1
Output Power (W)
1
100
1000
-10
-20
1
10
+10
+0
-10
-20
FFT (dBr)
-40
-50
-70
-70
-80
-80
-90
-90
-100
200
1000
Intermodulation Performance
RL = 4Ω
10Hz - 80kHz BW
19kHz, 20kHz, 1:1
BBM = 25nS
Pout = 30W/Channel
VS = +/-33.75V
0dBr = 11Vrms
Av = 14.8
ST STP19NB20 MOSFET
-50
-60
100
100
-40
-60
60
Output Power (W)
-30
-30
-100
50V
0.01
10Hz - 80kHz BW
19kHz, 20kHz, 1:1
BBM = 25nS
Pout = 20W/Channel
VS = +/-33.75V
0dBr = 13Vrms
Av = 14.8
ST STP19NB20 MOSFET
+0
33.75V
27V
Intermodulation Performance
RL = 8Ω
+10
500
1k
2k
5k
10k
20k 30k
60
100
200
500
1k
2k
5k
10k
20k 30k
Frequency (Hz)
Frequency (Hz)
Channel Separation versus Frequency
A-Weighted Noise FFT
+0
+0
20Hz - 22kHz BW
BBM = 25nS
Pout = 0
VS = +/-33.75V
RL = 4Ω
Av = 14.8
ST STP19NB20 MOSFET
-20
-30
-40
-10
Channel Separation (dBr)
-10
-50
Noise (dBv)
FFT (dBr)
10
20Hz - 22kHz BW
f = 1kHz
BBM = 25nS
Av = 14.8
ST STP19NB20 MOSFET
0.1
0.01
1
THD+N versus Output Power
versus Supply Voltage
RL = 4Ω
-60
-70
-80
-90
-100
-110
-20
-30
20Hz - 22kHz BW
BBM = 25nS
Pout = 30W/Channel @ 4Ω
Pout = 20W/Channel @ 8Ω
VS = +/-33.75V
Av = 14.8
ST STP19NB20 MOSFET
-40
-50
-60
-70
4Ω
-80
8Ω
-120
-90
-130
-140
20
50
100
200
500
1k
Frequency (Hz)
8
2k
5k
10k
20k
-100
20
50
100
200
500
1k
2k
5k
Frequency (Hz)
TA0102A, Rev. 3.1/06.01
10k
20k
Tripath Technology, Inc. - Technical Information
Functional Description
TA0102A Amplifier Operation
Figure 3 is a simplified diagram of one channel (channel 1) of a TA0102A amplifier to assist in
understanding its operation.
TA0102A
18 FDBKN1
16 OCS1H+
Over-current
Detection
VSPOS
RS
15 OCS1HVBOOT
MUTE
RIN
IN1
BBM0
CIN
BBM1
M
22 HO1
4
Processing
&
Modulation
6
7
21 HO1COM
19 VN12
Low-pass
Filter
M
20 LO1
8
RL
17 LO1COM
OCR1
RG
RG
Over-current 13 OCS1L+
Detection
11
ROCR1
14 OCS1L-
RS
VSNEG
9 GNDKELVIN1
2
35
Over/Under
Voltage
V5
23
24
OVERLOADB
HMUTE
VSPOS
VSNEG
3
A Gnd
1
P Gnd
28
Figure 3. Simplified TA0102A Amplifier
The audio input signal (IN1) is fed into the processor internal to the TA0102A, where a modulation
pattern is generated. This pattern is spread spectrum and varies between approximately 200kHz and
1.5MHz. Complementary copies of the switching pattern are level-shifted by the MOSFET drivers
and output from the TA0102A where they drive the gates (HO1 and LO1) of external power
MOSFETs that are connected as a half bridge. The output of the half bridge is a power-amplified
version of the switching pattern that switches between VSPOS and VSNEG. This signal is then low-pass
filtered to obtain amplified audio.
9
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
The processor portion of the TA0102A is operated from a 5-volt supply (between V5 and AGND). In
the generation of the complementary modulation pattern for the output MOSFETs, the processor
inserts a “break-before-make” dead time between when it turns one transistor off and it turns the
other one on in order to minimize shoot-through currents in the MOSFETs. The dead time can be
programmed by setting the break-before-make control bits, BBM0 and BBM1. Feedback information
from the output of the half-bridge is supplied to the processor via FDBKN1. Additional feedback
information to account for ground bounce is supplied via GNDKELVIN1.
The MOSFET drivers in the TA0102A are operated from voltages obtained from VN12 and LO1COM
for the low-side driver, and VBOOT (generated internal to the TA0102A) and HO1COM for the highside. Only N-Channel MOSFETs are required for both the top and bottom of the half bridge. VN12
must be a stable 12V above VSNEG. The gate resistors, RG, are used to control MOSFET slew rate
and thereby minimize voltage overshoots.
Over- and Under-Voltage Protection
The TA0102A senses the power rails through VSPOS and VSNEG for over- and under-voltage
conditions. The over- and under-voltage limits are Vo and Vu respectively as specified in the
Electrical Characteristics table. If the supply voltage exceeds Vo or drops below Vu, the TA0102A
shuts off the output stages of the amplifiers and asserts a logic level high on HMUTE. The removal
of the over-voltage or under-voltage condition returns the TA0102A to normal operation and returns
HMUTE to a logic level low. Please note that the limits specified in the Electrical Characteristics
table are at 25°C and these limits may change over temperature.
Over-current Protection
The TA0102A has over-current protection circuitry to protect itself and the output transistors from
short-circuit conditions. The TA0102A uses the voltage across a resistor, RS (measured via
OCS1H+, OCS1H-, OCS1L+ and OCS1L-), that is in series with each output MOSFET to detect an
over-current condition. RS and ROCR are used to set the over-current threshold. The OCS pins must
be Kelvin connected for proper operation. See “Circuit Board Layout” in Applications Information for
details. An over-current condition will cause the TA0102A to shut off the output stages of the
amplifiers and supply a logic level high on HMUTE. The occurrence of an over-current condition is
latched in the TA0102A and can be cleared by toggling the MUTE input or cycling power.
Overload
When logic low, the OVERLOADB pin indicates that the level of the input signal has overloaded the
amplifier and that the audio output signal is starting to distort. The OVERLOADB signal is active
only when an overload is present. The OVERLOADB signal can be used to control a distortion
indicator light or LED through a simple buffer circuit.
Mute
When a logic high signal is supplied to MUTE, both amplifier channels are muted (both high- and
low-side transistors are turned off) and a logic level high is output on the HMUTE pin. When a logic
level low is supplied to MUTE, both amplifiers are fully operational and a logic level low is supplied
on HMUTE. There is a delay of approximately 200 milliseconds between the de-assertion of MUTE
and the un-muting of the TA0102A.
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Application Information
Amplifier Gain and Input Resistor Selection
The value of the input resistor, RIN, is based on the required voltage gain, AV, of the amplifier
according to:
AV = 387 x103/(RIN + 5000)
where RIN = Input resistor value in ohms.
Input Capacitor Selection
CIN can be calculated once a value for RIN has been determined. CIN and RIN determine the input
low-frequency pole. Typically this pole is set at 10Hz. CIN is calculated according to:
CIN = 1/((2π x fP)(RIN + 5000))
where:
RIN = Input resistor value in ohms.
fP = Input low frequency pole (typically 10Hz).
DC Offset Adjust
While the DC offset voltages that appear at the speaker terminals of a TA0102A amplifier are
typically small, Tripath recommends that any offsets during operation be nulled out of the amplifier
with a circuit like the one shown connected to IN1 and IN2 in the Test/Application Circuit. Nulling
should be performed with the inputs shorted to ground.
It should be noted that even after nulling, the DC voltage on the output of a TA0102A amplifier with
no load in mute mode is approximately 2.5V. This offset does not need to be nulled. The output
impedance of the amplifier in mute mode is approximately 10 KOhms. This means that the 2.5V
drops to essentially zero when a typical load is connected.
Supply Voltage and Output Power
The relationship between the bipolar power supply voltage needed, VS, for a given RMS output
power, POUT, into a given load, RL, at a given level of THD (total harmonic distortion) is approximated
by:
VS = (2 x RL x POUT) 0.5/(K x RL/(RL + RON + RS + RCOIL))
where:
RON = The at-temperature RDSON of the output transistors, M.
RCOIL = Resistance of the output filter inductor.
RS = Sense Resistor
K = THD Factor, a number fixed by the algorithms in the TA0102A’s signal processor that
provides the relationship between THD at full output power of the amplifier and VS. K
corresponds to THD at full output power as follows:
THD
0.1%
1%
10%
K
0.83
0.95
1.09
Typical measurement graphs of POUT versus supply voltage for various levels of THD are also
included in this data sheet to help determine the supply voltage.
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Tripath Technology, Inc. - Technical Information
Bridged Operation
Note that the two channels of a TA0102A amplifier can be used to provide a single, bridged amplifier
of almost four times the output power of one of the single-ended amplifier channels. To configure a
bridged amplifier, the input to one TA0102A channel must be the inverted signal of the input to the
other channel.
Low-frequency Power Supply Pumping
A potentially troublesome phenomenon in single-ended switching amplifiers is power supply
pumping. This is caused by current from the output filter inductor flowing into the power supply
output filter capacitors in the opposite direction as a DC load would drain current from them. Under
certain conditions (usually low-frequency input signals), this current can cause the supply voltage to
“pump” (increase in magnitude) and eventually cause over-voltage/under-voltage shut down.
Moreover, since over/under-voltage are not “latched” shutdowns, the effect would be an amplifier
that oscillates between on and off states. If a DC offset on the order of 0.3V is allowed to develop on
the output of the amplifier (see “DC Offset Adjust”), the supplies can be boosted to the point where
the amplifier’s over-voltage protection triggers.
One solution to the pumping issue is to use large power supply capacitors to absorb the pumped
supply current without significant voltage boost. The low frequency pole used at the input to the
driver determines the value of the supply capacitor required. This works for AC signals only.
Another solution to the supply pumping problem uses the fact that music has low frequency
information that is correlated in both channels (it is in phase). This information can be used to
eliminate boost by putting the two channels of a TA0102A amplifier out of phase with each other.
This works because each channel is pumping out of phase with the other, and the net effect is a
cancellation of pumping currents. The phase of the audio signals needs to be corrected by
connecting one of the speakers in the opposite polarity as the other channel.
CONTACT INFORMATION
World Wide Sales Offices
United States & Europe
SE Asia & China
Japan & Korea
Jim Hauer
Eugene Hsu
Osamu Ito
[email protected]
[email protected]
[email protected]
408.567.3089
886.2.2653.7428
81.42.334.2433
TRIPATH TECHNOLOGY, INC
3900 Freedom Circle
Santa Clara
CA 95054
408.567.3000
www.tripath.com
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