Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on TK2019 STEREO 20W (4Ω) CLASS-T™ DIGITAL AUDIO AMPLIFIER DRIVER USING DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY Preliminary Information Revision 2.1 – October 2003 GENERAL DESCRIPTION The TK2019 (TC2001/TPS1035 chipset) is a stereo single ended 20W continuous average power per channel, Class-T Digital Audio Power Amplifier using Tripath’s proprietary Digital Power ProcessingTM technology. The TK2019 chipset consists of 1 TC2001 and 2 TPS1035’s to obtain a single ended stereo configuration. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers. APPLICATIONS 5.1-Channel powered DVD player Mini/Micro Component Systems Home Theater Stereo applications (4Ω / 8Ω) BENEFITS Single Supply Operation Very High Efficiency Wide Dynamic Range Compact layout 1 FEATURES Class-T Architecture High Output power 20W @ 4Ω, 10% THD+N Single Ended 11W @ 8Ω, 10% THD+N Single Ended Audiophile Quality Sound 0.03% THD+N @ 11W 4Ω Single Ended 0.03% THD+N @ 6W 8Ω Single Ended High Efficiency 92% @ 20W 4Ω Single Ended 93% @ 11W 8Ω Single Ended Dynamic Range >100 dB TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on A B S O L U T E M A X I M U M R A T I N G S – T C 2 0 0 1 (Note 1) Value UNITS V5 SYMBOL 5V Power Supply PARAMETER 6 V Vlogic Input Logic Level V5+0.3V V TA Operating Free-air Temperature Range -40 to 85 °C TSTORE Storage Temperature Range -55 to 150 °C TJMAX Maximum Junction Temperature 150 °C ESDHB ESD Susceptibility – Human Body Model (Note 2), all pins 2000 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. See the table below for Operating Conditions. Note 2: Human body model, 100pF discharged through a 1.5KΩ resistor. A B S O L U T E M A X I M U M R A T I N G S – T P S 1 0 3 5 (Note 1) SYMBOL PARAMETER Value UNITS VCC Power Supply 26 V Vlogic Input Logic Level 5.5 V TA Operating Free-air Temperature Range -40 to 85 °C TSTORE Storage Temperature Range -40 to 150 °C TJMAX Maximum Junction Temperature 150 °C ESDHB ESD Susceptibility – Human Body Model (Note 2), all pins except 1, 8 Pins 1, 8 2000 400 V ESDMM ESD Susceptibility – Machine model (Note 3), all pins 200 V Note 3: Machine model, 220pF – 240pF discharged through all pins. OPERATING CONDITIONS – TC2001 MIN. TYP. MAX. V5 SYMBOL Supply Voltage PARAMETER 4.5 5 5.5 VHI Logic Input High V5-1.0 VLO Logic Input Low TA Operating Temperature Range UNITS V V 1 V -40 25 85 °C MIN. TYP. MAX. UNITS 25 V OPERATING CONDITIONS – TPS1035 SYMBOL PARAMETER VCC Power Supply 8 VHI Logic Input High VLO Logic Input Low TA Operating Temperature Range TBD -40 V 25 TBD V 85 °C THERMAL CHARACTERISTICS TC2001 SYMBOL PARAMETER Junction-to-ambient Thermal Resistance (still air) θJA 2 Value UNITS 80 °C/W TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on TPS1035 SYMBOL Value UNITS θJA Junction-to-Ambient Thermal Resistance PARAMETER 50 °C/W θJC Junction-to-case Thermal Resistance 8 °C/W ELECTRICAL CHARACTERISTICS – TC2001 SYMBOL PARAMETER I5 Supply Current fsw Switching Frequency (adjustable via CFB) VIN Input Sensitivity VOUTHI High Output Voltage VOUTLO Low Output Voltage RIN Input Impedance MIN. 600 TYP. MAX. mA 650 kHz 0 1.5 V5-0.5 V V 100 Input DC Bias UNITS 60 mV 2 kΩ 2.5 V ELECTRICAL CHARACTERISTICS – TK2019 TA = 25 °C. See Application/Test Circuit. Unless otherwise noted, the supply voltage is VDD = 24V. SYMBOL VIH PARAMETER Quiescent Current (No load, Mute = 0V) Mute Supply Current (No load, TC2001 Mute = 5V, TPS1035 Sleep = 5V) High-level input voltage (MUTE) IIH = See Mute Control Section VIL Low-level input voltage (MUTE) IIL = See Mute Control Section ISC IVPPSENSE Short circuit current limit VPPSENSE Threshold Currents VDD = 24V, T=25oC Over-voltage turn on (muted) Over-voltage turn off (mute off) Under-voltage turn off (mute off) Under-voltage turn on (muted) Over-voltage turn on (muted) Over-voltage turn off (mute off) Under-voltage turn off (mute off) Under-voltage turn on (muted) Iq IMUTE VVPPSENSE Threshold Voltages with RVPPSENSE = 187KΩ (Note 4, Note 5) VDD = 24V V5 = 5V CONDITIONS MIN. TYP. 20 27 VDD = 24V V5 = 5V 2 7 MAX. 60 µA mA 3.5 V 1.0 138 62 25.8 11.6 UNITS mA mA 7.5 162 154 79 72 30.3 28.8 14.8 13.5 178 87 33.3 16.3 V A µA µA µA µA V V V V Note 4: These supply voltages are calculated using the IVPPSENSE values shown in the Electrical Characteristics table. The typical voltage values shown are calculated using a RVPPSENSE value of 187kohm without any tolerance variation. The minimum and maximum voltage limits shown include either a +1% or –1% (+1% for Over-voltage turn on and Under-voltage turn off, -1% for Over-voltage turn off and Under-voltage turn on) variation of RVPPSENSE off the nominal value. These voltage specifications are examples to show both typical and worst case voltage ranges for a given RVPPSENSE resistor values of 187kohm. Please refer to the Application Information section for a more detailed description of how to calculate the over and under voltage trip voltages for a given resistor value. Note 5: The fact that the over-voltage turn on specifications exceed the absolute maximum of 26V for the TK2019 does not imply that the part will work at these elevated supply voltages. It also does not imply that the TK2019 is tested or guaranteed at these supply voltages. The supply voltages are simply a calculation based on the process spread of the IVPPSENSE currents (see note 7). The supply voltage must be maintained below the absolute maximum of 26V or permanent damage to the TK2019 may occur. 3 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on PERFORMANCE CHARACTERISTICS – TK2019 TA = 25 °C. Unless otherwise noted, VDD = 24V, f=1kHz, and the measurement bandwidth is 20kHz. SYMBOL POUT PARAMETER Output Power (Continuous Average/Channel) (Note 13) THD + N Total Harmonic Distortion Plus Noise IHF-IM IHF Intermodulation Distortion SNR Signal-to-Noise Ratio CS Channel Separation AV Amplifier Gain AVERROR Channel to Channel Gain Error η Power Efficiency eN Output Noise Voltage 4 CONDITIONS VDD = 24V, RL = 8Ω THD+N = 0.03% THD+N = 1.0% THD+N = 10.0% VDD = 24V, RL = 4Ω THD+N = 0.03% THD+N = 1.0% THD+N = 10.0% POUT = 5W/Channel, RL = 8Ω VCC = 24V POUT = 10W/Channel, RL = 4Ω VCC = 24V 19kHz, 20kHz, 1:1 (IHF), RL = 4Ω POUT = 2.5W/Channel A-Weighted 0dB = 10W/Channel, RL = 8Ω 0dB = 6.5W, RL = 4Ω, f=1kHz POUT = 5W/Channel, RL = 8Ω, See Application / Test Circuit POUT = 5W/Channel, RL = 8Ω See Application / Test Circuit POUT = 11W/Channel, RL = 8Ω POUT = 20W/Channel, RL = 4Ω A-Weighted, input AC grounded, RFBC = 9.1kΩ , RFBB = 1kΩ MIN. TYP. MAX. UNITS 6 8 11 W W W 11 15 20 0.025 W W W % 0.025 % 0.01 % 102 dB 72 dB 10 V/V 0.5 93 92 75 dB % % µV TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on TC2001 AUDIO SIGNAL PROCESSOR PIN DESCRIPTIONS Pin 1 Function BIASCAP 2, 6 FBKGND2, FBKGND1 DCMP 3 4, 7 Description Bandgap reference times two (typically 2.5VDC). Used to set the common mode voltage for the input op amps. This pin is not capable of driving external circuitry. Ground Kelvin feedback (Channels 1 & 2) Internal mode selection. This pin must be grounded for proper device operation. Switching feedback (Channels 1 & 2) 5 8 FBKOUT2, FBKOUT1 VPWR HMUTE 9, 12 10, 11 13 14, 16 15 17 Y1, Y2 Y1B, Y2B NC OCD2, OCD1 REF VNNSENSE 18 19 OVRLDB VPPSENSE 20 21 22, 27 23, 28 AGND V5 OAOUT1, OAOUT2 INV1, INV2 24 MUTE 25, 26 BBM1, BBM0 Test pin. Must be left floating. Logic output. A logic high indicates both amplifiers are muted, due to the mute pin state, or a “fault”. Non-inverted switching modulator outputs. Inverted switching modulator outputs. No connect Over Current Detect pins. These pins should be tied to ground. Internal bandgap reference voltage; approximately 1.2 VDC. Negative supply voltage sense input. This pin is used for both over and under voltage sensing for the VNN supply. Not used on the TK2019. Connect this pin to AGND through a 10kΩ resistor. A logic low output indicates the input signal has overloaded the amplifier. Positive supply voltage sense input. This pin is used for both over and under voltage sensing for the VPP supply. Analog Ground. 5 Volt power supply input. Input stage output pins. Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with approximately 2.4VDC bias. When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. Ground if not used. Break-before-make timing control to prevent shoot-through in the output MOSFETs. When using with the TPS1035, these pins should both be set to 5V. TC2001 AUDIO SIGNAL PROCESSOR PINOUT 28-pin SOIC (Top View) BIASCAP 1 28 INV2 FBKGND2 2 27 OAOUT2 DCMP 3 26 BBM0 FBKOUT2 4 25 BBM1 VPW R 5 24 MUTE FBKGND1 6 23 INV1 FBKOUT1 7 22 OAOUT1 HMUTE 8 21 V5 AGND 9 20 Y1B 10 19 VPPSENSE Y2B 11 18 OVRLDB Y1 5 Y2 12 17 VNNSENSE NC 13 16 OCD1 OCD2 14 15 REF TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on TPS1035 POWER STAGE PIN DESCRIPTIONS Pin 1 2 3 4 5 6 Function INPUT VDD OUTPUT PGND VBOOT SLEEP 7 BYPASS 8 FAULT Description Input pin for power stage. Positive supply pin. Output pin. Power Ground pin. Bootstrapped voltage to supply drive to gate of high-side output MOSFET. Sleep Input pin. When set to logic level high, sleep mode is enabled. When set to logic level low (grounded), sleep mode is disabled. Bypass pin for the gate drive power supply. The gate drive for the output mosfets are internally generated from VDD. This pin should be connected to ground through a 0.1uF capacitor. This pin must be connected to the Fault pin (pin 8) through a 27kΩ resistor. Fault Output pin. During normal operation this pin is high. If an overcurrent or over temperature condition is detected the fault pin will become low. This pin must be connected to the Bypass pin (pin 7) through a 27kΩ resistor. TPS1035 POWER STAGE PINOUT (Top view with heat slug down) 8-pin SOIC with Heatslug (Top View) 6 INPUT 1 8 FAULT VDD 2 7 BYPASS OUTPUT 3 6 SLEEP PGND 4 5 VBOOT TK2019 – MC/2.1/10-03 7 RI 20K Ω RI 20K Ω V5 COF 0.1uF R OFB 1M Ω 25 3 BBM1 DCOMP A GND + - V5 V5 200K Ω 2.5V A GND + - V5 A GND V5 0Ω 13 4 2 OCD2 14 NC C FB 560pF FBKGND2 FBKOUT2 A GND (Pin 28) Y 2B Y2 HMUTE CFB 390pF FBKGND1 FBKOUT1 A GND (Pin 28) OCD1 Y 1B Y1 11 12 8 6 7 16 A nalog Ground Pow er Ground Proces s in g & Mo du lation Proces s in g & Mo du lation 10 9 * The va lu e s o fth es e co m p on e nts m u s t b e a dju s te d b as e d o n s u pp lyvo lta ge ra ng e.Se e App lication Info rm a tio n. 19 V PPSENSE 17 V NNSENSE 26 BBM0 C OF 0.1uF ROFB 1MΩ 28 27 V P2 IN2 15 24 1 REF MUTE RV N N 10K Ω *R V P P 1 187K Ω , 1% V 5 (Pin 27) *R V P P 2 187K Ω , 1% V PP ROFA 50K Ω Of f set Trim Circuit RF 20K Ω 22 20 21 INV 1 23 V P1 BIA SCA P RR E F 8.25K Ω , 1% 5V A GND RF 20KΩ CS 0.1uF CA 0.1uF V 5 (Pin 27) CI 2.2uF + ROFA 50K Ω Of f set Trim Circuit V 5 (Pin 27) CI 2.2uF + 5V TC2001 *R FB B 1.0K Ω *RFB B 1.0K Ω 5V *RFB B 1.0K Ω RC 100K Ω CBYPASS 0.1uF + DP 1N914 CB 0.1uF RB 27K Ω DC H MBR0520L CB Y P A S S 10.0uF HMUTE RB 27K Ω DC H MBR0520L DB OOT 5.1V Zener Diode R OFF 100K Ω 24V R B IA S 1 4.64KΩ Q1 2N3906 5V Q2 2N3906 24V RP 10K Ω RH M U T E 4.99K Ω RB IA S 2 54.9K Ω *R F B C 9.1K Ω RB A S E 1K Ω *R F B C 9.1K Ω *R FB B 1.0K Ω *R F B C 9.1K Ω *R F B C 9.1K Ω CB 0.1uF INPUT SLEEP FA ULT BY PA SS INPUT SLEEP FA ULT BY PA SS 1 6 8 7 1 6 8 7 DB OOT 1 MURS105T3 Input Logic/ Level Shift Internal Regulator TPS1035 Input Logic/ Level Shift Internal Regulator TPS1035 DB OOT 1 MURS105T3 V DD V BOOT V DD V BOOT 4 PGND 24V CB OOT 0.22uF DS MU R S1 05T3 DS MU R S1 05T3 24V CB OOT 0.22uF CH B R 0.1uF DB OOT 2 6.2V Zener Diode MU R S1 05T3 DS CH B R 0.1uF DB OOT 2 6.2V Zener Diode DS MU R S1 05T3 24V 3 OUTPUT 2 5 DC 1N914 RD 100K Ω 4 PGND 3 OUTPUT 2 5 DC 1N914 24V CO 0.22uF LO 10uH CO 0.22uF LO 10uH 24V CZ 0.22uF RZ 20 Ω , 2 W R OUT 1 8.45K Ω CZ 0.22uF RZ 20 Ω , 2 W + COUT 1000uF COUT 1000uF ROUT 2 20K Ω 24V ROUT 1 8.45KΩ R OUT 2 20KΩ + RD 100K Ω RL 4 Ω or 8 Ω RL 4 Ω or 8 Ω Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on APPLICATION / TEST DIAGRAM TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on E X T E R N A L C O M P O N E N T S D E S C R I P T I O N (Refer to the Application/Test Circuit) Components RI RF CI RFBB RFBC CFB ROFB ROFA RREF CS CZ RZ LO CO CHBR CBOOT DBOOT CDM 8 Description Inverting input resistance to provide AC gain in conjunction with RF. This input is biased at the BIASCAP voltage (approximately 2.5VDC). Feedback resistor to set AC gain in conjunction with RI. Please refer to the Amplifier Gain paragraph, in the Application Information section. AC input coupling capacitor, which, in conjunction with RI, forms a high pass filter at fC = 1 (2πRICI ) . Feedback divider resistor connected to AGND. The value of this resistor depends on the supply voltage setting and helps set the TK2019 gain in conjunction with RI, RF, RFBA, and RFBC. Please see the Modulator Feedback Design paragraphs in the Application Information Section. Feedback resistor connected from either the OUT1A/OUT2A to FBKOUT1/FBKOUT2 or OUT1B/OUT2B to FBKGND1/FBKGND2. The value of this resistor depends on the supply voltage setting and helps set the TK2019 gain in conjunction with RI, RF, RFBA, and RFBB. It should be noted that the resistor from OUT1/OUT2 to FBKOUT1/FBKOUT2 must have a power rating of greater than PDISS = VPP2 (2RFBC) . Please see the Modulator Feedback Design paragraphs in the Application Information Section. Feedback delay capacitor that both lowers the idle switching frequency and filters high frequency noise from the feedback signal, which improves amplifier performance. The value of CFB should be offset between channel 1 and channel 2 so that the idle switching difference is greater than 40kHz. Please refer to the Application / Test Circuit. Potentiometer used to manually trim the DC offset on the output of the TK2019. Resistor that limits the manual DC offset trim range and allows for more precise adjustment. Bias resistor. Locate close to pin 15 and ground at pin 20. Supply decoupling for the power supply pins. For optimum performance, these components should be located close to the TC2001/TPS1035 and returned to their respective ground as shown in the Application/Test Circuit. Zobel capacitor, which in conjunction with RZ, terminates the output filter at high frequencies. Use a high quality film capacitor capable of sustaining the ripple current caused by the switching outputs. Zobel resistor, which in conjunction with CZ, terminates the output filter at high frequencies. The combination of RZ and CZ minimizes peaking of the output filter under both no load conditions or with real world loads, including loudspeakers which usually exhibit a rising impedance with increasing frequency. The recommended power rating is 1 Watt. Output inductor, which in conjunction with CO, demodulates (filters) the switching waveform into an audio signal. Forms a second order filter with a cutoff frequency of f C = 1 ( 2 π L O C O ) and a quality factor of Q = R L C O L O C O . Output capacitor, which, in conjunction with LO, demodulates (filters) the switching waveform into an audio signal. Forms a second order low-pass filter with a cutoff frequency of f C = 1 ( 2 π L O C O ) and a quality factor of Q = R L C O L O C O . Use a high quality film capacitor capable of sustaining the ripple current caused by the switching outputs. Electrolytic capacitors should not be used. High-frequency bypass capacitor for VDD – GND on each supply pin. A 35V rating is required for this component. Boot strap capacitor that enables the charge pump for the high side gate drive for the internal H-bridge. Bootstrap diode. This diode charges up the bootstrap capacitor when the output is at ground to drive the high side gate circuitry. A fast or ultra fast recovery diode is recommended for the bootstrap circuitry. In addition, the bootstrap diode must be able to sustain the entire VDD voltage. Thus a 50V (or greater) diode should be used. Differential mode capacitor that reduces residual switching noise. TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on CB DS RVPP1 RVPP2 RVNN CA RHMUTE DCH Q1 Q2 RBASE RC ROFF DP DZ RBIAS1 RBIAS2 RD DC DBOOT2 ROUT1 ROUT2 RB COUT 9 Bypass capacitor for the internal regulator that powers the gate drive circuitry. MOSFET protection diode. This diode absorbs any high frequency overshoots or undershoots caused by the output inductor LO during high output current conditions. In order for this diode to be effective it must be connected directly to the drain of the topside MOSFET (pin 2) and the output (pin 3) and source of bottom side MOSFET (pin 4) and the output (pin 3). An ultra fast recovery diode that can sustain the entire VCC voltage should be used here. Thus a 50V or greater diode must be used. Overvoltage and undervoltage sense resistor for the positive supply (VDD). Please refer to the Electrical Characteristics Section for the trip points as well as the hysteresis band. Also, please refer to the Over / Under-voltage Protection section in the Application Information for a detailed discussion of the internal circuit operation and external component selection. Secondary overvoltage and undervoltage sense resistor for the positive supply (VDD). This resistor accounts for the internal VPPSENSE bias of 2.5V. Nominal resistor value should be equal to that of RVPP1. Please refer to the Over / Undervoltage Protection section in the Application Information for a detailed discussion of the internal circuit operation and external component selection. Not used on TK2019. Connect this pin to AGND through a 10kΩ resistor. BIASCAP decoupling capacitor. Should be located close to pin 1 of the TC2001 and grounded at pin 20 of the TC2001. Base resistor to limit the current output from the HMUTE pin. Diode to keep the Bypass pin (pin 7) of the TPS1035 charged to 5V while HMUTE is high. This diode should be a Schottky diode. PNP transistor to keep the Bypass pin (pin 7) of the TPS1035 charged to 5V whenever the HMUTE is high. PNP transistor to keep HMUTE high and mute the amplifier if the 5V supply is turned off before the 24V supply. If the amplifier is not muted and the 5V supply is turned off before the 24V supply, the amplifier will have an audible pop. Base resistor for limiting the current entering the base for Q2. Pull down resistor to pull the collector of Q2 to ground if both the 5V supply and the 24V supply is on and Q2 is off. Resistor that limits the current from the 24V supply going into the 5.1V zener diode (DZ). Diode in series with the collector of Q2 to pull HMUTE high if the 5V supply is turned off before the 24V supply. 5.1V zener diode to keep the emitter of Q2 to 5.1V so that when Q2 is on the HMUTE pin will not exceed 5V. Bias resistor to bias the FBKGND pins (pins 2 and 8 on TC2001) to 2.5V. Typically used value is 4.64kΩ. Second bias resistor to bias the FBKGND pins (pins 2 and 8 on TC2001) to 2.5V. The value of RBIAS2 when placed in parallel with RFBB and RFBC should have equivalent resistance to RBIAS1. Please see the Modulator Feedback Design paragraphs in the Application Information Section. An equivalent equation would be RBIAS1 = 1/ (RFBB + RFBC) + 1/ RBIAS2 . Resistor to limit the current flowing into diode DC. Diode to connect the VBOOT pin (pin 5 of the TPS1035) to the 24V supply so that the VBOOT pin is charged up while the TPS1035 is muted. This helps prevent clicks and pops while the sleep is disabled on the TPS1035. Protection diode for the VBOOT pin (pin 5 of the TPS1035) so that the VBOOT pin will never exceed 6.2V. Bias resistor to keep the output capacitor COUT charged to VDD/2. Typically used value is 8.45kΩ. Bias resistor used in conjunction with ROUT1 to keep the output capacitor COUT charged to VDD/2. Typically used value is 20kΩ. For proper operation of the TPS1035, the Fault pin (pin 8) must be connected to the Bypass pin (pin 7) through a 27kohm resistor. Output capacitor in series with the output to block DC current to flow to the output load. This capacitor will form a high pass filter with output load with a cutoff frequency at fC = 1 (2πRICI ) . Where R is the resistive value of the output load. TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on TYPICAL PERFORMANCE CHARACTERISTICS THD+N vs Frequency THD+N vs O UTPUT PO W ER 10 10 f = 1kHz VDD = 24V BW = 22Hz - 22kHz AES17 Filter 5 5 2 2 RL = 8Ω 1 THD+N (% ) RL = 4Ω 1 R L = 2Ω 0.5 f = 1kHz VDD = 24V POUT = 5W /Channel BW = 22Hz - 22kHz % 0.2 0.5 0.2 R L = 4Ω 0.1 0.1 0.05 0.05 0.02 R L = 8Ω 0.01 0.02 0.005 20 0.01 1 2 3 4 5 6 7 8 9 10 20 30 40 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) 50 W Intermodulation Distortion Noise Floor +0 +0 VDD = 24V POUT = 2.5W /Channel R L = 4Ω 19kHz, 20kHz 1:1 0dB = 3.2Vrm s -10 -20 -30 -12 -24 VDD = 24V POUT = 0W /Channel RL = 4Ω A V = 10V/V BW = 22Hz - 22kHz -36 Am plitude (dBV) Amplitude (dBr) -40 -50 -60 -70 -80 -48 -60 -72 -84 -90 -96 -100 -108 -110 -120 60 100 200 500 1k 2k Frequency (Hz) 5k 10k 20k -120 20 30k 50 100 500 1k Frequency (Hz) 5k 10k 20k 100 VDD = 24V POUT = 6.5W /Channel RL = 4Ω 0dB = 5.1Vrm s BW = 22Hz - 22kHz -10 -20 -30 8 OHMS 90 80 4 OHMS 70 -40 Efficiency (%) -50 -60 -70 -80 60 50 40 30 VDD = 24V THD+N <10% -90 20 -100 10 -110 0 -120 0 20 10 2k Efficiency vs Output Power Channel Seperation vs Frequency +0 Am plitude (dBr) 200 50 100 200 500 1k Frequency (Hz) 2k 5k 10k 20k 5 10 15 20 Output Power (W) TK2019 – MC/2.1/10-03 25 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on APPLICATION INFORMATION TK2019 Basic Amplifier Operation The TC2001 is a 5V CMOS signal processor that amplifies the audio input signal and converts the audio signal to a switching pattern. This switching pattern is spread spectrum with a typical idle switching frequency of about 700kHz. The switching patterns for the two channels are not synchronized and the idle switching frequencies should differ by at least 40kHz to avoid increasing the audio band noise floor. The idle frequency difference can be accomplished by offsetting the value of CFB for each channel. Typical values of CFB are 390pF for channel 1 and 560pF for channel 2. The TPS1035 is a MOSFET output stage that level-shifts the signal processor’s 5V switching patterns to the power supply voltages and drives the power MOSFETs. The power MOSFETs are N-channel devices configured in half-bridges and are used to supply power to the output load. The outputs of the power MOSFETs must be low pass filtered to remove the high frequency switching pattern. A residual voltage from the switching pattern will remain on the speaker outputs when the recommended output LC filter is used, but this signal is outside of the audio band and will not affect audio performance. Circuit Board Layout The TK2019 is a power (high current) amplifier that operates at relatively high switching frequencies. The output of the amplifier switches between VDD and GND at high speeds while driving large currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output inductanor. To avoid subjecting the TK2019 to potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is recommended that Tripath’s layout and application circuit be used for all applications and only be deviated from after careful analysis of the effects of any changes. The following components are important to place near their associated TC2001/TPS1035 pins and are ranked in order of layout importance, either for proper device operation or performance considerations. - The capacitors CHBR provide high frequency bypassing of the amplifier power supplies and will serve to reduce spikes across the supply rails. CHBR should be kept within 1/8” (3mm) of the VCC pins. Please note that the four VDD pins must be decoupled separately. In addition, the voltage rating for CHBR should be 35V as this capacitor is exposed to the full supply range. - CFB removes very high frequency components from the amplifier feedback signals and lowers the output switching frequency by delaying the feedback signals. In addition, the value of CFB is different for channel 1 and channel 2 to keep the average switching frequency difference greater than 40kHz. This minimizes in-band audio noise. - To minimize noise pickup and minimize THD+N, RFBC should be located as close to the TC2001 as possible. Make sure that the routing of the high voltage feedback lines is kept far away from the input op amps or significant noise coupling may occur. It is best to shield the high voltage feedback lines by using a ground plane around these traces as well as the input section. In general, to enable placement as close to the TC2001/TPS1035, and minimize PCB parasitics, the capacitors listed above (with the exception of the bulk capacitors) should be surface mount types. 11 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on Some components are not sensitive to location but are very sensitive to layout and trace routing. - To maximize the damping factor and reduce distortion and noise, the modulator feedback connections should be routed directly to the pins of the output inductors, LO. - The modulator feedback resistors should all be grounded together through a direct connection to pin 20 on the TC2001. TK2019 Grounding Proper grounding techniques are required to maximize TK2019 functionality and performance. Parametric parameters such as THD+N, noise floor and cross talk can be adversely affected if proper grounding techniques are not implemented on the PCB layout. The following discussion highlights some recommendations about grounding both with respect to the TK2019 as well as general “audio system” design rules. The TK2019 is divided into two sections: the input section, and the output (high power) section. On the TK2019 evaluation board, the ground is also divided into distinct sections, one for the input and one for the output. To minimize ground loops and keep the audio noise floor as low as possible, the input and output ground must be only connected at a single point. Depending on the system design, the single point connection may be in the form of a ferrite bead or a PCB trace. Modulator Feedback Design The modulator converts the signal from the input stage to the high-voltage output signal. The optimum gain of the modulator is determined from the maximum allowable feedback level for the modulator and maximum supply voltage for the power stage. Depending on the maximum supply voltage, the feedback ratio will need to be adjusted to maximize performance. The values of RFBB and RFBC (see explanation below) define the gain of the modulator. Once these values are chosen, based on the maximum supply voltage, the gain of the modulator will be fixed even with as the supply voltage fluctuates due to current draw. For the best signal-to-noise ratio and lowest distortion, the maximum modulator feedback voltage should be approximately 4Vpp. This will keep the gain of the modulator as low as possible and still allow headroom so that the feedback signal does not clip the modulator feedback stage. The modulator feedback resistors are: RFBB = User specified; typically 1kΩ V CC ∗ R FBB R FBC = 4V − R FBB Modulator Feedback Bias Resistors RBIAS1 and RBIAS2 set the bias of node 1 to VDD/2. The equivalent resistance of RBIAS2, RFBC1, RFBB1, RFBC2, and RFBB2 should be the same as RBIAS1. 12 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on Node 1 R BIAS1 4.64K Ω R FBC1 9.1K Ω 6 R FBB1 1.0K Ω TC2001 24V R BIAS2 54.9K Ω C BYPASS 0.1uF + C BYPASS 10.0uF R FBC2 9.1K Ω 2 R FBB2 1.0K Ω Figure 1: Modulator Feedback Bias Resistors The equivalent formula to calculate RBIAS1 is: 1 RBIAS1 = 1 1 + RFB RBIAS2 Where RFB is: 1 1 1 = + RFB RFBC1 + RFBB1 RFBC2 + RFBB2 TK2019 Amplifier Gain The gain of the TK2019 is the product of the input stage gain and the modulator gain. Please refer to the sections, Input Stage Design, and Modulator Feedback Design, for a complete explanation of how to determine the external component values. AV TK2019 AV = AV ≈ TK2019 INPUT STAGE * AV MODULATOR R F R FBC + R FBB RI R FBB For example, using a TK2019 with the following external components, RI = 20kΩ RF = 20kΩ RFBB = 1kΩ RFBC = 9.1kΩ AV TK2019 ≈ 20k Ω 20k Ω V 9.1k Ω + 1k Ω ≈ 10 1k Ω V Please note that Output 1 and Output 2, as shown in the Application/Test Diagram, are out of phase with respect to the input signal. This phase reversal can be eliminated by connecting the negative terminals of the speakers to Output 1 and Output 2 and the positive speaker terminals to ground. 13 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on Input Stage Design The TC2001 input stage is configured as an inverting amplifier, allowing the system designer flexibility in setting the input stage gain and frequency response. Figure 2 shows a typical application where the input stage is a constant gain inverting amplifier. The input stage gain should be set so that the maximum input signal level will drive the input stage output to 4Vpp. TC2001 OAOUT1 CI V5 RF RI INV1 INPUT1 + BIASCAP AGND V5 + INV2 CI - RF RI INPUT2 OAOUT2 AGND Figure 2: Input Stage The gain of the input stage, above the low frequency high pass filter point, is that of a simple inverting amplifier: It should be noted that the input amplifiers are biased at approximately 2.5VDC. Thus, the polarity of CI must be followed as shown in Figure 1 for a standard ground referenced input signal AV INPUT STAGE = − RF RI Input Capacitor Selection CI can be calculated once a value for RI has been determined. CI and RI determine the input low frequency pole. Typically this pole is set below 10Hz. CI is calculated according to: CI = where: 1 2π f P R I RI = Input resistor value in ohms. fP = Input low frequency pole (typically 10Hz or below) 14 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on Mute Control When a logic high signal is supplied to MUTE, both amplifier channels are muted (both high- and lowside transistors are turned off). When a logic level low is supplied to MUTE, both amplifiers are fully operational. There is a delay of approximately 200 milliseconds between the de-assertion of MUTE and the un-muting of the TK2019. To ensure proper device operation, including minimization of turn on/off transients that can result in undesirable audio artifacts, Tripath recommends that the TK2019 device be muted prior to power up or power down of the 5V supply. The “sensing” of the V5 supply can be easily accomplished by using a “microcontroller supervisor” or equivalent to drive the TC2001 mute pin high when the V5 voltage is below 4.5V. This will ensure proper operation of the TK2019 input circuitry. A micro-controller supervisor such as the MCP101-450 from Microchip Corporation has been used by Tripath to implement clean power up/down operation. If turn-on and/or turn-off noise is still present with a TK2019 amplifier, the cause may be other circuitry external to the TK2019. While the TK2019 has circuitry to suppress turn-on and turn-off transients, the combination of power supply and other audio circuitry with the TK2019 in a particular application may exhibit audible transients. One solution that will completely eliminate turn-on and turn-off pops and clicks is to use a relay to connect/disconnect that amplifier from the speakers with the appropriate timing during power on/off. Output Voltage Offset The TK2019 does not have internal compensation for DC offset. The output offset voltage must be trimmed with a potentiometer at the INV1/INV2 pins of the TC2001. If the output offset voltage is not trimmed the output power of the TK2019 will be reduced. Trimming the output offset voltage also reduces the turn on pop. The output offset voltage should be measured before the load on the positive terminal of the output capacitor COUT. This voltage should be trimmed to VDD/2. Output Filter Design Tripath amplifiers generally have a higher switching frequency than PWM implementations, allowing the use of higher cutoff frequency filters and reducing the load dependent peaking/drooping in the 20kHz audio band. This is especially important for applications where the end customer may attach any speaker to the amplifier (as opposed to a system where speakers are shipped with the amplifier), since speakers are not purely resistive loads and the impedance they present changes over frequency and from speaker model to speaker model. An RC network, or “Zobel” (RZ, CZ) should be placed at the filter output to control the impedance “seen” by the TPS1035 when not attached to a speaker load. The TK2019 works well with a 2nd order, 80kHz LC filter with LO = 10uH and CO = 0.22uF and RZ = 20 Ohm/1W and CZ = 0.22uF. Output inductor selection is a critical design step. The core material and geometry of the output filter inductor affects the TK2019 distortion levels, efficiency, power dissipation and EMI output. Wound iron powder toroidal cores are the recommended inductor choice for the TK2019. Toroidal cores have less flux leakage compared to shielded bobbin or shielded SMD inductors, resulting in reduced EMI and improved channel separation. For typical applications we recommend the Micrometals Type-2 iron powder (Carbonyl-E) core. This core material has low permeability metal powder and a distributed air gap for increased energy storage capability. This allows for a small footprint with high peak current capability. Minimum and Maximum Supply Voltage Operating Range The TK2019 can operate over a wide range of power supply voltages from +7.5V to +25V. In order to optimize operation for either the low or high range, the user must select the proper values for RFBB, and RFBC as well as RVPP1 and RVPP2. 15 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on Over- and Under-Voltage Protection The TC2001 senses the power rails through external resistor networks connected to VPPSENSE. The over- and under-voltage limits are determined by the values of the resistors in the networks, as described in the table “Test/Application Circuit Component Values”. If the supply voltage falls outside the upper and lower limits determined by the resistor networks, the TC2001 shuts off the TPS1035 output stage. The removal of the over-voltage or under-voltage condition returns the TK2019 to normal operation. Please note that trip points specified in the Electrical Characteristics table are at 25°C and may change over temperature. The TC2001 has built-in over and under voltage protection for both the VPP and VNN supply rails. The nominal operating voltage will typically be chosen as the supply “center point.” This allows the supply voltage to fluctuate, both above and below, the nominal supply voltage. For the TK2019 only the VPP (VDD) supply rail will be sensed and the VNN sensing will not be used so pin 17 of the TC2001 will be shorted to ground. VPPSENSE (pin 19) performs the over and undervoltage sensing for the positive supply, VPP. When the current through RVPPSENSE goes below or above the values shown in the Electrical Characteristics section (caused by changing the power supply voltage), the TK2019 will be muted. VPPSENSE (pin 19) is internally biased at 2.5V. Once the supply comes back into the supply voltage operating range (as defined by the supply sense resistors), the TK2019 will automatically be unmuted and will begin to amplify. There is a hysteresis range on both the VPPSENSE and VNNSENSE pins. If the amplifier is powered up in the hysteresis band the TK2019 will be muted. Thus, the usable supply range is the difference between the overvoltage turn-off and under-voltage turn-off for both the VPP supply. It should be noted that there is a timer of approximately 200mS with respect to the over and under voltage sensing circuit. Thus, the supply voltage must be outside of the user defined supply range for greater than 200mS for the TK2019 to be muted. The equation for calculating RVPP1 is as follows: R VPP1 = VPP I VPPSENSE Set R VPP2 = R VPP1 . IVPPSENSE can be any of the currents shown in the Electrical Characteristics table for VPPSENSE. The two resistors, RVPP2 and RVNN2 compensate for the internal bias points. Thus, RVPP1 and RVNN1 can be used for the direct calculation of the actual VPP and VNN trip voltages without considering the effect of RVPP2 and RVNN2. Using the resistor values from above, the actual minimum over voltage turn off points will be: VPP MIN_OV_TUR N_OFF = R VPP1 × I VPPSENSE (MIN_OV_TU RN_OFF) The other three trip points can be calculated using the same formula but inserting the appropriate IVPPSENSE current value. As stated earlier, the usable supply range is the difference between the minimum overvoltage turn off and maximum under voltage turn-off for the VPP supply. VPP RANGE = VPP MIN_OV_TUR 16 N_OFF - VPP MAX_UV_TUR N_OFF TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on Protection Circuits The TK2019 is protected against over-current, over / under-voltage and over-temperature conditions. 5V Q1 2N3906 30K Ω + 22uF 3K Ω HMUTE Pin (Pin 8 of TC2001) SLEEP 3 TPS1035 8 FAULT FDLL914 1K Ω 5V 10K Ω 510K Ω Q2 2N3906 HMUTE Pin (Pin 8 of TC2001) MUTE Pin (Pin 24 of TC2001) 20K Ω SLEEP 3 TPS1035 8 FAULT FDLL914 1K Ω Figure 3 Figure 3 shows an overcurrent detection circuit that will mute the amplifier whenever the TPS1035 detects an overcurrent condition. The fault pin (pin 8 of the TPS1035) is an overcurrent indicator and is normally high (approximately 5.4V). When an overcurrent condition is detected this pin will go low (0V). When the fault pin goes low Q2 will turn on and pull the Mute pin of the TC2001 to 5V (if the switch is closed). This is due to the fact that the emitter voltage of Q2 is controlled by the HMUTE pin of the TC2001 through Q1. If HMUTE is low the emitter voltage of Q2 will be connected to the 5V line. If HMUTE is high Q2 is disabled and the mute pin will be pulled low through the 20kΩ resistor. In this circuit, whenever the switch is open the Mute pin will be pulled up to 5V and the amplifier will be muted. Whenever the MUTE pin on the TC2001 is high (or enabled) the HMUTE pin will also switch high. The sleep pin of the TPS1035 is controlled by HMUTE of the TC2001 so that during any mute or overcurrent condition the TPS1035 is placed in sleep mode. Whenever SLEEP is enabled, the FAULT pin is low and mutes the TC2001. Q1 controls the emitter voltage of Q2 through HMUTE so that whenever the SLEEP is enabled the TC2001 can become unmuted again. Over-temperature Protection An over-temperature fault occurs if the junction temperature of the TPS1035 exceeds approximately 165°C. The thermal hysteresis of the part is approximately 30°C, therefore the fault will automatically clear when the junction temperature drops below 135°C. HMUTE The HMUTE pin on the TC2001 is a 5V logic output that indicates various fault conditions within the device. These conditions include: over-current, overvoltage and undervoltage. The HMUTE output is high whenever a fault condition occurs or mute is enabled. The HMUTE pin is capable of directly driving an LED through a series 2kΩ resistor. 17 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on OVRLDB The OVRLDB pin is a 5V logic output that is asserted just at the onset of clipping. When low, it indicates that the level of the input signal has overloaded the amplifier resulting in increased distortion at the output. The OVRLDB signal can be used to control a distortion indicator light or LED through a transistor, as the OVRLDB cannot drive an LED directly. There is a 20K resistor on chip in series with the OVRLDB output. Performance Measurements of the TK2019 The TK2019 operates by generating a high frequency switching signal based on the audio input. This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an amplified version of the audio input. The frequency of the switching pattern is spread spectrum in nature and typically varies between 100kHz and 1MHz, which is well above the 20Hz – 20kHz audio band. The pattern itself does not alter or distort the audio input signal, but it does introduce some inaudible components. The measurements of certain performance parameters, particularly noise related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible noise components introduced by the TK2019 amplifier switching pattern will degrade the measurement. One feature of the TK2019 is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters degrade frequency response. The TK2019 Reference Board uses the Application/Test Circuit of this data sheet, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument. 18 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on PACKAGE INFORMATION – TC2001 19 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on Package Information – TPS1035 20 TK2019 – MC/2.1/10-03 Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on Tripath and Digital Power Processing are trademarks of Tripath Technology Inc. Other trademarks referenced in this document are owned by their respective companies. Tripath Technology Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. TRIPATH’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. For more information on Tripath products, visit our web site at: http://www.tripath.com Contact Information TRIPATH TECHNOLOGY, INC 2560 Orchard Parkway, San Jose, CA 95131 408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ www.tripath.com/cont_s.htm For more Technical Information, please visit us @ www.tripath.com/data.htm 21 TK2019 – MC/2.1/10-03