TH71102 315/433MHz FSK/FM/ASK Receiver Features ! ! ! ! ! ! ! Double superhet architecture for high degree of image rejection FSK for digital data and FM reception for analog signal transmission FM/FSK demodulation with phase-coincidence demodulator Low current consumption in active mode and very low standby current Switchable LNA gain for improved dynamic range RSSI allows signal strength indication and ASK detection Surface mount package LQFP32 Ordering Information Part No. Temperature Range Package TH71102 -40 °C to 85°C LQFP32 Application Examples ! ! ! ! ! General digital and analog 315 MHz or 433 MHz ISM band usage Low-power telemetry Alarm and security systems Keyless car and central locking Pagers Technical Data Overview ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Input frequency range: 300 MHz to 450 MHz Power supply range: 2.5 V to 5.5 V Temperature range: -40 °C to +85 °C Operating current: 6.5 mA at low gain and 8.2 mA at high gain mode Standby current: < 100 nA 1) with 40 kHz second IF filter BW (incl. SAW front-end filter loss) Sensitivity: -111 dBm 2) Sensitivity: -104 dBm with 150 kHz second IF filter BW (incl. SAW front-end filter loss) Range of first IF: 10 MHz to 80 MHz Range of second IF: 455 kHz to 21.4 MHz Maximum input level: –10 dBm at ASK and 0 dBm at FSK nd Image rejection: > 65 dB (e.g. with SAW front-end filter and at 10.7 MHz 2 IF) Spurious emission: < -70 dBm Input frequency acceptance: ±50 kHz (with AFC option) RSSI range: 70 dB Frequency deviation range: ±5 kHz to ±120 kHz Maximum data rate: 80 kbit/s NRZ Maximum analog modulation frequency: 15 kHz 1) 2) at ± 8 kHz FSK deviation, BER = 3⋅10 and phase-coincidence demodulation -3 at ± 50 kHz FSK deviation, BER = 3⋅10 and phase-coincidence demodulation TH71102 Data Sheet 3901071102 -3 Page 1 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver General Description The TH71102 receiver IC consists of the following building blocks: " " " " " " " " " PLL synthesizer (PLL SYNTH) for generation of the first and second local oscillator signals LO1 and LO2 Parts of the PLL SYNTH are the high-frequency VCO1, the feedback dividers DIV_8 and DIV_2, a phase-frequency detector (PFD) with charge pump (CP) and a crystal-based reference oscillator (RO) Low-noise amplifier (LNA) for high-sensitivity RF signal reception First mixer (MIX1) for down-conversion of the RF signal to the first IF (IF1) second mixer (MIX2) for down-conversion of the IF1 to the second IF (IF2) IF amplifier (IFA) to amplify and limit the IF2 signal and for RSSI generation Phase coincidence demodulator (DEMOD) with third mixer (MIX3) to demodulate the IF signal Operational amplifier (OA) for data slicing, filtering and ASK detection Bias circuitry for bandgap biasing and circuit shutdown With the TH71102 receiver chip, various circuit configurations can be arranged in order to meet a number of different customer requirements. For FM/FSK reception the IF tank used in the phase coincidence demodulator can be constituted either by a ceramic resonator or an LC tank (optionally with a varactor diode to create an AFC circuit). In ASK configuration, the RSSI signal is feed to an ASK detector, which is constituted by the operational amplifier. Demodulation Type of receiver FM / FSK narrow-band RX with ceramic demodulation tank FM / FSK wide-band RX with LC demodulation tank ASK RX with RSSI-based demodulation The superheterodyne configuration is double conversion where MIX1 and MIX2 are driven by the internal local oscillator signals LO1 and LO2, respectively. This allows a high degree of image rejection, achieved in conjunction with an RF frontend filter. Efficient RF frontend filtering is realized by using a SAW, ceramic or helix filter in front of the LNA and by adding an LC filter at the LNA output. A single-conversion variant, called TH71101, is also available. Both RXICs have the same die. At the TH71101 the second mixer MIX2 operates as an amplifier. TH71102 Data Sheet 3901071102 Page 2 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver 18 OUT_OA 19 20 OA OAN OAP 24 23 OUTN OUTP Block Diagram 17 VCC_BIAS BIAS ENRX 28 16 MIX3 IN_DEM 22 VEE_BIAS 15 OUT_IFA 27 14 VCC_PLL VEE_RO 26 13 FPC2 RO RO IFA 21 25 RSSI 12 FBC1 11 PFD IN_IFA LF CP 29 MIX2 8 VCC_MIX LO2 9 OUT_MIX2 DIV_2 IF2 10 VEE_IF VCO1 MIX1 5 VEE_MIX LO1 6 IF1P DIV_8 IF1 7 IF1N 4 IN_MIX1 VEE_LNA GAIN_LNA VCC_LNA 32 LNA 31 1 VEE_LNAC IN_LNA 2 30 3 OUT_LNA Fig. 1: TH71102 block diagram TH71102 Data Sheet 3901071102 Page 3 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Frequency Planning Frequency planning is straightforward for single-conversion applications because there is only one IF that might be chosen, and then the only possible choice is low-side or high-side injection of the LO1 signal (which is now the one and only LO signal in the receiver). The receiver’s double-conversion architecture requires careful frequency planning. Besides the desired RF input signal, there are a number of spurious signals that may cause an undesired response at the output. Among them are the image of the RF signal (that must be suppressed by the RF front-end filter), spurious signals injected to the first IF (IF1) and their images which could be mixed down to the same second IF (IF2) as the desired RF signal (they must be suppressed by the LC filter at IF1 and/or by low-crosstalk design). By configuring the TH71102 for double conversion and using its internal PLL synthesizer with fixed feedback divider ratios of N1 = 8 (DIV_8) and N2 = 2 (DIV_2), four types of down-conversion are possible: low-side injection of LO1 and LO2 (low-low), LO1 low-side and LO2 high-side (low-high), LO1 high-side and LO2 low-side (high-low) or LO1 and LO2 high-side (high-high). The following table summarizes some equations that are useful to calculate the crystal reference frequency (REF), the first IF (IF1) and the VCO1 or first LO frequency (LO1), respectively, for a given RF and second IF (IF2). Injection type high-high low-low high-low low-high REF (RF – IF2)/14 (RF – IF2)/18 (RF + IF2)/14 (RF + IF2)/18 LO1 16•REF 16•REF 16•REF 16•REF IF1 LO1 – RF RF – LO1 LO1 – RF RF – LO1 LO2 2•REF 2•REF 2•REF 2•REF IF2 LO2 – IF1 IF1 – LO2 IF1 – LO2 LO2 – IF1 The following table depicts generated, desired, possible images and some undesired signals considering the examples of 315 MHz and 433.6 MHz RF reception at IF2 = 10.7 MHz. Signal type RF = 315 MHz RF = 315 MHz RF = 315 MHz RF = 315 MHz RF = RF = RF = RF = 433.6 MHz 433.6 MHz 433.6 MHz 433.6 MHz Injection type high-high low-low high-low low-high high-high low-low high-low low-high REF / MHz 21.73571 16.90556 23.26429 18.09444 30.20714 23.49444 31.73571 24.68333 LO1 / MHz 347.77143 270.48889 372.22857 289.51111 483.31429 375.91111 507.77143 394.93333 IF1 / MHz 32.77143 44.51111 57.22857 25.48889 49.71429 57.68889 74.17143 38.66667 LO2 / MHz 43.47143 33.81111 46.52857 36.18889 60.41429 46.98889 63.47143 49.36667 RF image/MHz 380.54286 225.97778 429.45714 264.02222 533.02857 318.22222 581.94286 356.26667 IF1 image/MHz 46.88889 54.17143 23.11111 35.82857 71.11429 36.28889 52.77143 60.06667 The selection of the reference crystal frequency is based on some assumptions. As for example: the first IF and the image frequencies should not be in a radio band where strong interfering signals might occur (because they could represent parasitic receiving signals), the LO1 signal should be in the range of 300 MHz to 430 MHz (because this is the optimum frequency range of the VCO1). Furthermore the first IF should be as high as possible to achieve highest RF image rejection. The columns in bold depict the selected frequency plans to receive at 315 MHz and 433.6 MHz, respectively. TH71102 Data Sheet 3901071102 Page 4 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Pin Definition and Description Pin No. 3 Name OUT_LNA I/O Type Functional Schematic analog output Description LNA open-collector output, to be connected to external LC tank that resonates at RF OUT_LNA 3 31 IN_LNA analog input LNA input, approx. 26Ω single-ended 5k IN_LNA VEE_LNAC 1 VEE_LNAC ground 2 GAIN_LNA analog input 31 ground of LNA core (cascode) 1 LNA gain control (CMOS input with hysteresis) GAIN_LNA 400Ω 2 4 IN_MIX1 analog input MIX1 input, approx. 33Ω single-ended 13Ω IN_MIX1 4 13Ω 500µA 5 VEE_MIX ground 6 IF1P analog I/O LNA biasing ground VCC 20p IF1P IF1N 20p 7 6 7 IF1N analog I/O open-collector output, to be connected to external LC tank that resonates at first IF 2x500µA VEE VEE 8 VCC_MIX supply 9 OUT_MIX2 analog output open-collector output, to be connected to external LC tank that resonates at first IF MIX1 and MIX2 positive supply 6.8k OUT_MIX2 MIX2 output, approx. 330Ω output impedance 130Ω 9 230µA 10 VEE_IF TH71102 Data Sheet 3901071102 ground ground for MIX2, IFA and DEMOD Page 5 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Pin No. 11 12 Name IN_IFA FBC1 I/O Type Functional Schematic analog input analog I/O IN_IFA FBC1 11 12 2.2k 2.2k 200µA FBC2 analog I/O IFA input, approx. 2.2kΩ input impedance VCC VCC VEE VCC 13 Description FBC2 to be connected to external IFA feedback capacitor VEE VEE to be connected to external IFA feedback capacitor 13 VEE 14 VCC_IF supply positive supply for IFA, DEMOD 15 OUT_IFA analog I/O IFA output and MIX3 input (of DEMOD) OUT_IFA 15 40µA 16 IN_DEM analog input DEMOD input, to MIX3 core 47k IN_DEM 16 17 VCC_BIAS supply positive supply of general bias system and OA 18 OUT_OA analog output OA output, 40uA current drive capability OUT_OA 50Ω 18 19 OAN analog input 20µA OAN 20 OAP TH71102 Data Sheet 3901071102 analog input 50Ω 19 Page 6 of 20 50Ω negative OA input, input voltage limited to approx. 0.7 Vpp between pins OAP and OAN OAP negative OA input, input 20 voltage limited to approx. 0.7 Vpp between pins OAP and OAN Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Pin No. 21 Name RSSI I/O Type Functional Schematic analog output 50Ω RSSI Description RSSI output, for RSSI and ASK detection, approx. 36kΩ output impedance I (Pi) 21 36k 22 VEE_BIAS ground ground for general bias system and OA 23 OUTP analog output FSK/FM positive output, output impedance of 100kΩ to 300kΩ OUTP OUTN 50Ω 24 OUTN analog 25 VEE_RO ground ground of dividers, PFD and RO 26 RO analog input RO input, Colpitts type oscillator with internal feedback capacitors 23 24 20µA 20µA 50k RO 26 FSK/FM negative output, output impedance of 100kΩ to 300kΩ 30p 30p 27 VCC_PLL supply positive supply of RO, DIV, PFD and charge pump 28 ENRX digital input mode control input (CMOS Input) ENRX 1.5k 28 29 LF analog output charge pump output and VCO1 control input LF 200Ω 29 400Ω 4p 30 VEE_LNA ground LNA biasing ground 32 VCC_LNA supply positive supply of LNA biasing TH71102 Data Sheet 3901071102 Page 7 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Technical Data Mode Configurations ENRX Mode 0 SBY 1 ON Note: ENRX are pulled down internally Description standby mode entire chip active LNA Gain Control VGAIN_LNA Mode < 0.8 V > 1.4 V HIGH GAIN LOW GAIN Description LNA set to high gain by voltage at GAIN_LNA LNA set to low gain by voltage at GAIN_LNA Note: hysteresis between gain modes to ensure stability Absolute Maximum Ratings Parameter Supply voltage Input voltage Input RF level Storage temperature Electrostatic discharge Symbol Vcc VIN Pimax TSTG ESD Condition / Note Min Max Unit 0 - 0.3 -40 7.0 VCC+0.3 10 +125 V V dBm °C human body model, MIL STD 833D method 3015.7, all pins except OUT_IFA pin OUT_IFA -500 -500 +500 +250 V V Condition Min Max Unit 2.5 -40 300 ±5 5.5 +85 450 ±120 40 15 80 V ºC MHz kHz kbit/s kHz kbit/s no damage Normal Operating Conditions Parameter Supply voltage Operating temperature Input frequency Frequency deviation FSK data rate FM bandwidth ASK data rate TH71102 Data Sheet 3901071102 Symbol Vcc Ta fi ∆f RFSK fm RASK at FM or FSK NRZ NRZ Page 8 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver DC Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at Ta = 23 °C and Vcc = 3 V Parameter Symbol Standby current Total supply current at low gain ISBY Icc, low Total supply current at high gain Icc, high Opamp input offset voltage Opamp input offset current Opamp input bias current RSSI voltage at low input level Voffs Ioffs Ibias VRSSI, low RSSI voltage at high input level VRSSI, high Condition ENRX=0 ENRX=1, LNA at LOW GAIN ENRX=1, LNA at HIGH GAIN IOAP – IOAN 0.5 * (IOAP + IOAN) Pi = -65 dBm, LNA at LOW GAIN Pi = -35 dBm, LNA at LOW GAIN Min Typ Max Unit 5.0 6.5 100 8.0 nA mA 6.5 8.2 10.0 mA -20 -50 -100 0.5 1.0 20 50 100 1.5 mV nA nA V 1.25 1.9 2.45 V AC System Characteristics all parameters under normal operating conditions, unless otherwise stated; all parameters based on test circuits for FSK (Fig. 2), FM (Fig. 4) and ASK (Fig. 5), respectively; typical values at Ta = 23 °C and Vcc = 3 V, RF at 433.6 MHz, second IF at 10.7 MHz Parameter Symbol start-up time – FSK/FM TFSK start-up time – ASK TASK input sensitivity – FSK (narrow band) Pmin, n input sensitivity – FSK (wide band) Pmin, w input sensitivity – ASK PminA, n (narrow band) input sensitivity – ASK PminA, w (wide band) maximum input signal – FSK/FM Pmax, FM maximum input signal – ASK Pmax, ASK spurious emission image rejection blocking immunity VCO gain Charge pump current Pspur ∆Pimag ∆Pblock KVCO ICP Condition Min ENRX from 0 to 1, valid data at output depends on ASK detector time constant, valid data at output BIF2 = 40kHz ∆f = ±15kHz (FSK/FM) -3 BER ≤ 3⋅10 BIF2 = 150kHz ∆f = ±50kHz (FSK/FM) -3 BER ≤ 3⋅10 BIF2 = 40kHz -3 BER ≤ 3⋅10 BIF2 = 150kHz -3 BER ≤ 3⋅10 -3 BER ≤ 3⋅10 LNA at LOW GAIN -3 BER ≤ 3⋅10 LNA at LOW GAIN Typ Max Unit 0.9 ms R3•C12 + TFSK ms -111 dBm -104 dBm -109 dBm -106 dBm 0 dBm -10 dBm -70 ∆fblock > ±2MHz, note 1 65 57 250 60 dBm dB dB MHz/V µA Notes: 1. desired signal with FSK/FM or ASK modulation, CW blocking signal TH71102 Data Sheet 3901071102 Page 9 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Test Circuits FSK Reception C14 C15 C16 OAN OAP RSSI OUT_OA XTAL VEE VEE OUTP OUTN VCC VCC C1 C13 IN_DEM C12 OUT_IFA RO VCC CP VCC VCC VCC CERRES C11 FBC2 LF FBC1 C9 C3 L3 C6 VCC IF1N IF1P VEE L4 LCFIL C4 CERFIL OUT_MIX2 C8 C7 L1 IN_IFA VEE OUT_LNA VCC VEE VCC SAWFIL L2 C5 GAIN_LNA IN_LNA C10 LQFP32 VEE IN_MIX1 R1 ENRX L5 CB* VCC Fig. 2: Test circuit for FSK reception TH71102 Data Sheet 3901071102 Page 10 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FSK test circuit component list to Fig. 2 Part Size Value / Type Tolerance C1 0805 15 pF ±10% C3 0805 1 nF ±10% C4 0603 3.3 pF ±5% C5 0603 3.3 pF ±5% C6 0603 4.7 pf ±5% C7 0603 2.2 pf ±5% C8 0603 27 pF ±5% C9 0805 33 nF ±10% C10 0603 1 nF ±10% C11 0603 1 nF ±10% C12 0603 1.5 pF ±5% C13 0603 680 pF ±10% CP 0805 10 – 12 pF ±5% C14 0805 10 – 47 pF ±5% C15 0805 10 – 47 pF ±5% C16 0603 330 pF ±10% R1 0805 10 kΩ ±10% L1 0603 33 nH ±5% L2 0603 33 nH ±5% L3 0603 15 nH ±5% L4 0805 100 nH ±5% L5 0805 100 nH ±5% XTAL HC49 SMD 23.49444 MHz @ RF = 433.6 MHz ±25ppm calibration ±30ppm temp. SAWFIL QCC8C B3555 @ RF = 433.6 MHz CERFIL leaded type SFE10.7MFP @ BIF2 = 40 kHz TBD SMD type SFECV10.7MJS-A @ BIF2 = 150 kHz ±40 kHz SMD type CDACV10.7MG18-A CERRES Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor CERRES parallel capacitor demodulator output low-pass capacitor, depending on data rate demodulator output low-pass capacitor, depending on data rate RSSI output low-pass capacitor loop filter resistor inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 Ω B3dB = 860 kHz low-loss SAW filter from EPCOS ±100 kHz (f0 = 433.92 MHz) ceramic filter from Murata ceramic demodulator tank from Murata NIP – not in place, may be used optionally TH71102 Data Sheet 3901071102 Page 11 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FSK Circuit with AFC and Ceramic Resonator Tolerance Compensation C14 C15 C16 C17 C18 R4 R3 VCC VCC OAN OAP RSSI OUT_OA XTAL VEE VEE OUTP OUTN R5 C1 VD C13 IN_DEM C12 OUT_IFA RO VCC CP VCC VCC VCC CERRES C11 FBC2 LF FBC1 C9 C3 C6 L4 LCFIL L3 C4 VCC CERFIL OUT_MIX2 C8 C7 L1 IF1N IF1P VEE VCC IN_IFA VEE OUT_LNA VCC VEE C5 SAWFIL L2 GAIN_LNA IN_LNA C10 LQFP32 VEE IN_MIX1 R1 ENRX L5 CB* VCC Fig. 3: Test circuit for FSK with AFC and resonator compensation Circuit Feature ! ! ! ! Improves input frequency acceptance range up to RFnom ±50 kHz Eliminates calibration tolerances of ceramic resonator Eliminates temperature tolerances of ceramic resonator Non-inverted and inverted CMOS-compatible outputs TH71102 Data Sheet 3901071102 Page 12 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FSK test circuit with AFC component list to Fig. 3 Part Size Value / Type Tolerance C1 0805 15 pF ±10% C3 0805 1 nF ±10% C4 0603 3.3 pF ±5% C5 0603 3.3 pF ±5% C6 0603 4.7 pF ±5% C7 0603 2.2 pF ±5% C8 0603 27 pF ±5% C9 0805 33 nF ±10% C10 0603 1 nF ±10% C11 0603 1 nF ±10% C12 0603 1.5 pF ±5% C13 0603 680 pF ±10% CP 0805 27 pF ±5% C14 0805 10 – 47 pF ±5% C15 0805 10 – 47 pF ±5% C16 0603 330 pF ±10% C17 C18 0805 R1 0805 0805 R3 33 nF ±10% 33 nF 10 nF 1 nF ±10% 10 kΩ ±10% ±10% R4 R5 L1 0805 0805 100 kΩ 680 kΩ 680 kΩ 0603 33 nH ±5% L2 0603 33 nH ±5% L3 0603 15 nH ±5% L4 0805 100 nH ±5% L5 0805 100 nH ±5% VD SOD-323 BB535 XTAL HC49 SMD 23.49444 MHz @ RF = 433.6 MHz SAWFIL QCC8C B3555 @ RF = 433.6 MHz CERFIL leaded type SFE10.7MFP @ BIF2 = 40 kHz SMD type SFECV10.7MJS-A @ BIF2 = 150 kHz SMD type CDACV10.7MG18-A CERRES ±10% ±10% Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor ceramic resonator loading capacitor demodulator output low-pass capacitor, depending on data rate demodulator output low-pass capacitor, depending on data rate RSSI output low-pass capacitor integrator capacitor, fixed integrator capacitor, @ 0.5 to 2 kbit/s NRZ integrator capacitor, @ 2 to 20 kbit/s NRZ integrator capacitor, @ 20 to 40 kbit/s NRZ loop filter resistor varactor diode biasing resistor integrator resistor integrator resistor inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor varactor diode from Infineon fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 Ω ±25ppm calibration ±30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS ±100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata ±40 kHz ceramic demodulator tank from Murata NIP – not in place, may be used optionally TH71102 Data Sheet 3901071102 Page 13 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FM Reception C14 R6 R5 R3 R4 C16 VCC VCC OAN OAP RSSI OUT_OA XTAL VEE VEE OUTP OUTN C15 C1 C13 IN_DEM C12 OUT_IFA RO VCC CP VCC VCC VCC CERRES C11 FBC2 LF FBC1 C9 C3 L3 C6 VCC IF1N IF1P VEE L4 LCFIL C4 CERFIL OUT_MIX2 C8 C7 L1 IN_IFA VEE OUT_LNA VCC VEE VCC SAWFIL L2 C5 GAIN_LNA IN_LNA C10 LQFP32 VEE IN_MIX1 R1 ENRX L5 CB* VCC Fig. 4: Test circuit for FM reception TH71102 Data Sheet 3901071102 Page 14 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver FM test circuit component list to Fig. 4 Part Size Value / Type Tolerance Description C1 0805 15 pF ±10% C3 0805 1 nF ±10% C4 0603 3.3 pF ±5% C5 0603 3.3 pF ±5% C6 0603 4.7 pF ±5% C7 0603 2.2 pF ±5% C8 0603 27 pF ±5% C9 0805 33 nF ±10% C10 0603 1 nF ±10% C11 0603 1 nF ±10% C12 0603 1.5 pF ±5% C13 0603 680 pF ±10% crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor DEMOD phase-shift capacitor DEMOD coupling capacitor CERRES parallel capacitor sallen-Key low-pass filter capacitor, to set cut-off frequency sallen-Key low-pass filter capacitor, to set cut-off frequency RSSI output low-pass capacitor loop filter resistor sallen-Key filter resistor, to set desired filter characteristic sallen-Key filter resistor, to set desired filter characteristic sallen-Key filter resistor, to set cut-off frequency sallen-Key filter resistor, to set cut-off frequency inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 Ω CP 0805 10 – 12 pF ±5% C14 0805 100 pF ±5% C15 0805 100 pF ±5% C16 0603 330 pF ±10% R1 0805 10 kΩ ±10% R3 0805 12 kΩ ±5% R4 0805 6.8 kΩ ±5% R5 0805 33 kΩ ±5% R6 0805 33 kΩ ±5% L1 0603 33 nH ±5% L2 0603 33 nH ±5% L3 0603 15 nH ±5% L4 0603 100 nH ±5% L5 0603 100 nH XTAL HC49 SMD 23.49444 MHz @ RF = 433.6 MHz SAWFIL QCC8C B3555 @ RF = 433.6 MHz CERFIL leaded type SFE10.7MFP @ BIF2 = 40 kHz SMD type SFECV10.7MJS-A @ BIF2 = 150 kHz SMD type CDACV10.7MG18-A CERRES ±5% ±25ppm calibration ±30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS ±100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata ±40 kHz ceramic demodulator tank from Murata NIP – not in place, may be used optionally TH71102 Data Sheet 3901071102 Page 15 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver ASK Reception R3 C13 VCC OAN OAP RSSI VCC OUT_OA XTAL VEE VEE OUTP OUTN C12 IN_DEM OUT_IFA RO C1 VCC VCC VCC VCC C11 FBC2 LF FBC1 C9 C3 L3 C6 VCC IF1N IF1P VEE L4 LCFIL C4 CERFIL OUT_MIX2 C8 C7 L1 IN_IFA VEE OUT_LNA VCC VEE VCC SAWFIL L2 C5 GAIN_LNA IN_LNA C10 LQFP32 VEE IN_MIX1 R1 ENRX L5 CB* VCC Fig. 5: Test circuit for ASK reception TH71102 Data Sheet 3901071102 Page 16 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver ASK test circuit component list to Fig. 5 Part Size Value / Type Tolerance C1 0805 15 pF ±10% C3 0805 1 nF ±10% C4 0603 3.3 pF ±5% C5 0603 3.3 pF ±5% C6 0603 4.7 pF ±5% C7 0603 2.2 pF ±5% C8 0805 27 pF ±5% C9 0805 33 nF ±10% C10 0603 1 nF ±10% C11 0603 1 nF ±10% C12 0805 1 nF to 10 nF ±10% C13 0603 330 pF ±10% R1 0805 10 kΩ ±10% R3 0603 100 kΩ ±5% L1 0603 33 nH ±5% L2 0603 33 nH ±5% L3 0603 15 nH ±5% L4 0603 100 nH ±5% L5 0603 100 nH ±5% XTAL HC49 SMD 23.49444 MHz @ RF = 433.6 MHz SAWFIL QCC8C B3555 @ RF = 433.6 MHz CERFIL leaded type SFE10.7MFP @ BIF2 = 40 kHz SMD type SFECV10.7MJS-A @ BIF2 = 150 kHz Description crystal series capacitor loop filter capacitor capacitor to match to SAW filter input capacitor to match to SAW filter output LNA output tank capacitor MIX1 input matching capacitor IF1 tank capacitor IFA feedback capacitor IFA feedback capacitor IFA feedback capacitor ASK data slicer capacitor, depending on data rate RSSI output low-pass capacitor loop filter resistor ASK data slicer resistor, depending on data rate inductor to match SAW filter inductor to match SAW filter LNA output tank inductor IF1 tank inductor IF1 tank inductor fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 50 Ω ±25ppm calibration ±30ppm temp. B3dB = 860 kHz low-loss SAW filter from EPCOS ±100 kHz (f0 = 433.92 MHz) TBD ceramic filter from Murata ±40 kHz NIP – not in place, may be used optionally TH71102 Data Sheet 3901071102 Page 17 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Package Dimensions D D1 24 17 16 25 E e E1 32 9 1 A A2 b 8 A1 L Fig. 6: LQFP32 (Low Quad Flat Package) All Dimension in mm, coplanaríty < 0.1mm E1, D1 A A1 A2 e b min 0.05 1.35 0.30 7.00 0.8 max 1.60 0.15 1.45 0.45 All Dimension in inch, coplanaríty < 0.004” min 0.002 0.053 0.012 0.276 0.031 max 0.630 0.006 0.057 0.018 TH71102 Data Sheet 3901071102 Page 18 of 20 L 0.45 E, D α 0° 9.00 0.75 7° 0.018 0° 0.354 0.030 7° Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Your Notes TH71102 Data Sheet 3901071102 Page 19 of 20 Nov. 2001 Rev. 005 TH71102 315/433MHz FSK/FM/ASK Receiver Your Notes Important Notice Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services. © 2000 Melexis GmbH. All rights reserved. For the latest version of this document. Go to our website at www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: All other locations: Phone: +32 1361 1631 E-mail: [email protected] Phone: +1 603 223 2362 E-mail: [email protected] QS9000, VDA6.1 and ISO14001 Certified TH71102 Data Sheet 3901071102 Page 20 of 20 Nov. 2001 Rev. 005