ROHM BU7988KVT

LVDS Interface ICs
56bit LVDS Transmitter
56:8 Serializer
BU7988KVT
●Description
LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and
number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number
by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI.
●Features
■Wide dot clock range : Single(112MHz)/Dual(224MHz)(NTSC, VGA, SVGA, WXGA UXGA)
■Support spread spectrum clock generator.
■Clock edge selectable.
■Support reduced swing LVDS for low EMI.
■Power down mode.
■Package TQFP100V
●Applications
Flat Plane Display
●Precaution
■This chip is not designed to protect from radioactivity.
Jun. 2008
●Block Diagram
LVCMOS Input
CLK_IN
LVDS Output
+
-
PLL
B10~B17
8
8
R20~R27
8
G20~G27
8
B20~B27
8
8
8
8
8
8
HSYNC
VSYNC
DE
MODE0
MODE1
XRST
OE
SEL_BIT
RF
RS
MAP
FLIP
Figure-1
Block Diagram
2 / 27
(8~112MHz)
+
-
TA1 P/N
+
-
TB 1 P/N
+
-
TC 1 P/N
+
-
TD 1 P/N
+
-
TCLK2 P/N
8
PARALLEL TO SERIAL
G10~G17
8
MUX
R10~R17
PARALLEL TO SERIAL
(4~150MHz)
TCLK1 P/N
(8~112MHz)
+
-
TA2 P/N
+
-
TB2 P/N
+
-
TC2 P/N
+
-
TD2 P/N
●TQFP100V
Package Outline and Specification
Product No.
16.0±0.3
14.0±0.2
51
75
76
50
16.0±0.3
14.0±0.2
BU7988KVT
1PIN MARK
100
26
0.5
Lot No.
25
1
1.2MAX
1.0±0.1
0.1±0.1
0.125±0.1
Figure-2
0.2±0.1
0.5
0.1
TQFP100V Package Outline and Specification
3 / 27
100-Pin TQFP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
B24
B25
VDD
GND
B26
B27
HSYNC
VSYNC
DE
CLKIN
RF
RS
Reserved0
MAP
MODE1
MODE0
OE
SEL_BIT
XRST
Reserved1
FLIP
N/C
PLL GND
PLL VCC
PLL GND
B15
B16
B17
R20
R21
R22
R23
R24
R25
R26
R27
VDD
GND
G20
G21
G22
G23
G24
G25
G26
G27
B20
B21
B22
B23
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
B14
B13
B12
GND
VDD
B11
B10
G17
G16
G15
G14
G13
G12
G11
G10
R17
R16
R15
R14
GND
VDD
R13
R12
R11
R10
● Pin configuration
Figure-3 Pin Diagram (Top View)
4 / 27
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
LVDS GND
TA1N
TA1P
TB1N
TB1P
LVDS VDD
TC1N
TC1P
TCLK1N
TCLK1P
TD1N
TD1P
LVDS GND
TA2N
TA2P
TB2N
TB2P
LVDS VDD
TC2N
TC2P
TCLK2N
TCLK2P
TD2N
TD2P
LVDS GND
●Pin Description
Table 1 : Pin Description
Pin Name
Pin No.
Type
TA1P, TA1N
48, 49
LVDS OUT
TB1P, TB1N
46, 47
LVDS OUT
TC1P, TC1N
43, 44
LVDS OUT
TD1P, TD1N
39, 40
LVDS OUT
TCLK1P, TCLK1N
41, 42
LVDS OUT
TA2P, TA2N
36, 37
LVDS OUT
TB2P, TB2N
34, 35
LVDS OUT
TC2P TC2N
31, 32
LVDS OUT
TD2P, TD2N
27, 28
LVDS OUT
TCLK2P, TCLK2N
29, 30
LVDS OUT
R17~R10
60, 59, 58, 57, 54, 53, 52, 51
IN
G17~G10
68, 67, 66, 65, 64, 63, 62, 61
IN
B17~B10
78, 77, 76, 75, 74, 73, 70, 69
IN
R27~R20
86, 85, 84, 83, 82, 81, 80, 79
IN
G27~G20
96, 95, 94, 93, 92, 91, 90, 89
IN
B27~B20
6, 5, 2, 1, 100, 99, 98, 97
IN
DE
9
IN
DATA-ENABLE input.
VSYNC
8
IN
VSYNC input.
HSYNC
7
IN
HSYNC input.
CLKIN
10
IN
Clock Input.
MAP
14
IN
LVDS mapping table select.
See Table11-14 and Figure11-14.
XRST
19
IN
H : Normal operation,
L : Power down (all outputs are Hi-Z)
FLIP
21
IN
LVDS output pin select. See Table10.
5 / 27
Descriptions
LVDS data out
LVDS clock out
LVDS data out
LVDS clock out
1st Pixel data input.
2st Pixel data inputs.
Pin Name
Pin No.
Type
Descriptions
LVDS swing mode, RS select.
RS
12
IN
RS
VDD
GND
LVDS
Swing
350mV
200mV
MODE1, MODE0
15, 16
IN
Pixel Data Mode
MODE1 MODE0
L
L
L
H
H
L
H
H
SEL_BIT
18
IN
6bit/8bit color select.
H:6bit (TDxP/N*1 are Hi-Z), L:8bit.
Mode
Dual-in/Dual-out
Dual-in/Single-out
Single-in/Dual-out
Single-in/Single-out
Outputs enable.
H:Outputs enable,
L:Output disable (all outputs are Hi-Z)
Input Clock Triggering Select
H : Rising edge,
L : Falling edge
OE
17
IN
RF
11
IN
N/C
22
Reserved1
20
IN
Must be tied to GND
Reserved0
13
IN
Must be open
VDD
3, 55, 71, 87
Power
GND
4, 56, 72, 88
Ground
LVDS VDD
33, 45
Power
Power Supply Pins for LVDS Outputs.
LVDS GND
26, 38, 50
Ground
Ground Pins for LVDS Outputs.
PLL VDD
24
Power
Power Supply for PLL circuitry.
PLL GND
23, 25
Ground
Ground Pin for PLL circuitry.
Must be open
Power Supply Pins for CMOS inputs, output and
digital circuitry.
Ground Pins for CMOS inputs, outputs and digital
circuitry.
*1: X=1,2
6 / 27
●Electrical characteristics
■Rating
Table 2 : Absolute Maximum Rating
Parameter
Symbol
Supply Voltage
Rating
Units
Min
Max
VDD
-0.3
4.0
V
Input Voltage
VIN
-0.3
VDD+0.3
V
Output Voltage
VOUT
-0.3
VDD+0.3
V
Storage Temperature Range
Tstg
-55
125
℃
Table 3 : Package Power
PACKAGE
Power Dissipation (mW)
900
1400*2
TQFP100V
De-rating (mW/℃) *1
9.0
14.0*2
*1:At temperature Ta >25℃
*2:Package power when mounting on the PCB board.
The size of PCB board :70×70×1.6(mm3)
The material of PCB board : The FR4 glass epoxy board.(3% or less copper foil area)
(It is recommended to apply the above package power requirement to PCB board when the small swing
input mode is used)
Table 4 : Recommended Operating Conditions
Parameter
Supply Voltage
Operating
Temperature Range
Rating
Symbol
VDD
Topr
Units
Conditions
Min
Typ
Max
3.0
3.3
3.6
V
VDD,LVDSVDD,PLLVDD
-20
-
85
℃
Clock frequency from 8MHz up to 90MHz
0
-
70
℃
Clock frequency from 90MHz up to 112MHz
7 / 27
■DC characteristics
Table 5 : CMOS DC Specifications(VDD=3.0V~3.6V, Ta=-20℃~+85℃)
Rating
Symbol
Parameter
Units
Min
Typ
Max
VIH
High Level Input Voltage
VDD×0.8
-
VDD
V
VIL
Low Level Input Voltage
GND
-
VDD×0.2
V
IINC
Input Leak Current
-10
-
+10
μA
Conditions
0V≤VIN≤VDD
Table 6 : LVDS Transmitter DC Specifications(VDD=3.0V~3.6V, Ta=-20℃~+85℃)
Rating
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Normal swing
250
350
450
mV
RS=VDD
Differential Output Voltage
VOD
RL=100Ω
Reduced
120
200
300
mV
swing
RS=GND
ΔVOD
Change in VOD between
complementary output states
-
-
35
mV
VOC
Common Mode Voltage
1.125
1.25
1.375
V
ΔVOC
Change in VOC between
complementary output states
-
-
35
mV
IOS
Output Short Circuit Current
-
-
-24
mA
VOUT=0V, RL=100Ω
IOZ
Output TRI-STATE Current
-10
-
+10
μA
XRST=0V,
VOUT=0V to VDD
8 / 27
RL=100Ω
■Supply Current
Table 7 : Supply Current (VDD=3.3V, Ta=25℃)
Symbol
ITCCG
ITCCW
ITCCS
Parameter
Rating
Units
Conditions
Min
Typ
Max
-
TBD
-
-
TBD
-
Transmitter Supply
-
TBD
-
Current
-
TBD
-
MODE[1:0]=L L
f=112MHz
(Gray Scale Pattern)
-
TBD
-
MODE[1:0]=H H
RL=100Ω
-
TBD
-
MODE[1:0]=H L
CL=5pF
-
TBD
-
-
TBD
-
MODE[1:0]=L L
-
TBD
-
MODE[1:0]=H H
-
TBD
-
Transmitter Supply
-
TBD
-
Current
-
TBD
-
MODE[1:0]=L L
f=112MHz
(Worst Case pattern)
-
TBD
-
MODE[1:0]=H H
RL=100Ω
-
TBD
-
MODE[1:0]=H L
CL=5pF
-
TBD
-
-
TBD
-
-
-
10
Transmitter Power
Down
Supply Current
9 / 27
MODE[1:0]=H H
mA
mA
mA
mA
RS=H
RS=L
RS=H
RS=L
MODE[1:0]=H L
MODE[1:0]=L H
MODE[1:0]=L H
MODE[1:0]=H L
MODE[1:0]=L H
MODE[1:0]=L H
MODE[1:0]=L L
μA
XRST=L
Gray Scale Pattern
CLK_IN
Rx0/Gx0/Bx0
Rx1/Gx1/Bx1
Rx2/Gx2/Bx2
Rx3/Gx3/Bx3
Rx4/Gx4/Bx4
Rx5/Gx5/Bx5
Rx6/Gx6/Bx6
Rx7/Gx7/Bx7
x=1,2
Figure-4 Gray scale pattern
Worst Case Pattern (Maximum Power condition)
CLK_IN
Rx0/Gx0/Bx0
Rx1/Gx1/Bx1
Rx2/Gx2/Bx2
Rx3/Gx3/Bx3
Rx4/Gx4/Bx4
Rx5/Gx5/Bx5
Rx6/Gx6/Bx6
Rx7/Gx7/Bx7
x=1,2
Figure-5 Worst Case Pattern
10 / 27
■AC characteristics
Table 8 : Switching Characteristics (VDD=3.3V, Ta=25℃)
Symbol
Parameter
Min
Typ
Max
Units
tTCIT
CLK IN Transition time
-
-
5.0
ns
Dual In /Dual Out
8.9
-
125.0
Dual In / Single Out
17.8
-
62.5
Single In / Dual Out
6.7
-
250.0
Single In / Single Out
8.9
tTCP
CLK IN Period
ns
125.0
tTCH
CLK IN High Time
0.35tTCP
0.5tTCP
0.65tTCP
ns
tTCL
CLK IN Low Time
ns
tTCD
CLK IN to
TCLK+/-Delay
0.35tTCP
0.5tTCP
0.65tTCP
Dual In /Dual Out
Single In/Single Out
-
TBD
-
Dual In / Single Out
-
TBD
-
Single In / Dual Out
-
TBD
-
ns
tTS
CMOS Data Setup to CLK IN
2.5
-
-
ns
tTH
CMOS Data Hold from CLK IN
0
-
-
ns
Dual In /Dual Out
8.9
-
125.0
Dual In / Single Out
8.9
-
125.0
Single In / Dual Out
13.3
-
125.0
Single In / Single Out
8.9
tTCOP
CLK OUT Period
125.0
tLVT
LVDS Transition Time
-
0.6
1.5
ns
tTOP1
Output Data Position 0
-0.2
0.0
+0.2
ns
tTOP0
Output Data Position 1
tTOP6
Output Data Position 2
tTOP5
Output Data Position 3
tTOP4
Output Data Position 4
tTOP3
Output Data Position 5
tTOP2
Output Data Position 6
tTCP
-0.2
7
tTCP
2
-0.2
7
tTCP
3
-0.2
7
tTCP
4
-0.2
7
tTCP
5
-0.2
7
tTCP
6
-0.2
7
tTCP
7
tTCP
2
7
tTCP
3
7
tTCP
4
7
tTCP
5
7
tTCP
6
7
tTCP
+0.2
7
tTCP
2
+0.2
7
tTCP
3
+0.2
7
tTCP
4
+0.2
7
tTCP
5
+0.2
7
tTCP
6
+0.2
7
Tck12
Skew Time between
TCLKXP and TCLKYP
-
-
0.5
ns
tTPLL
Phase Lock Loop Set Time
-
-
10.0
ms
11 / 27
ns
ns
ns
ns
ns
ns
●AC Timing
■AC Timing Diagrams
90%
90%
LVCMOS Input
CLK IN
10%
10%
tTCIT
tTCIT
LVDS Output
Vdiff=(TAP)-(TAN)
80%
TAP
Vdiff
5pF
100Ω
80%
20%
20%
TAN
tLVT
LVDS Output Load
tLVT
LVCMOS Input
tTCP
tTCH
CLKIN
VDD/2
RF=L
VDD/2
VDD/2
RF=H
tTCL
tTS
Rxn/Gxn/Bxn
HSYNC,
VSYNC,DE
TCLK1/2P
VDD/2
tTH
VDD/2
tTCD
VOC
TCLK1/2N
x=1, 2
y=0-7
Figure-6 AC Timing Diagrams
12 / 27
■ AC Timing Diagrams
tTOP2
tTOP3
tTOP4
tTOP5
tTOP6
tTOP0
tTOP1
Tyx+/-
Tyx6
Tyx5
Tyx4
Tyx3
TCLK1+
Tyx2
Tyx1
Tyx0
Tyx6
Tyx5
Tyx4
Vdiff = 0V
Tyx3
Tyx2
Tyx1
Vdiff = 0V
tTCOP
TCLK1P+
Vdiff = 0V
tCK12
TCLK2P+
Vdiff = 0V
Note:
Vdiff = (Tyx+) – (Tyx-), (TCLK1P) – (TCLK1N)
Figure-7 AC Timing Diagrams
X=1.2
Y=A,B,C,D
■Phase Lock Loop Set Time
XRST
VDD/2
3.6V
3.0V
VDD
tTPLL
CLKIN
Vdiff=0V
TCLKP/N
Figure-8 Phase Lock Loop Set Time
13 / 27
●Pixel Map Table for Dual Link
Table 9 : Pixel Map Table for Dual Link
1st Pixel Data
TFT Panel Data
BU7988KVT Input
24Bit
18Bit
LSB
R10
R10
R11
R11
R12
R10
R12
R13
R11
R13
R14
R12
R14
R15
R13
R15
R16
R14
R16
MSB
R17
R15
R17
LSB
G10
G10
G11
G11
G12
G10
G12
G13
G11
G13
G14
G12
G14
G15
G13
G15
G16
G14
G16
MSB
G17
G15
G17
LSB
B10
B10
B11
B11
B12
B10
B12
B13
B11
B13
B14
B12
B14
B15
B13
B15
B16
B14
B16
MSB
B17
B15
B17
2nd Pixel Data
TFT Panel Data
BU7988KVT Input
24Bit
18Bit
LSB
R20
R20
R21
R21
R22
R20
R22
R23
R21
R23
R24
R22
R24
R25
R23
R25
R26
R24
R26
MSB
R27
R25
R27
LSB
G20
G20
G21
G21
G22
G20
G22
G23
G21
G23
G24
G22
G24
G25
G23
G25
G26
G24
G26
MSB
G27
G25
G27
LSB
B20
B20
B21
B21
B22
B20
B22
B23
B21
B23
B24
B22
B24
B25
B23
B25
B26
B24
B26
MSB
B27
B25
B27
14 / 27
●LVDS Data Output Table for Function of FLIP pin
Table 10 : LVDS Data Output Pin Name
Output Pin Names
Pin No
FLIP=L
FLIP=H
49
TA1N
TD2P
48
TA1P
TD2N
47
TB1N
TCLK2P
46
TB1P
TCLK2N
44
TC1N
TC2P
43
TC1P
TC2N
42
TCLK1N
TB2P
41
TCLK1P
TB2N
40
TD1N
TA2P
39
TD1P
TA2N
37
TA2N
TD1P
36
TA2P
TD1N
35
TB2N
TCLK1P
34
TB2P
TCLK1N
32
TC2N
TC1P
31
TC2P
TC1N
30
TCLK2N
TB1P
29
TCLK2P
TB1N
28
TD2N
TA1P
27
TD2P
TA1N
15 / 27
●LVCMOS Data Input Timing for Dual Link
Example : SXGA+(1400×1050)
HSYNC
DE
C L K _IN
R 1x/G 1x/B 1x
#1
#3
#5
#7
1395
#1397
#1399
R 2x/G 2x/B 2x
#2
#4
#6
#8
1396
#1398
#1400
#1
#2
#1399
#1400
x=0~ 9
T FT Panel
(1 4 0 0 × 1 0 5 0 )
Figure-9 LVCMOS Data Input Timing for Dual Link
●LVCMOS Data Input Timing for Single Link
Example : SXGA+(1400×1050)
HSYNC
DE
C L K _IN
R 1x/G 1x/B 1x
#1
#2
#1
#2
#3
#4
1398
#1399
#1400
#1399
#1400
x=0~ 9
TFT Panel
(1 4 0 0 × 1 0 5 0 )
Figure-10 LVCMOS Data Input Timing for Single Link
16 / 27
●LVDS Output Data Mapping (Dual Link / Single Link)
LVDS Data Output
R1n,~B1n
n=0~7
VDD
DATA1n-1
DATA1n
DATA1n+1
GND
R2n,~B2n
n=0~7
VDD
DATA2n-1
DATA2n
DATA2n+1
GND
LVCMOS Data Input
Figure-11 LVDS Output Data Mapping
17 / 27
●LVCMOS Data Inputs Timing in Dual Link
Dual-in / Dual-out Mode
(MODE<1:0>=LL , FLIP=L)
Table 11 : LVCMOS Data Inputs Timing Diagrams in Dual Link
1st Pixel Data
2nd Pixel Data
LVDS
Output Data
(1st Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
LVDS
Output Data
(2nd Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
TA10
TA11
TA12
TA13
TA14
TA15
TA16
TB10
TB11
TB12
TB13
TB14
TB15
TB16
TC10
TC11
TC12
TC13
TC14
TC15
TC16
TD10
TD11
TD12
TD13
TD14
TD15
TD16
R12
R13
R14
R15
R16
R17
G12
G13
G14
G15
G16
G17
B12
B13
B14
B15
B16
B17
HSYNC
VSYNC
DE
R10
R11
G10
G11
B10
B11
L
R10
R11
R12
R13
R14
R15
G10
G11
G12
G13
G14
G15
B10
B11
B12
B13
B14
B15
HSYNC
VSYNC
DE
R16
R17
G16
G17
B16
B17
L
TA20
TA21
TA22
TA23
TA24
TA25
TA26
TB20
TB21
TB22
TB23
TB24
TB25
TB26
TC20
TC21
TC22
TC23
TC24
TC25
TC26
TD20
TD21
TD22
TD23
TD24
TD25
TD26
R22
R23
R24
R25
R26
R27
G22
G23
G24
G25
G26
G27
B22
B23
B24
B25
B26
B27
HSYNC
VSYNC
DE
R20
R21
G20
G21
B20
B21
L
R20
R21
R22
R23
R24
R25
G20
G21
G22
G23
G24
G25
B20
B21
B22
B23
B24
B25
HSYNC
VSYNC
DE
R26
R27
G26
G27
B26
B27
L
18 / 27
●LVCMOS Data Inputs Timing Diagrams in Dual Link
Dual-in / Dual-out Mode
(MODE<1:0>=LL, FLIP=L, MAP=H)
LVDS Data Output
R1n,~B1n
n=0~7
VDD
DATA1n-1
DATA1n
DATA1n+1
GND
R2n,~B2n
n=0~7
VDD
DATA2n-1
DATA2n
DATA2n+1
GND
LVCMOS Data Input
Figure-12 LVCMOS Data Inputs Timing Diagrams in Dual Link
19 / 27
●LVCMOS Data Inputs Timing in Single Link
Dual-in / Single-out Mode
(MODE<1:0>=LH, FLIP=L)
Table 12 : LVCMOS Data Inputs Timing Diagrams in Dual Link
LVDS
Mapping Mode1 Mapping Mode2
Output Data
(Input Pin Name) (Input Pin Name)
(1st Pixel Data)
TA10
TA11
TA12
TA13
TA14
TA15
TA16
TB10
TB11
TB12
TB13
TB14
TB15
TB16
TC10
TC11
TC12
TC13
TC14
TC15
TC16
TD10
TD11
TD12
TD13
TD14
TD15
TD16
R12/R22
R13/R23
R14/R24
R15/R25
R16/R26
R17/R27
G12/G22
G13/G23
G14/G24
G15/G25
G16/G26
G17/G27
B12/B22
B13/B23
B14/B24
B15/B25
B16/B26
B17/B27
HSYNC
VSYNC
DE
R10/R20
R11/R21
G10/G20
G11/G21
B10/B20
B11/B21
L
R10/R20
R11/R21
R12/R22
R13/R23
R14/R24
R15/R25
G10/G20
G11/G21
G12/G22
G13/G23
G14/G24
G15/G25
B10/B20
B11/B21
B12/B22
B13/B23
B14/B24
B15/B25
HSYNC
VSYNC
DE
R16/R26
R17/R27
G16/G26
G17/G27
B16/B26
B17/B27
L
20 / 27
●LVCMOS Data Inputs Timing Diagrams in Single Link
Dual-in / Single-out Mode
(MODE<1:0>=LH, FLIP=L, MAP=H)
LVDS Data Output
R1n,~B1n
n=0~7
VDD
DATA1n-1
DATA1n
DATA1n+1
GND
R2n,~B2n
n=0~7
VDD
DATA2n-1
DATA2n
DATA2n+1
GND
LVCMOS Data Input
Figure-13 LVCMOS Data Inputs Timing Diagrams in Single Link
21 / 27
●LVCMOS Data Inputs Timing in Single Link
Single-in / Dual-out Mode
(MODE<1:0>=HH, FLIP=L)
Table 13 : LVCMOS Data Inputs Timing Diagrams in Single Link
1st Pixel Data
2nd Pixel Data
LVDS
Output Data
(1st Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
LVDS
Output Data
(1st Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
TA10
R12
R10
TA20
R12+1
R10+1
TA11
R13
R11
TA21
R13+1
R11+1
TA12
R14
R12
TA22
R14+1
R12+1
TA13
R15
R13
TA23
R15+1
R13+1
TA14
R16
R14
TA24
R16+1
R14+1
TA15
R17
R15
TA25
R17+1
R15+1
TA16
G12
G10
TA26
G12+1
G10+1
TB10
G13
G11
TB20
G13+1
G11+1
TB11
G14
G12
TB21
G14+1
G12+1
TB12
G15
G13
TB22
G15+1
G13+1
TB13
G16
G14
TB23
G16+1
G14+1
TB14
G17
G15
TB24
G17+1
G15+1
TB15
B12
B10
TB25
B12+1
B10+1
TB16
B13
B11
TB26
B13+1
B11+1
TC10
B14
B12
TC20
B14+1
B12+1
TC11
B15
B13
TC21
B15+1
B13+1
TC12
B16
B14
TC22
B16+1
B14+1
TC13
B17
B15
TC23
B17+1
B15+1
TC14
HSYNC
HSYNC
TC24
HSYNC+1
HSYNC+1
TC15
VSYNC
VSYNC
TC25
VSYNC+1
VSYNC+1
TC16
DE
DE
TC26
DE+1
DE+1
TD10
R10
R16
TD20
R10+1
R16+1
TD11
R11
R17
TD21
R11+1
R17+1
TD12
G10
G16
TD22
G10+1
G16+1
TD13
G11
G17
TD23
G11+1
G17+1
TD14
B10
B16
TD24
B10+1
B16+1
TD15
TD16
B11
L
B17
L
TD25
TD26
B11+1
L
B17+1
L
22 / 27
●LVCMOS Data Inputs Timing in Dual Link
Single-in / Dual-out Mode
(MODE<1:0>=HL, FLIP=L, MAP=H)
LVDS Data Output
R1n,G1n,B1n
(n=0~7)
VDD
DATA1n-2
DATA1n-1
DATA1n
DATA1n+1
DATA1n+2
DATA1n+3
GND
LVCMOS Data Input
Figure-14 LVCMOS Data Inputs Timing in Dual Link
23 / 27
●LVCMOS Data Inputs Timing in Single Link
Single-in / Single-out Mode
(MODE<1:0>=HH, FLIP=L)
Table 14 : LVCMOS Data Inputs Timing Diagrams in Single Link
LVDS
Output Data
(1st Pixel Data)
MAP=H
Input Pin Name
MAP=L
Input Pin Name
TA10
R12
R10
TA11
R13
R11
TA12
R14
R12
TA13
R15
R13
TA14
R16
R14
TA15
R17
R15
TA16
G12
G10
TB10
G13
G11
TB11
G14
G12
TB12
G15
G13
TB13
G16
G14
TB14
G17
G15
TB15
B12
B10
TB16
B13
B11
TC10
B14
B12
TC11
B15
B13
TC12
B16
B14
TC13
B17
B15
TC14
HSYNC
HSYNC
TC15
VSYNC
VSYNC
TC16
DE
DE
TD10
R10
R16
TD11
R11
R17
TD12
G10
G16
TD13
G11
G17
TD14
B10
B16
TD15
TD16
B11
L
B17
L
24 / 27
●LVCMOS Data Inputs Timing Diagrams in Single Link
Single-in / Single-out Mode
(MODE<1:0>=HH, FLIP=L, MAP=H)
LVDS Data Output
R1n,G1n,B1n
(n=0~7)
VDD
DATA1n-1
DATA1n
DATA1n+1
GND
LVCMOS Data Input
Figure-15 LVCMOS Data Inputs Timing Diagrams in Single Link
25 / 27
●About the Power On Reset
Power On Reset is not mandatory for this device.
(The PD pin should be set to high level when Power On Reset procedure is not used.)
VDD
XRST
BU7988KVT
Figure–16 terminal connection when Power On Reset is not used
However, Power On Reset procedure is strongly recommend for internal logic initialization by following
two methods.
① The method of using CR circuit.
② The method of using external specific IC.
It is recommend to do enough examination for target application.
V DD
V DD
VDD
schottky barrier diode
10KΩ
V T
XRST
220Ω
Be careful of temperature of
the capacitor especially over
and again.
B characteristic ceramics and
polymer aluminum
are recommended.
+
XRST
2.2μF
Internal Reset
td
td is approximately equal to 20ms when the left RC coleus are applied.
Figure–17 Power On Reset by external a CR circuit
V DD
VDD
power on IC
(open drain
output)
V DD
Detection voltage
220KΩ
VDD
XRST
VOUT
0.1μF
GND
V T
XRST
Internal Reset
B Characteristic
ceramics.
td
Figure–18 Power On Reset by specific IC
26 / 27
+
TQFP100V
<Dimension>
<Packing information>
16.0 ± 0.3
14.0 ± 0.2
51
76
1.2Max.
1.0 ± 0.1
0.1 ± 0.1
0.5
16.0 ± 0.3
14.0 ± 0.2
26
1
0.5
25
0.2 ± 0.1
500pcs
Direction of product is fixed in a tray.
Direction
of feed
50
100
Tray(with dry pack)
Quantity
0.125 ± 0.1
1pin
75
Container
0.1
(Unit:mm)
※When you order , please order in times the amount of package quantity.
Catalog No.08T241A '08.6 ROHM ©