CSD17510Q5A www.ti.com SLPS271B – JULY 2010 – REVISED SEPTEMBER 2010 30V, N-Channel NexFET™ Power MOSFETs Check for Samples: CSD17510Q5A PRODUCT SUMMARY FEATURES 1 • • • • • • • 2 Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package VDS Drain to Source Voltage 30 V Qg Gate Charge Total (4.5V) 6.4 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage • Point-of-Load Synchronous Buck in Networking, Telecom, and Computing Systems Optimized for Control and Synchronous FET Applications The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. Top View S S 8 1 7 2 6 3 D D 4.1 mΩ 1.5 5 4 V Package Media CSD17510Q5A SON 5-mm × 6-mm Plastic Package 13-Inch Reel Qty Ship 2500 Tape and Reel Text Added For Spacing ABSOLUTE MAXIMUM RATINGS VALUE UNIT VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage 20 / –12 V Continuous Drain Current, TC = 25°C 100 A Continuous Drain Current(1) 20 A IDM Pulsed Drain Current, TA = 25°C(2) 129 A PD Power Dissipation(1) 3 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 54A, L = 0.1mH, RG = 25Ω 45 mJ ID (1) Typical RqJA = 41°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. (2) Pulse duration ≤300ms, duty cycle ≤2% D P0093-01 Text 4 Spacing RDS(on) vs VGS Text 4 Spacing GATE CHARGE 30 20 ID = 20A VGS - Gate-to-Source Voltage - V RDS(on) - On-State Resistance - mΩ VGS = 10V Device D D G mΩ TA = 25°C unless otherwise stated DESCRIPTION S nC 5.4 Text Added For Spacing ORDERING INFORMATION APPLICATIONS • 1.9 VGS = 4.5V 25 20 15 T C = 25°C T C = 125°C 10 5 ID = 20A VDS = 15V 18 16 14 12 10 8 6 4 2 0 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage - V 18 20 G006 0 5 10 15 Qg - Gate Charge - nC 20 25 G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CSD17510Q5A SLPS271B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, IDS = 250mA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = 20/-12V VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250mA RDS(on) Drain to Source On Resistance gfs Transconductance 30 1 V 1 mA 100 nA 1.5 2.1 V VGS = 4.5V, IDS = 20A 5.4 7.3 mΩ VGS = 10V, IDS = 20A 4.1 5.2 mΩ VDS = 15V, IDS = 20A 59 S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Gate Charge Total (4.5V) Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 15V, f = 1MHz VDS = 15V, IDS = 20A VDS = 13.5V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 20A,RG = 2Ω 960 1250 pF 630 820 pF pF 51 66 0.85 1.7 Ω 6.4 8.3 nC 1.9 nC 2.7 nC 1.5 nC 16 nC 7 ns 11 ns 9 ns 4.1 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 20A, VGS = 0V 0.85 VDD= 13.5V, IF = 20A, di/dt = 300A/ms 1 V 25 nC 24 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER RqJC Thermal Resistance Junction to Case RqJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 MIN (1) 2 TYP MAX UNIT 1.6 °C/W 51 °C/W 2 RqJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17510Q5A CSD17510Q5A www.ti.com SLPS271B – JULY 2010 – REVISED SEPTEMBER 2010 GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RqJA = 51°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RqJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA - Normalized Thermal Impedance 10 1 0.5 0.3 0.1 0.01 0.1 0.05 Duty Cycle = t1/t2 0.02 0.01 P Single Pulse t1 t2 0.001 0.0001 0.001 Typical RqJA = 100°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA 0.01 0.1 1 tp - Pulse Duration - s 10 100 1k G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17510Q5A 3 CSD17510Q5A SLPS271B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 VDS = 5V VGS = 10V IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A 60 50 VGS = 4.5V VGS = 4V 40 VGS = 3.5V 30 20 VGS = 3V 10 0 10 T C = -55°C 1 0.1 T C = 25°C 0.01 T C = 125°C 0.001 0 0.5 1 1.5 VDS - Drain-to-Source Voltage - V 2 0 1 G001 Figure 2. Saturation Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING ID = 20A VDS = 15V 18 Ciss = Cgd + Cgs C - Capacitance - nF 16 C - Capacitance - nF VGS - Gate-to-Source Voltage - V G002 10 14 12 10 8 6 1 Coss = Cds + Cgd Crss = Cgd 0.1 4 f = 1MHz VGS = 0V 2 0 0.01 0 5 10 15 Qg - Gate Charge - nC 20 25 0 5 G003 Figure 4. Gate Charge TEXT ADDED FOR SPACING 25 30 G004 TEXT ADDED FOR SPACING 30 RDS(on) - On-State Resistance - mΩ ID = 250µA 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -75 10 15 20 VDS - Drain-to-Source Voltage - V Figure 5. Capacitance 2 VGS(th) - Threshold Voltage - V 5 Figure 3. Transfer Characteristics 20 ID = 20A 25 20 15 T C = 25°C T C = 125°C 10 5 0 -25 25 75 T C - Case Temperature - °C 125 175 0 2 G005 Figure 6. Threshold Voltage vs. Temperature 4 2 3 4 VGS - Gate-to-Source Voltage - V 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage - V 18 20 G006 Figure 7. On-State Resistance vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17510Q5A CSD17510Q5A www.ti.com SLPS271B – JULY 2010 – REVISED SEPTEMBER 2010 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 ID = 20A VGS = 10V 1.4 ISD - Source-to-Drain Current - A Normalized On-State Resistance 1.6 1.2 1 0.8 0.6 0.4 0.2 -75 10 1 T C = 125°C 0.1 T C = 25°C 0.01 0.001 0.0001 -25 25 75 T C - Case Temperature - °C 125 0 175 0.2 Figure 8. Normalized On-State Resistance vs. Temperature TEXT ADDED FOR SPACING G008 TEXT ADDED FOR SPACING I(AV) - Peak Avalanche Current - A IDS - Drain-to-Source Current - A 1.2 100 100 10 1ms 10ms 1 11110 100ms Area Limited by RDS(on) 0.01 0.01 1 Figure 9. Typical Diode Forward Voltage 1k 0.1 0.4 0.6 0.8 VSD - Source-to-Drain Voltage - V G007 1s Single Pulse Typical R θJA = 100°C/W (min Cu) T C = 25°C 10 T C = 125°C DC 0.1 1 10 VDS - Drain-to-Source Voltage - V 100 1 0.01 0.1 1 t(AV) - Time in Avalanche - ms G009 Figure 10. Maximum Safe Operating Area 10 G010 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING IDS - Drain-to-Source Current - A 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 T C - Case Temperature - °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17510Q5A 5 CSD17510Q5A SLPS271B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com MECHANICAL DATA Q5A Package Dimensions L E2 H K 7 D2 3 4 b 4 5 5 6 3 6 e D1 7 2 2 8 8 1 1 q L1 Top View Bottom View Side View c A q E1 E Front View M0135-01 DIM 6 MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 1.17 1.27 1.37 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 q 0° Submit Documentation Feedback 12° Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17510Q5A CSD17510Q5A www.ti.com SLPS271B – JULY 2010 – REVISED SEPTEMBER 2010 Recommended PCB Pattern F1 F7 DIM F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket Spacer Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17510Q5A 7 CSD17510Q5A SLPS271B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com REVISION HISTORY Changes from Original (July 2010) to Revision A • Changed the Y axis scale for Figure 5 ................................................................................................................................. 4 Changes from Revision A (August 2010) to Revision B • 8 Page Page Changed RDS(on) Test Conditions From VGS = 8V To: VGS = 10V ......................................................................................... 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17510Q5A PACKAGE OPTION ADDENDUM www.ti.com 8-Sep-2010 PACKAGING INFORMATION Orderable Device CSD17510Q5A Status (1) PREVIEW Package Type Package Drawing SON DQJ Pins Package Qty 8 2500 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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