TI CSD17310Q5A

CSD17310Q5A
www.ti.com
SLPS255 – FEBRUARY 2010
30V, N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD17310Q5A
FEATURES
1
•
•
•
•
•
•
•
•
2
PRODUCT SUMMARY
Optimized for 5V Gate Drive
Ultralow Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package
VDS
Drain to Source Voltage
30
V
Qg
Gate Charge Total (4.5V)
8.9
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain to Source On Resistance
VGS(th)
•
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications,
and optimized for 5V gate drive applications.
Top View
D
mΩ
3.9
mΩ
1.3
V
Package
Media
CSD17310Q5A
13-Inch
Reel
Qty
Ship
2500
Tape and
Reel
Text and br Added for Spacing
Text and br Added for Spacing
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
VDS
Drain to Source Voltage
30
V
VGS
Gate to Source Voltage
+10 / –8
V
Continuous Drain Current, TC = 25°C
100
A
Continuous Drain Current (1)
21
A
IDM
Pulsed Drain Current, TA = 25°C (2)
134
A
PD
Power Dissipation (1)
3.1
W
S
2
7
D
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
S
3
6
D
EAS
Avalanche Energy, single pulse
ID = 58A, L = 0.1mH, RG = 25Ω
168
mJ
G
4
5
D
D
(1)
(2)
P0093-01
Text 4 Spacing
RDS(on) vs VGS
RqJA = 40°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick)
Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
Pulse duration ≤300ms, duty cycle ≤2%
Text 4 Spacing
GATE CHARGE
16
8
ID = 20A
14
VGS - Gate-to-Source Voltage - V
RDS(on) - On-State Resistance - mΩ
4.5
VGS = 8V
SON 5-mm × 6-mm
Plastic Package
ID
8
VGS = 4.5V
Device
DESCRIPTION
1
mΩ
Text and br Added for Spacing
Text and br Added for Spacing
ORDERING INFORMATION
Notebook Point of Load
Point-of-Load Synchronous Buck in
Networking, Telecom and Computing Systems
Optimized for Synchronous FET Applications
S
nC
5.7
Threshold Voltage
APPLICATIONS
•
•
2.1
VGS = 3V
12
10
T C = 125°C
8
6
4
T C = 25°C
2
0
ID = 20A
VDS = 15V
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G006
0
2
4
6
8
10
Qg - Gate Charge - nC
12
14
16
G003
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CSD17310Q5A
SLPS255 – FEBRUARY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, ID = 250mA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = +10/-8V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, ID = 250mA
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
30
0.9
V
1
mA
100
nA
1.3
1.8
V
VGS = 3V, ID = 20A
5.7
7.8
mΩ
VGS = 4.5V, ID = 20A
4.5
5.9
mΩ
VGS = 8V, ID = 20A
3.9
5.1
mΩ
VDS = 15V, ID = 20A
85
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
1200
1560
pF
630
820
Crss
pF
Reverse Transfer Capacitance
59
77
pF
RG
Series Gate Resistance
0.9
1.8
Ω
Qg
Gate Charge Total (4.5V)
8.9
11.6
nC
Qgd
Gate Charge Gate to Drain
2.1
nC
Qgs
Gate Charge Gate to Source
2.7
nC
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
Turn On Delay Time
tr
Rise Time
td(off)
Turn Off Delay Time
tf
Fall Time
VGS = 0V, VDS = 15V, f = 1MHz
VDS = 15V, IDS = 20A
VDS = 12.8V, VGS = 0V
VDS = 15V, VGS = 4.5V, IDS = 20A,
RG = 2Ω
1.4
nC
15.9
nC
6.5
ns
11.6
ns
15
ns
5
ns
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 20A, VGS = 0V
0.85
VDD= 12.8V, IF = 20A, di/dt = 300A/ms
1
V
21
nC
22
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
RqJC
RqJA
(1)
(2)
Thermal Resistance Junction to Ambient
(1) (2)
2
TYP
MAX
UNIT
1.9
°C/W
51
°C/W
2
RqJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
Text
Text
Text
Text
2
MIN
Thermal Resistance Junction to Case (1)
and
and
and
and
br
br
br
br
Added
Added
Added
Added
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for
for
for
for
Spacing
Spacing
Spacing
Spacing
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CSD17310Q5A
CSD17310Q5A
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SLPS255 – FEBRUARY 2010
GATE
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RqJA = 51°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
Source
Max RqJA = 123°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
ZqJA - Normalized Thermal Impedance
10
1
0.5
0.3
0.1
Duty Cycle = t1/t2
0.1
0.05
P
0.01
0.02
0.01
t1
t2
Single Pulse
0.001
0.001
0.01
Typical RqJA = 98°C/W (min Cu)
TJ = P ´ ZqJA ´ RqJA
0.1
1
tp - Pulse Duration - s
10
100
1k
G012
Figure 1. Transient Thermal Impedance
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3
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SLPS255 – FEBRUARY 2010
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
60
60
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
VDS = 5V
50
VGS = 8V
40
VGS = 4.5V
30
VGS = 3.5V
20
VGS = 3V
VGS = 2.5V
10
0
50
T C = 125°C
40
30
T C = 25°C
20
T C = -55°C
10
0
0
0.2
0.4
0.6
0.8
VDS - Drain-to-Source Voltage - V
1
1
1.2
1.4
1.6
1.8
2
2.2
VGS - Gate-to-Source Voltage - V
G001
Figure 2. Saturation Characteristics
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
ID = 20A
VDS = 15V
7
f = 1MHz
VGS = 0V
2.5
6
C - Capacitance - nF
VGS - Gate-to-Source Voltage - V
G002
3
5
4
3
2
Coss = Cds + Cgd
2
Ciss = Cgd + Cgs
1.5
1
Crss = Cgd
0.5
1
0
0
0
2
4
6
8
10
Qg - Gate Charge - nC
12
14
16
0
5
10
15
20
VDS - Drain-to-Source Voltage - V
G003
Figure 4. Gate Charge
25
30
G004
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
16
1.8
RDS(on) - On-State Resistance - mΩ
ID = 250µA
1.6
VGS(th) - Threshold Voltage - V
2.6
Figure 3. Transfer Characteristics
8
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-75
ID = 20A
14
12
10
T C = 125°C
8
6
4
T C = 25°C
2
0
-25
25
75
T C - Case Temperature - °C
125
175
0
1
G005
Figure 6. Threshold Voltage vs. Temperature
4
2.4
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G006
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
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SLPS255 – FEBRUARY 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
ID = 20A
VGS = 8V
1.4
ISD - Source-to-Drain Current - A
Normalized On-State Resistance
1.6
1.2
1
0.8
0.6
0.4
0.2
-75
10
1
T C = 125°C
0.1
T C = 25°C
0.01
0.001
0.0001
-25
25
75
T C - Case Temperature - °C
125
175
0
0.2
G007
Figure 8. Normalized On-State Resistance vs. Temperature
1
G008
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1k
I(AV) - Peak Avalanche Current - A
1k
IDS - Drain-to-Source Current - A
0.4
0.6
0.8
VSD - Source-to-Drain Voltage - V
100
1ms
10
10ms
1
1001
100ms
Area Limited
by RDS(on)
0.1
1s
Single Pulse
Typical R θJA = 98°C/W (min Cu)
0.01
0.01
DC
0.1
1
10
VDS - Drain-to-Source Voltage - V
100
100
10
T C = 25°C
T C = 125°C
1
0.01
G009
Figure 10. Maximum Safe Operating Area
0.1
1
10
t(AV) - Time in Avalanche - ms
100
G010
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain-to-Source Current - A
120
100
80
60
40
20
0
-50
-25
0
25
50
75
100 125
T C - Case Temperature - °C
150
175
G011
Figure 12. Maximum Drain Current vs. Temperature
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CSD17310Q5A
SLPS255 – FEBRUARY 2010
www.ti.com
MECHANICAL DATA
Q5A Package Dimensions
L
E2
H
K
7
D2
3
4
b
4
5
5
6
3
6
e
D1
7
2
2
8
8
1
1
q
L1
Top View
Bottom View
Side View
c
A
q
E1
E
Front View
M0135-01
DIM
MILLIMETERS
MIN
NOM
MAX
A
0.90
1.00
1.10
b
0.33
0.41
0.51
c
0.20
0.25
0.30
D1
4.80
4.90
5.00
D2
3.61
3.81
3.96
E
5.90
6.00
6.10
E1
5.70
5.75
5.80
E2
3.38
3.58
3.78
e
6
1.27 BSC
H
0.41
K
1.10
0.51
0.61
L
0.51
0.61
0.71
L1
0.06
0.13
0.20
q
0°
Submit Documentation Feedback
12°
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CSD17310Q5A
CSD17310Q5A
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SLPS255 – FEBRUARY 2010
MILLIMETERS
INCHES
Recommended PCB Pattern
DIM
MIN
MAX
MIN
MAX
F1
F1
6.205
6.305
0.244
0.248
F2
4.46
4.56
0.176
0.18
F3
4.46
4.56
0.176
0.18
F4
0.65
0.7
0.026
0.028
F5
0.62
0.67
0.024
0.026
F6
0.63
0.68
0.025
0.027
F7
0.7
0.8
0.028
0.031
F8
0.65
0.7
0.026
0.028
F9
0.62
0.67
0.024
0.026
F7
F3
8
1
F2
F11
F5
F9
5
4
F6
F10
4.9
5
0.193
0.197
F11
4.46
4.56
0.176
0.18
F8
F4
F10
M0139-01
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
Q5A Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
R 0.30 TYP
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket
6. MSL1 260°C (IR and convection) PbF reflow compatible
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SLPS255 – FEBRUARY 2010
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Package Marking Information
Location
8
1st Line
CSD
= Fixed Characters
NNNNN
= Product Code
2nd Line (Date Code)
YY
= Last 2 digits of the Year
WW
= 2-digit Work Week
C
= Country of Origin
5
5
8
4
1
CSDNNNNN
YYWWC
LLLLL
> Philippines = P
> Taiwan = T
> China = C
3rd Line
LLLLL
= Last 5 digits of the Wafer Lot #
1
4
Pin 1
Identifier
M0136-01
8
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Product Folder Link(s): CSD17310Q5A
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
CSD17310Q5A
ACTIVE
SON
DQJ
Pins Package Eco Plan (2)
Qty
8
2500
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
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Addendum-Page 1
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