TI SN74BCT2241DW

SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
D Available in the Texas Instruments
D
D
D
D
D
D
D
NanoStar and NanoFree Packages
Low Static-Power Consumption;
ICC = 0.9 µA Max
Low Dynamic-Power Consumption;
Cpd = 4.6 pF Typ at 3.3 V
Low Input Capacitance; Ci = 1.5 pF Typ
Low Noise − Overshoot and Undershoot
<10% of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Includes Schmitt-Trigger Inputs
Wide Operating VCC Range of 0.8 V to 3.6 V
DBV OR DCK PACKAGE
(TOP VIEW)
B
GND
A
1
6
2
5
3
4
D Optimized for 3.3-V Operation
D 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
D tpd = 5.3 ns Max at 3.3 V
D Suitable for Point-to-Point Applications
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
D
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
ESD Protection Exceeds ±5000 V With
Human-Body Model
YEP OR YZP PACKAGE
(BOTTOM VIEW)
A
GND
B
C
VCC
Y
3 4
2 5
1 6
Y
VCC
C
description /ordering information
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC
range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent
signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Static-Power Consumption
(µA)
100%
100%
80%
80%
40%
3
60%
3.3-V
Logic†
3.3-V
Logic
LVC †
40%
AUP
0%
2.5
Input
2
Output
1.5
1
0.5
20%
20%
0%
3.5
Voltage − V
60%
Switching Characteristics
at 25 MHz†
Dynamic-Power Consumption
(pF)
AUP
† Single, dual, and triple gates
Figure 1. AUP − The Lowest-Power Family
0
−0.5
20 25 30
Time − ns
† AUP1G08 data at CL = 15 pF
0
5
10
15
35
40
45
Figure 2. Excellent Signal Integrity
The SN74AUP1G98 features configurable multiple functions. The output state is determined by eight patterns
of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter.
All inputs can be connected to VCC or GND.
The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition
and better switching-noise immunity at the input.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2004, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
POST OFFICE BOX 655303
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1
SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
description/ordering information (continued)
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
−40°C to 85°C
TOP-SIDE
MARKING‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel
SN74AUP1G98YEPR
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel
SN74AUP1G98YZPR
SOT (SOT-23) − DBV
Tape and reel
SN74AUP1G98DBVR
H98_
SOT (SC-70) − DCK
Tape and reel
SN74AUP1G98DCKR
HR_
_ _ _HR_
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
C
B
A
OUTPUT
Y
L
L
L
H
L
L
H
H
L
H
L
L
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
H
H
H
H
L
logic diagram (positive logic)
A
3
4
B
C
2
1
6
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Y
SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
FUNCTION SELECTION TABLE
FIGURE NO.
LOGIC FUNCTION
2-to-1 data selector with inverted output
3
2-input NAND gate
4
2-input NOR gate with one inverted input
5
2-input AND gate with one inverted input
5
2-input NAND gate with one inverted input
6
2-input OR gate with one inverted input
6
2-input NOR gate
7
Noninverted buffer
8
Inverter
9
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3
SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
logic configurations
VCC
VCC
C
B
B
Y
A
A
1
6
2
5
3
4
C
C
Y
A
A
Y
GND
1
6
2
5
3
4
C
Y
GND
Figure 3. 2-to-1 Data Selector
With Inverted Output
When C is L, Y = B
When C is H, Y = A
Figure 4. 2-Input NAND Gate
VCC
C
VCC
C
Y
C
Y
B
A
Y
A
A
1
6
2
5
3
4
B
C
C
Y
Y
B
1
6
2
5
3
4
C
Y
GND
GND
Figure 6. 2-Input NAND Gate
With One Inverted Input
2-Input OR Gate With One Inverted Input
Figure 5. 2-Input NOR Gate
With One Inverted Input
2-Input AND Gate With One Inverted Input
VCC
VCC
C
B
Y
B
1
6
2
5
3
4
C
C
Y
Y
1
6
2
5
3
4
GND
GND
Figure 8. Noninverted Buffer
Figure 7. 2-Input NOR Gate
VCC
B
B
Y
1
6
2
5
3
4
Y
GND
Figure 9. Inverter
4
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C
Y
SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Output voltage range in the high or low state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VI
Supply voltage
VO
Output voltage
Input voltage
VCC = 0.8 V
VCC = 1.1 V
IOH
IOL
∆t/∆v
High-level output current
Low-level output current
Input transition rise or fall rate
MIN
MAX
0.8
3.6
UNIT
V
0
3.6
V
0
VCC
−20
µA
V
−1.1
VCC = 1.4 V
VCC = 1.65
−1.7
VCC = 2.3 V
VCC = 3 V
−3.1
VCC = 0.8 V
VCC = 1.1 V
20
−1.9
mA
−4
µA
1.1
VCC = 1.4 V
VCC = 1.65 V
1.7
VCC = 2.3 V
VCC = 3 V
3.1
VCC = 0.8 V to 3.6 V
200
1.9
mA
4
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VT+
Positive-going
input threshold
voltage
VT−
Negative-going
input threshold
voltage
∆V
VT
Hysteresis
(VT+ − VT−)
VOH
0.3
0.6
0.3
0.9
0.53
0.9
1.4 V
0.74
1.11
0.74
1.11
1.65 V
0.91
1.29
0.91
1.29
2.3 V
1.37
1.77
1.37
1.77
3V
1.88
2.29
1.88
2.29
0.1
0.6
0.1
0.6
1.1 V
0.26
0.65
0.26
0.65
1.4 V
0.39
0.75
0.39
0.75
1.65 V
0.47
0.84
0.47
0.84
2.3 V
0.69
1.04
0.69
1.04
1.24
3V
0.88
1.24
0.88
0.8 V
0.07
0.5
0.07
0.5
1.1 V
0.08
0.46
0.08
0.46
1.4 V
0.18
0.56
0.18
0.56
1.65 V
0.27
0.66
0.27
0.66
2.3 V
0.53
0.92
0.53
0.92
0.79
1.31
0.79
1.31
VOL
∆Ioff
ICC
†
6
1.03
1.3
2.05
1.97
1.9
1.85
2.72
2.67
2.6
0.1
0.3 × VCC
1.4 V
0.31
0.37
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
3V
V
2.55
0.3 × VCC
2.3 V
V
V
1.1 V
IOL = 2.3 mA
IOL = 3.1 mA
All inputs
1.11
1.32
0.1
IOL = 2.7 mA
IOL = 4 mA
II
Ioff
1.4 V
0.8 V to 3.6 V
IOL = 1.7 mA
IOL = 1.9 mA
V
VCC − 0.1
0.7 × VCC
1.65 V
3V
IOL = 20 µA
IOL = 1.1 mA
VCC − 0.1
0.75 × VCC
UNIT
0.6
0.8 V
2.3 V
IOH = −2.7 mA
IOH = −4 mA
TA = −40°C TO 85°C
MIN
MAX
0.53
1.1 V
IOH = −2.3 mA
IOH = −3.1 mA
MAX
1.1 V
0.8 V to 3.6 V
IOH = −1.7 mA
IOH = −1.9 mA
TA = 25°C
TYP
0.8 V
3V
IOH = −20 µA
IOH = −1.1 mA
MIN
V
0.44
0.45
VI = GND to 3.6 V
VI or VO = 0 V to 3.6 V
0 V to 3.6 V
0.1
0.5
µA
0V
0.2
0.6
µA
VI or VO = 0 V to 3.6 V
VI = GND or
IO = 0
(VCC to 3.6 V)
0 V to 0.2 V
0.2
0.6
µA
0.8 V to 3.6 V
0.5
0.9
µA
40
50
µA
∆ICC
VI = VCC − 0.6 V†
IO = 0
One input at VCC − 0.6 V, other inputs at VCC or GND
3.3 V
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SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
Ci
VI = VCC or GND
Co
VO = GND
VCC
MIN
TA = 25°C
TYP
0V
1.5
3.6 V
1.5
0V
3
TA = −40°C TO 85°C
MIN
MAX
MAX
UNIT
pF
pF
switching characteristics over recommended operating free-air temperature range, CL = 5 pF
(unless otherwise noted) (see Figures 10 and 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
A, B, or C
Y
TA = −40°C
TO 85°C
TA = 25°C
VCC
TYP
MAX
MIN
UNIT
MAX
22.2
1.2 V ± 0.1 V
2.7
9.1
13.6
2.2
17
1.5 V ± 0.1 V
2
6.4
9.2
1.5
11.1
1.8 V ± 0.15 V
1.4
5.2
7.2
0.9
8.9
2.5 V ± 0.2 V
1.2
3.8
5.3
0.7
6.3
3.3 V ± 0.3 V
1
3.1
4.5
0.5
5.3
ns
switching characteristics over recommended operating free-air temperature range, CL = 10 pF
(unless otherwise noted) (see Figures 10 and 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
1.2 V ± 0.1 V
tpd
A, B, or C
Y
TA = −40°C
TO 85°C
TA = 25°C
VCC
TYP
UNIT
MAX
MIN
MAX
25.4
5.2
10.4
15.4
4.7
19
1.5 V ± 0.1 V
4
7.4
10.5
3.5
12.6
1.8 V ± 0.15 V
3.1
6
8.3
2.6
10.2
2.5 V ± 0.2 V
2.7
4.5
6.1
2.2
7.3
3.3 V ± 0.3 V
2.5
3.7
5
2
6
ns
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figures 10 and 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
A, B, or C
Y
POST OFFICE BOX 655303
TA = −40°C
TO 85°C
TA = 25°C
VCC
TYP
MAX
MIN
MAX
28.7
1.2 V ± 0.1 V
3.7
11.5
17
3.2
21.1
1.5 V ± 0.1 V
2.8
8.3
11.6
2.3
14
1.8 V ± 0.15 V
2.1
6.7
9.2
1.6
11.3
2.5 V ± 0.2 V
1.8
5
6.7
1.3
8.1
3.3 V ± 0.3 V
1.6
4.1
5.5
1.1
6.6
• DALLAS, TEXAS 75265
UNIT
ns
7
SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figures 10 and 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
A, B, or C
Y
TA = −40°C
TO 85°C
TA = 25°C
VCC
TYP
UNIT
MAX
MIN
MAX
39.7
1.2 V ± 0.1 V
5.1
15.3
21.6
4.6
26.8
1.5 V ± 0.1 V
3.9
10.9
14.6
3.4
17.6
1.8 V ± 0.15 V
3.1
8.9
11.5
2.6
14.1
2.5 V ± 0.2 V
2.6
6.7
8.4
2.1
10.1
3.3 V ± 0.3 V
2.3
5.5
6.9
1.8
8.3
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
8
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
POST OFFICE BOX 655303
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VCC
0.8 V
TYP
UNIT
4
1.2 V ± 0.1 V
4
1.5 V ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
4.3
3.3 V ± 0.3 V
4.6
pF
SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Duration)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
0V
tPLH
tsu
VOH
VM
Output
th
VCC
VM
VOL
Data Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 10. Load Circuit and Voltage Waveforms
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SCES506B − NOVEMBER 2003 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
5 kΩ
From Output
Under Test
CL
(see Note A)
S1
GND
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 11. Load Circuit and Voltage Waveforms
10
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP1G98DBVR
ACTIVE
SOT-23
DBV
6
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DBVT
ACTIVE
SOT-23
DBV
6
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DCKR
ACTIVE
SC70
DCK
6
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98DCKT
ACTIVE
SC70
DCK
6
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G98YEPR
ACTIVE
WCSP
YEP
6
3000
None
SNPB
Level-1-260C-UNLIM
SN74AUP1G98YZPR
ACTIVE
WCSP
YZP
6
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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