Genesys Logic, Inc. GL813 USB 2.0 CompactFlash Card Reader Controller Specification 1.2 April 12, 2002 Genesys Logic, Inc. 10F., No.11, Ln.155, Sec.3, Peishen Rd., Shenkeng, Taipei, Taiwan Tel: 886-2-2664-6655 Fax: 886-2-2664-5757 http://www.genesyslogic.com GL813 - USB2.0 CompactFlash Card Reader Controller Contents 1. General Description ......................................................................................... 3 2. Features ............................................................................................................ 4 3. Function Block ................................................................................................. 5 3.1 Block Diagram .............................................................................................. 5 3.2 Functional Overview ..................................................................................... 6 4. Pinning Information ......................................................................................... 7 4.1 48-pin LQFP Package .................................................................................. 7 4.2 100-pin LQFP package................................................................................. 9 5. Functional Description .................................................................................. 15 5.1 Transmit Operation ..................................................................................... 15 5.2 Receive Operation...................................................................................... 17 6. Electrical Characteristics .............................................................................. 19 6.1 Absolute Maximum Ratings ........................................................................ 19 6.2 Recommended Operating Conditions......................................................... 19 6.3 DC Characteristics (Digital Pins) ................................................................ 19 6.4 DC Characteristics (D+/D-)......................................................................... 20 6.5 Switching Characteristics ........................................................................... 20 7. Package Dimension ....................................................................................... 22 7.1 48-pin LQFP Package ................................................................................ 22 7.2 100-pin LQFP Package .............................................................................. 23 8. Revision History............................................................................................. 24 ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 2 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 1. General Description The GL813 is a high performance, low cost USB2.0 CompactFlash-single card reader controller. With the integration of GenesysLogic own design USB 2.0 high speed UTMI transceiver, the GL813 has made a conspicuous improvement with full speed USB 1.1 card readers on data transfer rate between PC host and flash memory card. There are totally 4 endpoints in GL813 controller, Control, Bulk In, Bulk Out, and Interrupt. Complies with USB 480Mbps specification ver. 2.0 and USB Storage Class specification ver. 1.0. (Bulk only protocol), the GL813 can support not only plug and play but also Windows ME/ 2000/ XP default driver. For the EMI consideration, the GL813 uses 12MHZ crystal and slew-rate controlled pads to reduce the EMI issue. The GL813 is 48-pin LQFP package (9mmX9mm) to make the best cost competitive for the high speed single flash card reader design and applications. Also we provide 100-pin LQFP package (14mmX14mm) with external ROM/ Flash for design flexibility. ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 3 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 2. Features Complies with Universal Serial Bus specification rev. 2.0. Complies with Compact Flash specification rev. 1.4. Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) Operating system supported: Win XP/ 2000/ ME/ 98/ 98SE; Mac OS 9.X/ X. Supports 4 endpoints: Control/ Bulk Read/ Bulk Write/ Interrupt. 64/ 512 bytes Data Payload for full / high speed Bulk Endpoint. Supports 8-bit / 16-bit Standard PIO mode interface. Embedded USB 2.0 UTMI transceiver. Embedded 7.5 MIPS RISC CPU. Supports external ROM/ Flash modes for design flexibility. (100-pin LQFP) Supports Power Down mode and USB suspend indicator. Supports USB 2.0 TEST mode features. 12MHz external clock to provide better EMI3.3V power input. 5V tolerance pad for Compact Flash Card interface. Supports EEPROM to customize USB VID / PID and String Descriptors. Available in 48-pin (9mmX9mm) / 100-pin (14mmX14mm) LQFP package. ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 4 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 3. Function Block 3.1 Block Diagram CPU Control Register CONTROL FIFO Compact TXFIFO0 Flash Controller TXFIFO1 Engine SIE UTMI USB2.0 LOGIC TXCVR RXFIFO0 RXFIFO1 12MHz X40 Clkgen ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 5 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 3.2 Functional Overview 3.2.1 USB 2.0 TXCVR The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS signaling. 3.2.2 UTMI Logic The UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles the low level USB protocol and signaling. The major jobs of UTMI Logic is data and clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test modes supporting and serial / parallel conversion. 3.2.3 PLL 40XPLL block will provide 480MHz for USB HS data transmission. 3.2.4 CLKGEN CLKGEN is the clock generator block for the logic blocks. It generates 15MHz clock for micro controller, 12MHz for PIO mode, and 30MHz clock for UTMI, SIE, and FIFO. 3.2.5 CPU The CPU is the control center of GL813. It’s an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command, then it re-assigns tasks to the CompactFlash controller engine, GPIO, FIFO, and response proper data/ status to USB host. 3.2.6 CompactFlash Controller Engine The CompactFlash controller engine is extended from standard ATA/ ATAPI protocol. It supports PIO mode data transfers. 3.2.7 FIFOs Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from CompactFlash controller engine, and re-direct to USB SIE logic. RXFIFO0 / RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE logic, and re-direct to CompactFlash controller engine. 3.2.8 Control Registers Control Register configures GL813 to proper operation. For example, CPU can set register to generate wakeup event, enter suspend, transmits proper USB packet to host. ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 6 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 4. Pinning Information IODD[0] 37 IODD[1] 38 IODD[2] 39 IODD[3] 40 DGND2 41 42 DVCC2 IODD[4] 43 IODD[5] 44 IODD[6] 45 IODD[7] 46 CS 47 48 CFRST 4.1 48-pin LQFP 33 INTRQ IODD[11] 5 DA1/ Dl DVCC1 6 GL813 32 31 DA0 DGND1 7 CS0_ IODD[12] 8 48 LQFP 30 29 TEST IODD[13] 9 28 CFDET IODD[14] 10 27 AGND1 !ODD[15] 11 26 X1 DO 12 25 X2 AVCC1 RREF AGND0 DMH DMF DPH DPF AVCC0 RPU RESET# I/O Pad Type CFPWR IODD [8:11] B I Tri-state Tri-state 6 DVCC1 P Power Digital VCC 7 DGND1 P Power Digital ground IODD [12:15] B Tri-state IDE data bus 12~15 12 DO I Tri-state DO from EEPROM 13 CS1_ O Tri-state IDE chip select 1 1 2~5 8~11 Name DA2/ SK 13 CS1_ Pin # 24 4 23 IODD[10] 22 IORDY 21 34 20 3 19 IODD[9] 18 DIOR_ 17 35 16 2 IODD[8] 15 DIOW_ 1 14 36 CFPWR ©2001-2002 Genesys Logic Inc.—All rights reserved. Description Compact flash card power control IDE data bus 8~11 Page 7 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller Pin # Name I/O Pad Type Description 14 15 DA2 / SK RESET# O I Tri-state Pull-high IDE address 2 / SK to EEPROM HW reset 16 RPU A U20mia 3.3v output 17 AVCC0 P Power Analog VCC 18 DPF B U20mia Full speed DP 19 DPH B U20mia High speed DP 20 DMF B U20mia Full speed DM 21 DMH B U20mia High speed DM 22 AGND0 P Power Analog ground 23 RREF 24 AVCC1 P Power Analog VCC 25 X2 B Clock Crystal output 26 X1 I Clock Crystal input, 12Mhz 27 AGND1 P Power Analog ground 28 CFDET I Tri-state Compact flash card detect 29 TEST I Pull-low TEST mode input 30 CS0_ O Tri-state IDE Chip select 0 31 DA0 O Tri-state IDE address 0 32 DA1 / DI O Tri-state IDE address 1 / DI to EEPROM 33 INTRQ I Tri-state IDE Interrupt request 34 IORDY I Tri-state IDE IO ready 35 DIOR_ O Tri-state IDE read signal 36 DIOW_ O Tri-state IDE write signal IODD [0:3] B Tri-state IDE data bus 0~3 41 DGND2 P Power Digital ground 42 DVCC2 P Power Digital VCC IODD [4:7] B Tri-state IDE data bus 4~7 47 CS O Tri-state CS to EEPROM 48 CFRST B Tri-state Compact Flash Card HW reset 37~40 43~46 U20mia Reference resister connect (*) (*) RREF must be connected with a 510 ohm resister to ground. ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 8 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller NC NC NC NC GPIO8 GPIO5 GPIO6 IODD8 IODD9 IODD10 IODD11 DVCC1 NC NC DGND1 IODD12 IODD13 IODD14 IODD15 CBLID_ GL813 100 LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DIOR_ IORDY DMACK_ INTRQ GPIO13 GPIO14 GPIO15 GPIO16 DA1 DA0 CS0_ GPIO17 GPIO18 GPIO19 EXT15 EXT14 NC AGND1 X1 X2 NC NC NC NC EXT5 NC NC NC NC EXT6 EXT7 EXT8 EXT9 EXT10 EXT11 EXT12 EXT13 CS1_ DA2 RESET# RPU AVCC0 DPF DPH DMF DMH AGND0 RREF AVCC1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 EXT0 EXT1 EXT2 EXT3 EXT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GPIO7 GPIO4 GPIO3 GPIO2 GPIO1 IODD7 IODD6 IODD5 IODD4 DVCC2 DGND2 IODD3 IODD2 IODD1 IODD0 DMARQ GPIO9 GPIO10 GPIO11 GPIO12 NC NC NC NC DIOW_ 4.2 100-pin LQFP ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 9 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller Pin # Name I/O Pad Type Description 1 NC - - - 2 NC - - - 3 NC - - - 4 NC - - - 5 GPIO8 B Tri-state GPIO8 (*) 6 GPIO5 B Tri-state GPIO5 7 GPIO6 B Tri-state GPIO6 IODD [8:11] B Tri-state IDE data bus 8 ~ 11 12 DVCC1 P Power 13 NC - - - 14 NC - - - 15 DGND1 P Power IODD [12:15] B Tri-state IDE data bus 12 ~ 15 CBLID_ I Tri-state Cable select input 8~11 16~19 20 21 NC/ECPURD/EROMD0 I Pull-low 22 NC/ECPUWR/EROMD1 I Pull-low 23 NC/ECPUA5/EROMD2 I Pull-low 24 NC/ECPUA4/EROMD3 I Pull-low 25 NC/ECPUA3/EROMD4 I Pull-low ©2001-2002 Genesys Logic Inc.—All rights reserved. Digital VCC Digital ground NC: Embedded CPU mode ECPURD: Read signal when external CPU mode EROMD0: Data0 when external ROM mode NC: Embedded CPU mode ECPUWR: Write signal when external CPU mode EROMD1: Data1 when external ROM mode NC: Embedded CPU mode ECPUA5: Address5 when external CPU mode EROMD2: Data2 when external ROM mode NC: when embedded CPU mode ECPUA4: Address4 when external CPU mode EROMD3: Data3 when external ROM mode NC: Embedded CPU mode ECPUA3: Address3 when external CPU mode EROMD4: Data4 when external ROM mode Page 10 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller Pin # Name I/O Pad Type Description 26 NC/ECPUA2/EROMD5 I Pull-low 27 NC - - NC: Embedded CPU mode ECPUA2: Address2 when external CPU mode EROMD5: Data5 when external ROM mode - 28 NC - - - 29 NC - - - 30 NC - - - 31 NC/ECPUA1/EROMD6 I Pull-low 32 NC/ECPUA0/EROMD7 I Pull-low 33 NC/ECPUD7/EROMD8 B Pull-low 34 NC/ECPUD6/EROMD9 B Pull-low 35 NC/ECPUD5/EROMD10 B Pull-low 36 NC/ECPUD4/EROMD11 B Pull-low 37 NC/ECPUD3/EROMD12 B Pull-low ©2001-2002 Genesys Logic Inc.—All rights reserved. NC: Embedded CPU mode ECPUA1: Address1 when external CPU mode EROMD6: Data6 when external ROM mode NC: Embedded CPU mode ECPUA0: Address0 when external CPU mode EROMD7: Data7 when external ROM mode NC: Embedded CPU mode ECPUD7: Data7 when external CPU mode EROMD8: Data8 when external ROM mode NC: Embedded CPU mode ECPUD6: Data6 when external CPU mode EROMD9: Data9 when external ROM mode NC: Embedded CPU mode ECPUD5: Data5 when external CPU mode EROMD10: Data10 when external ROM mode NC: Embedded CPU mode ECPUD4: Data4 when external CPU mode EROMD11: Data11 when external ROM mode NC: Embedded CPU mode ECPUD3: Data3 when external CPU mode EROMD12: Data12 when external ROM mode Page 11 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller Pin # Name I/O Pad Type Description 38 NC/ECPUD2/EROMD13 B Pull-low 39 CS1_ O Tri-state NC: Embedded CPU mode ECPUD2: Data2 when external CPU mode EROMD13: Data13 when external ROM mode Chip select 1 40 DA2 O Tri-state IDE address 2 41 RESET# I Pull-high Reset pin 42 RPU A U20mia 3.3v output 43 AVCC0 P Power Analog VCC 44 DPF B U20mia Full speed DP 45 DPH B U20mia High speed DP 46 DMF B U20mia Full speed DM 47 DMH B U20mia High speed DM 48 AGND0 P Power Analog ground 49 RREF 50 AVCC1 P Power 51 NC - - - 52 NC - - - 53 NC - - - 54 NC - - - 55 X2 B Clock Crystal output 56 X1 I Clock Crystal input, 12Mhz 57 AGND1 P Power Analog ground 58 NC - - 59 60 61 62 NC/ECPUD1/EROMA0 NC/ECPUD0/EROMA1 GPIO19 GPIO18/GPIO18/EROM A11 U20mia B B B B Pull-low Pull-low Pull-low Pull-low ©2001-2002 Genesys Logic Inc.—All rights reserved. Reference resister connect (*) Analog VCC NC: Embedded CPU mode ECPUD1: Data1 when CPU mode EROMA0: Address0 when ROM mode NC: Embedded CPU mode ECPUD0: Data0 when CPU mode EROMA1: Address1 when ROM mode GPIO19 GPIO18: for embedded or CPU mode EROMA11: Address11 external ROM mode external external external external external Page 12 of 24 when GL813 - USB2.0 CompactFlash Card Reader Controller Pin # Name 63 GPIO17/GPIO17/EROM A10 64 Pad Type Description B Pull-low GPIO17: For embedded or external CPU mode EROMA10: Address10 when external ROM mode CS0_ O Tri-state Chip select 0 65 DA0 O Tri-state IDE address 0 66 DA1 O Tri-state IDE address 1 67 GPIO16/GPIO16/EROM A9 Pull-low GPIO16: For embedded or external CPU mode EROMA9: Address9 when external ROM mode Pull-low GPIO15: For embedded or external CPU mode EROMA8: Address8 when external ROM mode Pull-low GPIO14: For embedded or external CPU mode EROMA7: Address7 when external ROM mode 68 GPIO15/GPIO15/EROM A8 I/O B B 69 GPIO14/GPIO15/EROM A7 70 GPIO13/GPIO14/EROM A6 B Pull-low GPIO13: For embedded or external CPU mode EROMA6: Address6 when external ROM mode 71 INTRQ I Tri-state IDE interrupt input 72 DMACK_ O Tri-state IDE acknowledge 73 IORDY I Pull-high IDE ready 74 DIOR_ O Tri-state IDE read signal 75 NC - - 76 DIOW_ O Tri-state 77 NC - - - 78 NC - - - 79 NC - - - 80 NC - - - 81 GPIO12/GPIO13/EROM A5 B Pull-low 82 GPIO11/GPIO12/EROM A4 B Pull-low B ©2001-2002 Genesys Logic Inc.—All rights reserved. IDE write signal GPIO12: For embedded or external CPU mode EROMA5: Address5 when external ROM mode GPIO11: For embedded or external CPU mode EROMA4: Address4 when external ROM mode Page 13 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller Pin # Name 83 GPIO10/GPIO10/EROM A3 I/O Pad Type Description 84 GPIO9/GPIO9/EROMA2 B Pull-low 85 DMARQ I Pull-low GPIO10: For embedded or CPU mode EROMA3: Address3 when ROM mode GPIO9: For embedded or CPU mode EROMA2: Address2 when ROM mode IDE request IDEDD [0:3] B Tri-state IDE data bus 0~3 90 DGND2 P Power Digital ground 91 DVCC2 P Power Digital VCC IDEDD [4:7] B Tri-state IDE data bus 4~7 96 GPIO1 B Pull-high GPIO1 97 GPIO2 B Pull-high GPIO2 98 GPIO3 B Pull-high GPIO3 99 GPIO4 B Pull-low GPIO4 100 GPIO7 B Pull-low GPIO 7 (*) 86~89 92~95 B Pull-low external external external external (*) When operating in default mode: GPIO7 is the IDE reset input, GPIO8 is used to control the power input of IDE device. ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 14 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 5. Functional Description 5.1 Transmit Operation 5.1.1 Transmit State Diagram !TXVLD HRST# Reset !HRST# TX Wait !TXRDY TXVLD EOP not done TX Hold Reg Empty Send SYNC TX Data Load !TXVLD Send EOP TXRDY TX Hold Reg Full !TXRDY TX Hold Reg Empty TX Data Wait !TXRDY TX Hold Reg Full Transmit must be asserted to enable any transmissions. The SIE asserts TXVLD to begin a transmission. The SIE negates TXVLD to end a transmission. After the SIE asserts TXVLD it can assume that the transmission has started when it detects TXRDY asserted. The SIE assumes that the UTM has consumed a data byte if TXRDY and TXVLD are asserted. The SIE must have valid packet information (PID) asserted on the Data bus coincident with the assertion of TXVLD. Depending on the UTM implementation, TXRDY may be asserted by the Transmit State Machine as soon as one CLK after the assertion of TXVLD. TXVLD and TXRDY are sampled on the rising edge of CLKOUT. The Transmit State Machine does not automatically generate Packet ID’s (PIDs) or ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 15 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller CRC. When transmitting, the SIE is always expected to present a PID as the first byte of the data stream and if appropriate, CRC as the last bytes of the data stream. The SIE must use LINEST0/1 to verify a Bus Idle condition before asserting TXVLD in the TX Wait state. 5.1.2 Transmit Timing for Data Packet CLKOUT TXVLD Data PID Data Data Data Data CRC CRC TXRDY DP/DM SYNC PID Data Data Data Data CRC CRC EOP C C P The SIE negates TXVLD to complete a packet. Once negated, the Transmit State Machine will never reassert TXRDY until after the EOP has been loaded into the Transmit Shift Register. Note that the UTM Transmit State Machine can be ready to start another package immediately, however the SIE must confirm to the minimum inter-packet delays identified in the USB 2.0 Specification. ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 16 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 5.2 Receive Operation 5.2.1 Receive State Diagram !SYNC !HRST# Reset !RXACTV !RXVLD HRST# SYNC Detected EOP Detected Data Trip SYNC RXACTV Terminate !RXACTV RX Wait Strip EOP !RXACTV !RXVLD Rx Data RXVLD Data !Data Data SYNC RX Data Wait !RXVLD Receive Error Abort 1 !RXACTV !RXVLD !RXERR Abort 2 !RXVLD !RXERR Error RXERR !Data Idle state !Idle state RXACTV and RXVLD are sampled on the rising edge of CLKOUT. In the RX Wait state the receiver is always looking for SYNC. The Macrocell asserts RXACTV when SYNC is detected (Strip SYNC state). The Macrocell negates RXACTV when an EOP is detected (Strip EOP state). When RXACTV is asserted, RXVLD will be asserted if the RX Holding Register is full. RXVLD will be negated if the RX Holding Register was not loaded during the previous byte time. This will occur if 8 stuffed bits have been accumulated. The SIE must be ready to consume a data byte if RXACTV and RXVLD are asserted (RX Data state). In FS mode, if a bit stuff error is detected then the Receive State Machine will negate RXACTV and RXVLD, and return to the RXWait state. ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 17 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 5.2.2 Receive Timing for Data Packet (with CRC-16) CLKOUT RXACTV Data PID Data Data Data Data CRC CRC Data Data Data Data CRC CRC EOP RXVLD RXERR DP/DM SYNC PID Note that the USB 2.0 transceiver does not decode Packet ID’s (PIDs). They are passed to the SIE for decoding. This timing example is in HS mode. When a HS/FS UTM is in FS mode there are approximately 40 clock cycles every byte time. The Receive State Machine assumes that the SIE captures the data on the data bus if RXACTV and RXVLD are asserted. In FS mode, RXVLD will only be asserted for one clock per byte time. Note that the receive and transmit sections of the transceiver operate independently. The receiver will receive any packets on the USB. The transceiver does not identify whether the packet that it is receiving from the upstream or the downstream port. The SIE must ignore receive data while it is transmitting. ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 18 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Symbol Min Max Unit DC supply voltage -0.3 +3.6 V DC input voltage -0.3 VCC + 0.3 V VI/O DC input voltage range for I/O -0.3 VCC + 0.3 V VAI/O DC input voltage for USB D+/D- pins -0.3 VCC + 0.3 V VI/OZ DC voltage applied to outputs in High Z state -0.3 VCC + 0.3 V VESD Static discharge voltage 4000 VCC VI TA Description Ambient Temperature V 0 o 100 C 6.2 Recommended Operating Conditions Item Value Supply Voltage +3.3V to + 3.6V Ground Voltage 0V Fosc 12 MHz ± 100 ppm Operating Temperature 0 oC ~ 70 oC 6.3 DC Characteristics (Digital Pins) Symbol Description Min Typ Max Unit PD Power Dissipation VDD Power Supply Voltage 3 IO DC output sink current excluding D+/ D-/ VCC/ GND 8 VIL LOW level input voltage VIH HIGH level input voltage 2.0 VTLH LOW to HIGH threshold voltage 1.3 1.43 1.56 V VTHL HIGH to LOW threshold voltage 1.3 1.43 1.56 V ©2001-2002 Genesys Logic Inc.—All rights reserved. mA 3.3 3.6 V mA 0.9 V V Page 19 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller Symbol Description Min Typ Max Unit - 0 - V 0.4 V VHYS Hysteresis voltage VOL LOW level output voltage when IOL=8mA VOH HIGH level output voltage when IOH=8mA IOLK Leakage current for pads with internal pull up or pull down resistor RDN Pad internal pull down resister 79K RUP Pad internal pull up resister 78K 2.4 V 46 µA 105K 152K Ohms 104K 146K Ohms 6.4 DC Characteristics (D+/D-) Symbol Description VOL D+/D- static output LOW (RL of 1.5K to 3.6V ) VOH D+/D- static output HIGH (RL of 15K to GND ) 2.8 VDI Differential input sensitivity 0.2 VCM Differential common mode range 0.8 VSE Single-ended receiver threshold 0.2 CIN Transceiver capacitance ILO Hi-Z state data line leakage Driver output resistance ZDRV Min Typ Max Unit 0.3 V 3.6 V V 2.5 V V 20 pF -10 +10 µA 28 43 Ohms 6.5 Switching Characteristics Symbol Description Min Typ Max Unit 11.97 12 12.03 MHz FX1 X1 crystal frequency TCYC X1 cycle time TX1L X1 clock LOW time 0.45Tcyc ns TX1H X1 clock HIGH time 0.45Tcyc ns Tr30pf Output pad rise time from 10% to 90% swing with 30pF loading ns Tf30pf Output pad fall time from 10% to 90% swing with 30pF loading ns ©2001-2002 Genesys Logic Inc.—All rights reserved. 83.3 ns Page 20 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller Symbol Description Tr50pf Output pad rise time from 10% to 90% swing with 50pF loading ns Tf50pf Output pad fall time from 10% to 90% swing with 50pF loading ns TrUSB D+/D- rise time with 50pF loading 4 20 ns TfUSB D+/D- fall time with 50pF loading 4 20 ns ©2001-2002 Genesys Logic Inc.—All rights reserved. Min Typ Max Unit Page 21 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 7. Package Dimension 7.1 48-pin LQFP SYMBOL MIN MAX A 1.6 A1 0.05 0.15 A2 1.35 1.45 C1 0.09 0.16 D 9.00BSC D1 7.00BSC E 9.00BSC E1 7.00BSC e 0.5BSC b 0.17 0.27 L 0.45 0.75 L1 ©2001-2002 Genesys Logic Inc.—All rights reserved. 1 REF Page 22 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 7.2 100-pin LQFP ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 23 of 24 GL813 - USB2.0 CompactFlash Card Reader Controller 8. Revision History Version Description Date 1.0 First draft 2002/03/20 1.1 Correction and supplement of Electrical Characteristics data 2002/04/03 1.2 Add 100-pin LQFP package related data 2002/04/12 ©2001-2002 Genesys Logic Inc.—All rights reserved. Page 24 of 24