TI TPS650231RSBT

TPS650231
www.ti.com
SLVSAE3 – AUGUST 2010
POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
Check for Samples: TPS650231
FEATURES
1
•
23
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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1.7 A, 90% Efficient Step-Down Converter for
Processor Core (VDCDC1)
1.2 A, Up to 95% Efficient Step-Down
Converter for System Voltage (VDCDC2)
0.8 A, 92% Efficient Step-Down Converter for
Memory Voltage (VDCDC3)
30 mA LDO/Switch for Real Time Clock (VRTC)
2 × 200 mA General-Purpose LDO
Dynamic Voltage Management for Processor
Core
Preselectable LDO Voltage Using Two Digital
Input Pins
Externally Adjustable Reset Delay Time
Battery Backup Functionality
Separate Enable Pins for Inductive Converters
I2C™ Compatible Serial Interface
85-mA Quiescent Current
Low Ripple PFM Mode
Thermal Shutdown Protection
40 Pin, 5 mm × 5 mm QFN /RSB) Package or
49 Ball 3 mm x 3 mm WCSP (YFF) package
APPLICATIONS
•
•
•
Smart phones
Netbooks / MIDs
Portable Media Players
DESCRIPTION
The TPS650231 is an integrated Power Management
IC for applications powered by one Li-Ion or
Li-Polymer cell, and which require multiple power
rails. The TPS650231 provides three highly efficient,
step-down converters targeted at providing the core
voltage, peripheral, I/O and memory rails in a
processor based system. The core converter allows
for on-the-fly voltage changes via serial interface,
allowing the system to implement dynamic power
savings. All three step-down converters enter a
low-power mode at light load for maximum efficiency
across the widest possible range of load currents.
The TPS650231 also integrates two general-purpose
200 mA LDO voltage regulators, which are enabled
with an external input pin. Each LDO operates with
an input voltage range between 1.5 V and 6.5 V,
allowing them to be supplied from one of the
step-down converters or directly from the battery. The
default output voltage of the LDOs can be digitally set
to 4 different voltage combinations using the
DEFLDO1 and DEFLDO2 pins. The serial interface
can be used for dynamic voltage scaling, masking
interrupts, or for dis/enabling and setting the LDO
output voltages. The interface is compatible with the
Fast/Standard mode I2C specification, allowing
transfers at up to 400 kHz. The TPS650231 is
available in a 40-pin (RSB) QFN package or in a 49
ball 3mm x 3mm WCSP (YFF) package, and
operates over a free-air temperature of –40°C to
85°C.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS650231
SLVSAE3 – AUGUST 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PACKAGE
PACKAGE SIZE
PART NUMBER (2)
–40°C to 85°C
40 pin QFN (RSB)
see package drawings
TPS650231RSB
–40°C to 85°C
49 ball WCSP (YFF)
see package drawings
E = 3.082mm ± 30µm
D = 3.066mm ± 30µm
TPS650231YFF
TA
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The RSB and YFF packages are available in tape and reel. Add the R suffix (TPS650231RSBR, TPS650231YFFR) to order quantities of
3000 parts per reel. Add the T suffix (TPS650231RSBT, TPS650231YFFT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
VI
Input voltage range on all pins except AGND and PGND pins with respect to AGND
7
V
2500
mA
Peak current at all other pins
1000
mA
Operating free-air temperature
TJ
Junction temperature
Tstg
Storage temperature
–0.3
UNIT
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3,
PGND3
TA
(1)
MAX
–40
–65
85
°C
125
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
THERMAL INFORMATION
TPS650231
THERMAL METRIC (1)
RSB
YFF
40 PINS
49 BALLS
qJA
Junction-to-ambient thermal resistance
32.7
40
qJCtop
Junction-to-case (top) thermal resistance
15.3
10
qJB
Junction-to-board thermal resistance
13.6
15
yJT
Junction-to-top characterization parameter
0.1
0.1
yJB
Junction-to-board characterization parameter
5.4
14
qJCbot
Junction-to-case (bottom) thermal resistance
1.1
n/a
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Input voltage range step-down converters
(VINDCDC1, VINDCDC2, VINDCDC3)
2.5
6
Output voltage range for VDCDC1 step-down converter (1)
0.6
VINDCDC1
Output voltage range for VDCDC2 step-down converter (1)
0.6
VINDCDC2
Output voltage range for VDCDC3 step-down converter (1)
0.6
VINDCDC3
VI
Input voltage range for LDOs (VINLDO)
1.5
6.5
VO
Output voltage range for LDOs (VLDO1, VLDO2)
1
VINLDO1-2
IO(DCDC1)
Output current at L1
VCC
VO
1700
Inductor at L1 (2)
1.5
CI(DCDC1)
Input capacitor at VINDCDC1
(2)
10
CO(DCDC1)
Output capacitor at VDCDC1
(2)
10
IO(DCDC2)
Output current at L2
Inductor at L2
2.2
1.5
(2)
10
CO(DCDC2)
Output capacitor at VDCDC2
(2)
10
22
IO(DCDC3)
Output current at L3
(2)
1.5
2.2
Input capacitor at VINDCDC3 (2)
10
(2)
10
Output capacitor at VDCDC3
CI(VCC)
Input capacitor at VCC
CI(VINLDO)
Input capacitor at VINLDO
CO(VLDO1-2)
Output capacitor at VLDO1, VLDO2
IO(VLDO1-2)
Output current at VLDO1, VLDO2
CO(VRTC)
Output capacitor at VRTC
TA
Operating ambient temperature
–40
TJ
Operating junction temperature
–40
(2)
(2)
(2)
(1)
(2)
(3)
mF
mA
mH
mF
22
mF
1
mF
1
mF
2.2
mF
4.7
Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering (3)
mA
mF
200
(2)
V
mA
mH
800
CO(DCDC3)
V
mF
2.2
Input capacitor at VINDCDC2
CI(DCDC3)
V
mF
22
CI(DCDC2)
Inductor at L3
V
mH
1200
(2)
UNIT
mA
mF
1
85
°C
125
°C
10
Ω
When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1
See Applications Information section for more information.
Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted
accordingly.
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ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONTROL SIGNALS : SCLK, SDAT (input)
VIH
High level input voltage for the SCLK pin
Rpullup at SCLK = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5V to 5.25V
1.4
VCC
V
VIH
High level input voltage for the SDAT pin
Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5V to 5.25V
1.69
VCC
V
VIH
High level input voltage for the SDAT pin
Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5V to 4.5V
1.55
VCC
V
VIL
Low level input voltage
Rpullup at SCLK and SDAT = 4.7 kΩ, pulled
to VRTC
0
0.35
V
IH
Input bias current
0.1
mA
0.01
CONTROL SIGNALS : HOT_RESET , DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
VIH
High-level input voltage
1.3
VCC
V
VIL
Low-level input voltage
0
0.4
V
IIB
Input bias current
tglitch
Deglitch time at HOT_RESET
25
0.01
0.1
mA
30
35
ms
6
V
CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output)
VOH
High-level output voltage
VOL
Low-level output voltage
IIL = 5 mA
Duration of low pulse at RESPWRON
External capacitor 1 nF
Resetpwron threshold
VRTC falling
–3%
Resetpwron threshold
VRTC rising
–3%
leakage current
output inactive high
ILK
4
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0
0.3
100
V
ms
2.4
3%
V
2.52
3%
V
0.001
0.1
mA
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) : TPS650231
TPS650231
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SLVSAE3 – AUGUST 2010
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3,
VINDCDC13 (for TPS650231YFF)
I(q)
II
I(q)
Operating quiescent
current, PFM
Current into VCC; PWM
Quiescent current
All 3 DCDC converters enabled,
zero load, and no switching, LDOs
enabled
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
85
100
All 3 DCDC converters enabled,
zero load, and no switching, LDOs
off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
78
90
DCDC1 and DCDC2 converters
enabled, zero load, and no
switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
57
70
DCDC1 converter enabled, zero
load, and no switching, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
43
55
All 3 DCDC converters enabled
and running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
2
3
DCDC1 and DCDC2 converters
enabled and running in PWM,
LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
1.5
2.5
DCDC1 converter enabled and
running in PWM, LDOs off
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
0.85
2
VCC = 3.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
23
33
mA
VCC = 2.6 V, VBACKUP = 3 V;
V(VSYSIN) = 0 V
3.5
5
mA
43
mA
All converters disabled, LDOs off
mA
VCC = 3.6 V, VBACKUP = 0 V;
V(VSYSIN) = 0 V
I(SD)
mA
Shutdown supply current
into VINDCDC1; for
TPS650231RSB
DCDC1_EN = GND
0.1
1
mA
Shutdown supply current
into VINDCDC2; for
TPS650231RSB
DCDC2_EN = GND
0.1
1
mA
Shutdown supply current
into VINDCDC3; for
TPS650231RSB
DCDC3_EN = GND
0.1
1
mA
Shutdown supply current
into VINDCDC13; for
TPS650231YFF
DCDC1_EN = DCDC3_EN =
GND
0.2
2
mA
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ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C,
typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20
33
mA
3
mA
SUPPLY PINS: VBACKUP, VSYSIN, VRTC
I(q)
Operating quiescent current
VBACKUP = 3 V, VSYSIN = 0 V;
VCC = 2.6 V, current into VBACKUP
I(SD)
Operating quiescent current
VBACKUP < V_VBACKUP, current into
VBACKUP
2
VRTC LDO output voltage
VSYSIN = VBACKUP = 0 V, IO = 0 mA
3
Output current for VRTC
VSYSIN < 2.57 V and VBACKUP < 2.57 V
30
mA
VRTC short-circuit current limit
VRTC = GND; VSYSIN = VBACKUP = 0 V
100
mA
Maximum output current at VRTC for
RESPWRON = 1
VRTC > 2.6 V, VCC = 3 V;
VSYSIN = VBACKUP = 0 V
Output voltage accuracy for VRTC
VSYSIN = VBACKUP = 0 V; IO = 0 mA
–1%
1%
Line regulation for VRTC
VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA
–1%
1%
Load regulation VRTC
IO = 1 mA to 30 mA;
VSYSIN = VBACKUP = 0 V
–3%
1%
Regulation time for VRTC
Load change from 10% to 90%
Input leakage current at VSYSIN
VSYSIN < V_VSYSIN
IO
VO
Ilkg
V
30
mA
10
ms
2
mA
rDS(on) of VSYSIN switch
12.5
Ω
rDS(on) of VBACKUP switch
12.5
Ω
Input voltage range at VBACKUP
2.73
3.75
V
Input voltage range at VSYSIN
2.73
3.75
V
VSYSIN threshold
VSYSIN falling
–3%
2.55
3%
V
VSYSIN threshold
VSYSIN rising
–3%
2.65
3%
V
VBACKUP threshold
VBACKUP falling
–3%
2.55
3%
V
VBACKUP threshold
VBACKUP falling
–3%
2.65
3%
V
SUPPLY PIN: VINLDO
I(q)
Operating quiescent current
Current per LDO into VINLDO
20
33
mA
I(SD)
Shutdown current
Total current for both LDOs into VINLDO,
VLDO = 0 V
0.1
1
mA
6
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SLVSAE3 – AUGUST 2010
ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC1 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC1
IO
Maximum output current
rDS(on)
P-channel MOSFET on-resistance
VINDCDC1 (VINDCDC13) = V(GS) = 3.6 V
Ilkg
P-channel leakage current
VINDCDC1 (VINDCDC13) = 6 V
rDS(on)
N-channel MOSFET on-resistance
VINDCDC1 (VINDCDC13) = V(GS) = 3.6 V
Ilkg
N-channel leakage current
V(DS) = 6 V
Forward current limit (P-channel and
N-channel)
2.5 V < V(VINDCDC1) < 6 V
fS
2.5
1700
Oscillator frequency
Fixed output voltage
FPWMDCDC1=0
6
mA
125
261
2
mA
130
260
mΩ
7
10
mA
1.94
2.19
2.44
A
1.95
2.25
2.55
MHz
VINDCDC1 (VINDCDC13) = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.7 A
–2%
2%
VINDCDC1 (VINDCDC13) = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.7 A
–1%
1%
Adjustable output voltage with resistor
divider at DEFDCDC1; FPWMDCDC1=0
VINDCDC1 (VINDCDC13) = VDCDC1 + 0.5 V
(min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.7 A
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC1; FPWMDCDC1=1
VINDCDC1 (VINDCDC13) = VDCDC1 + 0.5 V
(min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.7 A
–1%
1%
Line Regulation
VINDCDC1 (VINDCDC13) = VDCDC1 + 0.3 V
(min. 2.5 V) to 6 V; IO = 10 mA
Fixed output voltage
FPWMDCDC1=1
All VDCDC1
V
0
mΩ
%/V
Load Regulation
IO = 10 mA to 1700 mA
tStart
Start-up time
Time from active EN to start switching
145
175
200
ms
tRamp
VOUT ramp-up time
Time to ramp from 5% to 95% of VOUT
400
750
1000
ms
Internal resistance from L1 to GND
VDCDC1 discharge resistance
0.25
%/A
1
DCDC1 discharge = 1
300
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MΩ
Ω
7
TPS650231
SLVSAE3 – AUGUST 2010
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ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C,
typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC2 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC2
2.5
6
VDCDC2 = 1.2V
1200
IO
Maximum output current
VINDCDC2 = 3.7 V;
3.3 V - 1% ≤ VDCDC2 ≤ 3.3V + 1%
1000
rDS(on)
P-channel MOSFET on-resistance
VINDCDC2 = V(GS) = 3.6 V
Ilkg
P-channel leakage current
VINDCDC2 = 6 V
rDS(on)
N-channel MOSFET on-resistance
VINDCDC2 = V(GS) = 3.6 V
Ilkg
N-channel leakage current
V(DS) = 6 V
ILIMF
Forward current limit (P-channel and
N-channel)
2.5 V < VINDCDC2 < 6 V
fS
Oscillator frequency
VDCDC2
Adjustable output voltage with resistor
divider at DEFDCDC2; FPWMDCDC2=0
VINDCDC2 = VDCDC2 + 0.4 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.2 A
–2%
2%
VDCDC2
Adjustable output voltage with resistor
divider at DEFDCDC2; FPWMDCDC2=1
VINDCDC2 = VDCDC2 + 0.4 V (min 2.5 V)
to 6 V; 0 mA ≤ IO ≤ 1.2 A
–1%
1%
Line Regulation
VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V)
to 6 V; IO = 10 mA
mA
140
300
2
mA
150
297
mΩ
7
10
mA
1.74
1.94
2.12
A
1.95
2.25
2.55
MHz
0
Load Regulation
IO = 10 mA to 1.2 A
Start-up time
Time from active EN to start switching
145
175
200
tRamp
VOUT ramp-up time
Time to ramp from 5% to 95% of VOUT
400
750
1000
VDCDC2 discharge resistance
8
0.25
1
DCDC2 discharge =1
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300
mΩ
%/V
tStart
Internal resistance from L2 to GND
V
%/A
µs
ms
MΩ
Ω
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ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C,
typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDCDC3 STEP-DOWN CONVERTER
VI
Input voltage range, VINDCDC3
DEFDCDC3 = GND
800
IO
Maximum output current
VINDCDC3 (VINDCDC13) = 3.6 V;
3.3V - 1% ≤ VDCDC3 ≤ 3.3V + 1%
525
rDS(on)
P-channel MOSFET on-resistance
VINDCDC3 (VINDCDC13) = V(GS) = 3.6 V
Ilkg
P-channel leakage current
VINDCDC3 (VINDCDC13) = 6 V
0.1
2
mA
rDS(on)
N-channel MOSFET on-resistance
VINDCDC3 (VINDCDC13) = V(GS) = 3.6 V
220
503
mΩ
Ilkg
N-channel leakage current
V(DS) = 6 V
7
10
mA
Forward current limit (P-channel and
N-channel)
2.5 V < VINDCDC3 (VINDCDC13) < 6 V
1.28
1.49
1.69
A
1.95
2.25
2.55
MHz
fS
2.5
6
mA
310
Oscillator frequency
698
VINDCDC3 (VINDCDC13) = 2.5 V to 6 V;
VDCDC3 = 1.8V
0 mA ≤ IO ≤ 0.8 A
–2%
2%
VDCDC3 = 3.3V
VINDCDC3 (VINDCDC13) = 3.6 V to 6 V;
0 mA ≤ IO ≤ 0.8 A
–1%
1%
VDCDC3 = 1.8V
VINDCDC3 (VINDCDC13) = 2.5 V to 6 V;
0 mA ≤ IO ≤ 0.8 A
–2%
2%
VDCDC3 = 3.3V
VINDCDC3 (VINDCDC13) = 3.6 V to 6 V;
0 mA ≤ IO ≤ 0.8 A
–1%
1%
Adjustable output voltage with resistor
divider at DEFDCDC3 FPWMDCDC3=0
VINDCDC3 (VINDCDC13) = VDCDC3 + 0.5 V
(min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 800 mA
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC3; FPWMDCDC3=1
VINDCDC3 (VINDCDC13) = VDCDC3 + 0.5 V
(min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 800 mA
–1%
1%
Line Regulation
VINDCDC3 (VINDCDC13) = VDCDC3 + 0.3 V
(min. 2.5 V) to 6 V; IO = 10 mA
Load Regulation
IO = 10 mA to 800 mA
tStart
Start-up time
Time from active EN to start switching
145
175
200
tRamp
VOUT ramp-up time
Time to ramp from 5% to 95% of VOUT
400
750
1000
Fixed output voltage
FPWMDCDC3=0
Fixed output voltage
FPWMDCDC3=1
Internal resistance from L3 to GND
VDCDC3 discharge resistance
%/V
0.25
%/A
300
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mΩ
0
1
DCDC3 discharge =1
V
µs
ms
MΩ
Ω
9
TPS650231
SLVSAE3 – AUGUST 2010
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ELECTRICAL CHARACTERISTICS
VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C,
typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1 and VLDO2 LOW DROPOUT REGULATORS
VI
Input voltage range for LDO1, 2
1.5
6.5
V
VO(LD01)
VO(LDO2)
LDO1 output voltage range
1
3.15
V
LDO2 output voltage range
1.05
3.3
V
VI = 1.8 V, VO = 1.3 V
IO
Maximum output current for LDO1, LDO2
I(SC)
LDO1 and LDO2 short circuit current limit V(LDO1) = GND, V(LDO2) = GND
200
VI = 1.5 V, VO = 1.3 V
400
IO = 50 mA, VINLDO = 1.8 V
Minimum voltage drop at LDO1, LDO2
mA
120
IO = 50 mA, VINLDO = 1.5 V
65
IO = 200 mA, VINLDO = 1.8 V
Output voltage accuracy for LDO1, LDO2 IO = 10 mA
mA
120
150
mV
300
–2%
1%
Line regulation for LDO1, LDO2
VINLDO1, 2 = VLDO1,2 + 0.5 V
(min. 2.5 V) to 6.5 V, IO = 10 mA
–1%
1%
Load regulation for LDO1, LDO2
IO = 0 mA to 50 mA
–1%
Regulation time for LDO1, LDO2
Load change from 10% to 90%
1%
10
ms
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
High-level input voltage
1.3
VCC
VIL
Low-level input voltage
0
0.1
V
0.05
mA
Input bias current
0.001
V
THERMAL SHUTDOWN
T(SD)
Thermal shutdown
Increasing junction temperature
160
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO
Internal UVLO
V(UVLO_HYST)
Internal UVLO comparator hysteresis
VCC falling
–2%
2.35
2%
120
V
mV
VOLTAGE DETECTOR COMPARATOR INPUTS PWRFAIL_SNS, LOWBAT_SNS
Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS)
LOWBAT_SNS for TPS650231RSB only
Falling threshold
Hysteresis
Propagation delay
ILK
–1%
1
1%
V
40
50
60
mV
25-mV overdrive
Input leakage current
10
ms
0.001
0.1
mA
POWER GOOD
V(PGOODF)
VDCDC1, VDCDC2, VDCDC3,
VLDO1, VLDO2, decreasing
–12%
–10%
–8%
V(PGOODR)
VDCDC1, VDCDC2, VDCDC3,
VLDO1, VLDO2, increasing
–7%
–5%
–3%
10
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PWRFAIL
DEFDCDC2
PGND2
VDCDC2
L2
VINDCDC2
PWRFAIL_SNS
VCC
LOWBAT_SNS
AGND1
PIN ASSIGNMENT FOR TPS650231RSB
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
DEFDCDC3
1
30
SCLK
VDCDC3
2
29
SDAT
3
28
INT
4
27
RESPWRON
5
26
TRESPWRON
VINDCDC1
6
25
DCDC1_EN
L1
7
24
DCDC2_EN
PGND1
8
23
DCDC3_EN
9
22
LDO_EN
10
21
LOWBAT
PGND3
L3
VINDCDC3
VDCDC1
DEFDCDC1
VLDO1
VINLDO
VLDO2
VRTC
AGND2
VBACKUP
VSYSIN
DEFLDO1
DEFLDO2
HOT_RESET
11 12 13 14 15 16 17 18 19 20
PIN FUNCTIONS FOR TPS650231RSB
PIN
NAME
NO.
I/O
DESCRIPTION
SWITCHING REGULATOR SECTION
AGND1
40
Analog ground. All analog ground pins are connected internally on the chip.
AGND2
17
Analog ground. All analog ground pins are connected internally on the chip.
PowerPAD™
–
Connect the power pad to analog ground.
VINDCDC1
6
L1
7
VDCDC1
9
PGND1
8
VINDCDC2
36
L2
35
VDCDC2
33
PGND2
34
VINDCDC3
5
L3
4
VDCDC3
2
PGND3
3
VCC
37
I
Input voltage for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage
supply as VINDCDC2, VINDCDC3, and VCC.
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
I
VDCDC1 feedback voltage sense input. Connect directly to VDCDC1
Power ground for VDCDC1 converter.
I
Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage
supply as VINDCDC1, VINDCDC3, and VCC.
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
I
VDCDC2 feedback voltage sense input. Connect directly to VDCDC2
Power ground for VDCDC2 converter
I
Input voltage for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage
supply as VINDCDC1, VINDCDC2, and VCC.
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
I
VDCDC3 feedback voltage sense input. Connect directly to VDCDC3
Power ground for VDCDC3 converter.
I
Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters. VCC
must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. VCC also
supplies serial interface block.
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PIN FUNCTIONS FOR TPS650231RSB (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
DEFDCDC1
10
I
Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V; DEFDCDC1 can also be connected
to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a
range from 0.6 V to VINDCDC1 V.
DEFDCDC2
32
I
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC2 can also be connected
to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2 converter is set in a
range from 0.6 V to VINDCDC2 V.
DEFDCDC3
1
I
Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC3 can also be connected
to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a
range from 0.6 V to VINDCDC3 V.
DCDC1_EN
25
I
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN
24
I
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN
23
I
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
LDO REGULATOR SECTION
VINLDO
19
I
Input voltage for LDO1 and LDO2
VLDO1
20
O
Output voltage of LDO1
VLDO2
18
O
Output voltage of LDO2
LDO_EN
22
I
Enable input for LDO1 and LDO2. A Logic high enables the LDOs, a logic low disables the LDOs.
VBACKUP
15
I
Connect the backup battery to this input pin.
VRTC
16
O
Output voltage of the LDO/switch for the real time clock.
VSYSIN
14
I
Input of system voltage for VRTC switch.
DEFLD01
12
I
Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.
DEFLD02
13
I
Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.
CONTROL AND I2C SECTION
HOT_RESET
11
I
Push button input that reboots or wakes up the processor via RESPWRON output pin.
TRESPWRON
RESPWRON
26
I
Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms.
27
O
Open drain system reset output.
PWRFAIL
31
O
Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
LOW_BAT
21
O
Open drain output of LOW_BAT comparator.
INT
28
O
Open drain output
SCLK
30
I
Serial interface clock line
SDAT
29
I/O
PWRFAIL_SNS
38
I
Input for the comparator driving the PWRFAIL output.
LOWBAT_SNS
39
I
Input for the comparator driving the LOW_BAT output.
12
Serial interface data/address
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SLVSAE3 – AUGUST 2010
FUNCTIONAL BLOCK DIAGRAM
VCC
VSYSIN
VBACKUP
VRTC
TPS650231RSB
BBAT
SWITCH
Thermal
Shutdown
VINDCDC1
L1
DCDC1
Buck Converter
1700 mA
SCLK
SDAT
VDCDC1
DEFDCDC1
PGND1
Serial Interface
VINDCDC2
DCDC1_EN
L2
DCDC2_EN
DCDC2
Buck Converter
1200 mA
DCDC3_EN
LDO_EN
CONTROL
VDCDC2
DEFDCDC2
PGND2
HOT_RESET
Dynamic
Voltage
Management
RESPWRON
INT
VINDCDC3
L3
LOWBAT_SNS
PWRFAIL_SNS
LOW_BATT
PWRFAIL
DCDC3
Buck Converter
1000 mA
UVLO
VREF
OSC
VDCDC3
DEFDCDC3
PGND3
TRESPWRON
LDO1
200 mA
DEFLDO1
DEFLDO2
VLDO1
VINLDO
LDO2
200 mA
VLDO2
AGND1
AGND2
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PIN ASSIGNMENT FOR TPS650231YFF
(BOTTOM VIEW)
VLDO1
VINLDO
VLDO2
VBACKUP
DEFLDO2
DEFLDO1
VDCDC1
A7
LDO_EN
DCDC2_EN
AGND
VSYSIN
PGND1
PGND1
PGND1
A6
DCDC3_EN
DCDC1_EN
VRTC
DEFDCDC1
L1
L1
L1
A5
Trespwron
SDAT
VDCDC2
Vcc
VINDCDC13
VINDCDC13
VINDCDC13
A4
DEFDCDC2
PGND2
L2
VINDCDC2
VDCDC3
L3
VINDCDC13
A3
SCLK
PGND2
L2
PWRFAIL
_SNS
VINDCDC2
PGND3
L3
A2
/PWRFAIL
PGND2
G1
L2
F1
VINDCDC2
E1
DEFDCDC3
D1
AGND
C1
PGND3
B1
A1
PIN FUNCTIONS FOR TPS650231YFF
PIN
NAME
NO.
I/O
DESCRIPTION
SWITCHING REGULATOR SECTION
AGND
B1, E6
Analog ground. All analog ground pins are connected internally on the chip.
VINDCDC13
A3,
A4,
B4,
C4
I
Input voltage for VDCDC1 and VDCDC3 step-down converter. This must be connected to the same
voltage supply as VINDCDC2 and VCC.
L1
A5,
B5,
C5
O
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
VDCDC1
A7
I
VDCDC1 feedback voltage sense input. Connect directly to VDCDC1
PGND1
A6,
B6,
C6
VINDCDC2
D1,
D2,
D3
I
Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage
supply as VINDCDC13 and VCC.
E1,
E2, E3
O
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
E4
I
VDCDC2 feedback voltage sense input. Connect directly to VDCDC2
L2
VDCDC2
Power ground for VDCDC1 converter.
PGND2
F1,
F2, F3
L3
A2, B3
O
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
C3
I
VDCDC3 feedback voltage sense input. Connect directly to VDCDC3
VDCDC3
PGND3
14
A1, B2
Power ground for VDCDC2 converter
Power ground for VDCDC3 converter.
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SLVSAE3 – AUGUST 2010
PIN FUNCTIONS FOR TPS650231YFF (continued)
PIN
I/O
DESCRIPTION
D4
I
Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters. VCC
must be connected to the same voltage supply as VINDCDC13 and VINDCDC2. VCC also supplies the
serial interface block.
DEFDCDC1
D5
I
Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V; DEFDCDC1 can also be connected
to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a
range from 0.6 V to VINDCDC1 V.
DEFDCDC2
G3
I
This pin needs to be connected to a resistor divider between VDCDC2 and GND. The output voltage of
the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V.
DEFDCDC3
C1
I
Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC3 can also be connected
to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a
range from 0.6 V to VINDCDC3 V.
DCDC1_EN
F5
I
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN
F6
I
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN
G5
I
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
NAME
NO.
VCC
LDO REGULATOR SECTION
VINLDO
F7
I
Input voltage for LDO1 and LDO2
VLDO1
G7
O
Output voltage of LDO1
VLDO2
E7
O
Output voltage of LDO2
LDO_EN
G6
I
Enable input for LDO1 and LDO2. A Logic high enables the LDOs, a logic low disables the LDOs.
VBACKUP
D7
I
Connect the backup battery to this input pin.
VRTC
E5
O
Output voltage of the LDO/switch for the real time clock.
VSYSIN
D6
I
Input of system voltage for VRTC switch.
DEFLD01
B7
I
Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.
DEFLD02
C7
I
Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.
2
CONTROL AND I C SECTION
TRESPWRON
G4
I
Connect a 1nF capacitor from this pin to GND.
PWRFAIL
G1
O
Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
SCLK
G2
I
Serial interface clock line
SDAT
F4
I/O
PWRFAIL_SNS
C2
I
Serial interface data/address
Input for the comparator driving the PWRFAIL output.
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FUNCTIONAL BLOCK DIAGRAM FOR TPS650231YFF
VSYSIN
THERMAL
SHUTDOWN
VCC
VBACKUP
DCDC3
STEP -DOWN
CONVERTER
BBAT
SWITCH
VRTC
PGND3
VINDCDC13
DCDC1
SCLK
SDAT
L3
VDCDC3
DEFDCDC3
STEP-DOWN
CONVERTER
Serial Interface
L1
VDCDC1
DEFDCDC1
PGND1
VINDCDC2
DCDC1_EN
DCDC2_EN
DCDC3_EN
LDO _ EN
DCDC2
CONTROL
STEP-DOWN
CONVERTER
Dynamic
Voltage
Scaling
PWRFAIL_ SNS
/PWRFAlL
L2
VDCDC2
DEFDCDC2
PGND2
VLDO1
UVLO
VREF
OSC
VLDO1
200 mA LDO
TRESPWRON
AGND
VINLDO
DEFLDO1
VLDO2
DEFLDO2
VLDO2
200 mA LDO
16
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TYPICAL CHARACTERISTICS
Graphs were taken using the EVM with the following inductor/output capacitor combinations:
CONVERTER
INDUCTOR
OUTPUT CAPACITOR
OUTPUT CAPACITOR VALUE
VDCDC1
LQH32PN1R5
JMK107BJ106
2 × 10 mF
VDCDC2
LQH32PN2R2
JMK107BJ106
2 × 10 mF
VDCDC3
LQH32PN2R2
JMK107BJ106
2 × 10 mF
Table 1. Table of Graphs
FIGURE
h
Efficiency
vs Output current
1, 2, 3, 4, 5, 6
Output voltage
vs Output current at 85°C
7, 8
Line transient response
9, 10, 11
Load transient response
12, 13, 14
VDCDC2 PFM operation
15
VDCDC2 low ripple PFM operation
16
VDCDC2 PWM operation
17
Startup VDCDC1, VDCDC2 and VDCDC3
18
Startup LDO1 and LDO2
19
Line transient response
20, 21, 22
Load transient response
23, 24, 25
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
DCDC1: EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
VI = 2.5 V
90
VI = 3 V
80
80
VI = 4.2 V
60
VI = 3.6 V
VI = 5 V
50
40
30
VI = 3.6 V
60
50
VI = 4.2 V
40
VI = 5 V
30
20
20
TA = 25°C,
VO = 1.2 V,
PFM Mode
10
0
0.01
VI = 2.5 V
VI = 3 V
70
Efficiency - %
Efficiency - %
70
TA = 25°C,
VO = 1.2 V,
PWM Mode
0.1
1
10
100
1k
IO - Output Current - mA
10
10 k
0
0.01
Figure 1.
0.1
1
10
100
1k
IO - Output Current - mA
10 k
Figure 2.
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DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
DCDC2: EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
VI = 3 V
90
80
80
VI = 3.6 V
VI = 2.5 V
70
VI = 4.2 V
60
Efficiency - %
Efficiency - %
70
VI = 5 V
50
40
30
TA = 25°C,
VO = 1.8 V,
PFM Mode
10
0.1
1
10
100
1k
IO - Output Current - mA
VI = 3.6 V
50
VI = 4.2 V
40
VI = 5 V
10
0
0.01
10 k
1
10
100
1k
IO - Output Current - mA
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
DCDC3: EFFICIENCY
vs
OUTPUT CURRENT
10 k
100
TA = 25°C,
90 V = 1.8 V,
O
PWM Mode
80
VI = 3 V
70
60
Efficiency - %
VI = 3.6 V
VI = 4.2 V
VI = 5 V
50
40
VI = 2.5 V
VI = 3 V
VI = 3.6 V
60
VI = 4.2 V
50
VI = 5 V
40
30
30
20
20
TA = 25°C,
VO = 1.8 V,
PFM Mode
10
0.1
1
10
100
1k
IO - Output Current - mA
10
10 k
0
0.01
Figure 5.
18
0.1
Figure 4.
VI = 2.5 V
70
Efficiency - %
60
Figure 3.
80
0
0.01
VI = 3 V
20
100
90
VI = 2.5 V
30
20
0
0.01
TA = 25°C,
VO = 1.8 V,
PWM Mode
0.1
1
10
100
1k
IO - Output Current - mA
10 k
Figure 6.
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DCDC2: OUTPUT VOLTAGE
vs
OUTPUT CURRENT at 85°C
DCDC3: OUTPUT VOLTAGE
vs
OUTPUT CURRENT at 85°C
3.3
3.4
TA = 85°C
DEFDCDC3 = VINDCDC3
VI = 3.8 V
3.35
VI = 3.7 V
VO - Output Voltage - V
VO - Output Voltage - V
3.267
3.234
VI = 3.5 V
3.201
VI = 3.6 V
VI = 3.8 V
3.3
VI = 3.7 V
3.25
3.2
VI = 3.6 V
VI = 3.5 V
3.168
3.15
TA = 85°C
DEFDCDC2 = VINDCDC2
3.135
0.1
1
IO - Output Current - A
10
3.1
0.1
1
IO - Output Current - A
Figure 7.
Figure 8.
VDCDC1 LINE TRANSIENT RESPONSE
VDCDC2 LINE TRANSIENT RESPONSE
C1 High
4.72 V
C1 High
4.02 V
C1 Low
3.72 V
VI = 3.7 V to 4.7 V
VO = 1.2 V, IO = 100 mA
DEFDCDC1 = GND
PWM Mode
C2 Pk-Pk
24.7 mV
10
C1 Low
3.02 V
VI = 3 V to 4 V,
VO = 1.8 V, IO = 100 mA;
DEFDCDC2 = resistor divider; set for VO = 1.8 V,
PWM Mode
C2 Mean
1.20701 V
Figure 9.
C2 Pk-Pk
128 mV
C2 Mean
1.8002 V
Figure 10.
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VDCDC3 LINE TRANSIENT RESPONSE
VI = 3.6 V to 4.6 V,
VO = 3.3 V, IO = 100 mA,
DEFDCDC1 = VINDCDC3,
PWM Mode
VDCDC1 LOAD TRANSIENT RESPONSE
C1 High
4.62 V
C4 High
1.56 A
C1 Low
3.62 V
C4 Low
120 mA
VI = 3.8 V, VO = 1.2 V,
IO = 170 mA to 1530 mA
C2 Pk-Pk
91 mV
C2 Pk-Pk
166 mV
C2 Mean
3.2993 V
C2 Mean
1.2046 V
Figure 11.
Figure 12.
VDCDC2 LOAD TRANSIENT RESPONSE
VDCDC3 LOAD TRANSIENT RESPONSE
C4 High
1.12 A
VI = 3.8 V, VO = 3.3 V,
IO = 120 mA to 720 mA
C4 High
720 mA
C4 Low
80 mA
C4 Low
80 mA
C2 Pk-Pk
147 mV
C2 Pk-Pk
194 mV
VI = 3.8 V, VO = 1.8 V,
IO = 120 mA to 1080 mA
C2 Mean
3.2961 V
C2 Mean
1.7993 V
Figure 13.
20
Figure 14.
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VDCDC2 OUTPUT VOLTAGE RIPPLE
VDCDC2 OUTPUT VOLTAGE RIPPLE
VI = 3.8 V, VO = 1.8 V,
ILOAD = 1 mA; PFM Mode
C2 Pk-Pk
20.6 mV
C2 Mean
1.81186 V
Figure 15.
Figure 16.
VDCDC2 OUTPUT VOLTAGE RIPPLE
STARTUP VDCDC1, VDCDC2, AND VDCDC3
mV
Figure 17.
Figure 18.
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STARTUP LDO1 AND LDO2
LDO1 LINE TRANSIENT RESPONSE
ENABLE
C1 High
3.82 V
VCC = 3.8 V, VI LDO = 3.3 V to 3.8 V
VO = 2.1 V, IO = 25 mA
LDO1
C1 Low
3.29 V
C2 Pk-Pk
4.2 mV
C2 Mean
2.10252 V
LDO2
Ch1 = VI
Ch2 = VO
Figure 19.
Figure 20.
LDO2 LINE TRANSIENT RESPONSE
VRTC LINE TRANSIENT RESPONSE
IO = 25 mA
VO = 3.3 V
TA = 25oC
C1 High
4.51 V
Ch1 = VI
Ch2 = VO
C1 High
3.82 V
C1 Low
3.99 V
C1 Low
3.28 V
C2 PK-PK
6.1 mV
C2 PK-PK
22.8 mV
C2 Mean
3.29828 V
C2 Mean
2.98454 V
Figure 21.
22
IO = 10 mA
VO = 3 V
o
TA = 25 C
Figure 22.
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LDO1 LOAD TRANSIENT RESPONSE
VCC = 3.8 V, VI = 3.3 V, VO = 2.1 V,
IO = 20 mA to 180 mA
LDO2 LOAD TRANSIENT RESPONSE
C4 High
184 mA
C4 High
180 mA
C4 Low
16 mA
C4 Low
16 mA
C2 Pk-Pk
53.1 mV
C2 Pk-Pk
78.1 mV
C2 Mean
2.10024 V
C2 Mean
3.29606 V
VCC = 3.8 V, VI = 3.8 V, VO = 3.3 V,
IO = 20 mA to 180 mA
Figure 23.
Figure 24.
VRTC LOAD TRANSIENT RESPONSE
C4 High
21.4 mA
C4 Low
-1.4 mA
C2 PK-PK
76 mV
C2 Mean
2.9762 V
Ch2 = VO
Ch4 = IO
VI = 3.8 V
VO = 3 V
o
TA = 25 C
Figure 25.
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DETAILED DESCRIPTION
VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY
The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail (i.e. for a
Real Time Clock). The TPS650231 asserts the RESPWRON signal if VRTC drops below 2.4 V. VRTC is
selected from a priority scheme based on the VSYSIN and VBACKUP inputs.
When the voltage at the VSYSIN pin exceeds 2.65 V, VRTC connects to the VSYSIN input via a PMOS switch
and all other paths to VRTC are disabled. The PMOS switch drops a maximum of 375 mV at 30 mA, which
should be considered when using VRTC. VSYSIN can be connected to any voltage source with the appropriate
input voltage, including VCC or, if set to 3.3 V output, DCDC2 or DCDC3. When VSYSIN falls below 2.65 V or
shorts to ground, the PMOS switch connecting VRTC and VSYSIN opens and VRTC then connects to either
VBACKUP or the output of a dedicated 3V/30mA LDO. Texas Instruments recommends connecting VSYSIN to
VCC or ground - VCC if a non-replaceable primary cell is connected to VBACKUP and ground if the VRTC
output will float.
If the PMOS switch between VSYSIN and VRTC is open and VBACKUP exceeds 2.65 V, VRTC connects to
VBACKUP via a PMOS switch. The PMOS switch drops a maximum of 375 mV at 30 mA, which should be
considered if using VRTC. A typical application may connect VBACKUP to a primary Li button cell, but any
battery that provides a voltage between 2.65 V and 6 V (i.e. a single Li-Ion cell or a single boosted NiMH battery)
is acceptable, to supply the VRTC output. In systems with no backup battery, the VBACKUP pin should be
connected to GND.
If the switches between VRTC and VSYSIN or VBACKUP are open, the dedicated 3-V/30-mA LDO, driven from
VCC, connects to VRTC. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V.
Inside TPS650231 there is a switch (Vmax switch) which selects the higher voltage between VCC and
VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output
of the Vmax switch are:
• INT output
• RESPWRON output
• HOT_RESET input
• LOW_BATT output
• PWRFAIL output
• Enable pins for dc-dc converters, LDO1 and LDO2
• Undervoltage lockout comparator (UVLO)
• Reference system with low frequency timing oscillators
• LOW_BATT and PWRFAIL comparators
The main 2.25-MHz oscillator, and the I2C™ interface are only powered from VCC.
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VSYSIN
Vref
V_VSYSIN
VCC
VBACKUP
Vref
V_VBACKUP
priority
#1
priority
#2
V_VSYSIN
V_VBACKUP
EN
VRTC
LDO
priority
#3
VRTC
Vref
A.
V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%
B.
RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%
RESPWRON
Figure 26.
STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3
The TPS650231 incorporates three synchronous step-down converters operating typically at 2.25MHz fixed
frequency PWM (Pulse Width Modulation) at moderate to heavy load currents. At light load currents the
converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation). The
VDCDC1 converter is capable of delivering 1.7A output current, the VDCDC2 converter is capable of delivering
1.2A and the VDCDC3 converter delivers up to 800mA.
The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. For
DEFDCDC1 and DEFDCDC3, the pins can either be connected to GND, VCC or to a resistor divider between
the output voltage and GND.
The VDCDC1 converter defaults to 1.2V or 1.6V depending on the DEFDCDC1 configuration pin, if DEFDCDC1
is tied to ground the default is 1.2V, if it is tied to VCC the default is 1.6V. When the DEFDCDC1 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC1 V. See the
application section for more details. The core voltage can be reprogrammed via the serial interface in the range
of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst any
programmed voltage change is underway, whether the voltage is being increased or decreased. The DEFCORE
and DEFSLEW registers are used to program the output voltage and slew rate during voltage transitions.
The DEFDCDC2 pin does not have the logic function in parallel and always needs to be connected with a
resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.
The VDCDC3 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3
is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC3 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The
step-down converter outputs (when enabled) are monitored by Power Good comparators, the outputs of which
are available via the serial interface. The outputs of the DC-DC converters can be optionally discharged via
on-chip 300Ω resistors when the DC-DC converters are disabled.
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During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic will turn off the
switch. The current limit comparator will also turn off the switch in case the current limit of the P-channel switch is
exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier
is turned on and the inductor current will ramp down. The next cycle will be initiated by the clock signal again
turning off the N-channel rectifier and turning on the P-channel switch.
The three DC-DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. The phase of the
three converters can be changed using the CON_CTRL register.
POWER SAVE MODE OPERATION
As the load current decreases, the converters enter the power save mode operation. During power save mode,
the converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 2.25 MHz, nominal
for one burst cycle. However, the frequency between different burst cycles depends on the actual load current
and is typically far less than the switching frequency with a minimum quiescent current to maintain high
efficiency.
In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM
is calculated as follows:
VINDCDC1
IPFMDCDC1 enter =
24 W
IPFMDCDC2 enter =
VINDCDC2
26 W
IPFMDCDC3 enter =
VINDCDC3
39 W
(1)
During the power save mode the output voltage is monitored with a comparator, and by maximum skip burst
width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and
the converter effectively delivers a constant current defined as follows.
VINDCDC1
IPFMDCDC1 leave =
18 W
IPFMDCDC2 leave =
VINDCDC2
20 W
IPFMDCDC3 leave =
VINDCDC3
29 W
(2)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage
has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode
if either of the following conditions are met:
1. the output voltage drops 2% below the nominal VO due to increasing load current
2. the PFM burst time exceeds 16 × 1/fs (7.11 ms typical).
26
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These control methods reduce the quiescent current to typically 14 mA per converter, and the switching activity to
a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator
delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The
PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM
mode.
LOW RIPPLE MODE
Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in
PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is
reduced, depending on the actual load current. The lower the actual output current on the converter, the lower
the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage
ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is
used to keep the switching frequency above the audible range in PFM mode down to a low output current.
SOFT START
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft
start is realized by using a low current to initially charge the internal compensation capacitor. The soft start time
is typically 750 ms if the output voltage ramps from 5% to 95% of the final target value. If the output is already
precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a
short delay of typically 170 ms between the converter being enabled and switching activity actually starting. This
allows the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent
discharging of the output while the internal soft start ramp catches up with the output voltage.
100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS650231 converters offer a low input to output voltage difference while still maintaining operation with the
use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load current
and output voltage. It is calculated as:
Vin
min
+ Vout
min
) Iout max
ǒrDS(on) max ) RLǓ
(3)
with:
Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions)
rDS(on)max = maximum P-channel switch rDS(on)
RL = DC resistance of the inductor
Voutmin = nominal output voltage minus 2% tolerance limit
ACTIVE DISCHARGE WHEN DISABLED
When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or
OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is
individually enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the
VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 Ω (typical) load which is active as long as
the converters are disabled.
POWER GOOD MONITORING
All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators.
Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5%
hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An
interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when
the converters are disabled and the relevant PGOODZ register bits indicate that power is good.
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LOW DROPOUT VOLTAGE REGULATORS
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of
300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the
LDO_EN pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and
LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect
external regulators in parallel in systems with a backup battery. The TPS650231 step-down and LDO voltage
regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction
temperature rises above 160°C.
POWER GOOD MONITORING
Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these
comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any
voltage rail drops below the 10% threshold. The comparators are disabled when the LDOs are disabled and the
relevant PGOODZ register bits indicate that power is good.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit for the five regulators on the TPS650231 prevents the device from
malfunctioning at low-input voltages and from excessive discharge of the battery. It disables the converters and
LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV)
hysteresis. Note that when any of the dc-dc converters are running, there is an input current at the VCC pin,
which is up to 3 mA when all three converters are running in PWM mode. This current needs to be taken into
consideration if an external RC filter is used at the VCC pin to remove switching noise from the TPS650231
internal analog circuitry supply.
POWER-UP SEQUENCING
The TPS650231 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved
by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs.
The relevant control pins are described in Table 2.
Table 2. Control Pins and Status Outputs for DC-DC Converters
PIN NAME
I/O
FUNCTION
DEFDCDC3
I
Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.8 V,
DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V.
DEFDCDC2
I
Feedback pin of the VDCDC2 switching converter, connected to a resistive divider. The output voltage can be set
between 0.6V and VINDCDC2 V.
DEFDCDC1
I
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2 V,
DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V.
DCDC3_EN
I
Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter
DCDC2_EN
I
Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter
DCDC1_EN
I
Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter
HOT_RESET
I
TPS650231RSB only:
The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any
TPS650231 settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of VDCDC1
to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by the TPS650231.
RESPWRON
O
TPS650231RSB only:
RESPWRON is held low when power is initially applied to the TPS650231. The VRTC voltage is monitored:
RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the
TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.
TRESPWRON
I
Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms).
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SYSTEM RESET + CONTROL SIGNALS
The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron
seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an
external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the
HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)
hysteresis.
The DCDC1 converter is reset to its default output voltage defined by the DEFDCDC1 input, when HOT_RESET
is asserted. Other I2C registers are not affected. Generally, the DCDC1 converter is set to its default voltage with
one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout
(UVLO) condition, or RESPWRON active.
The RESPWRON, HOT_RESET, LOW_BAT and LOWBAT_SNS pins are not available in TPS650231YFF.
DEFLDO1 and DEFLDO2
These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to
the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of
both LDOs can be changed during operation with the I2C interface as described in the interface description.
Table 3.
DEFLDO2
DEFLDO1
VLDO1
VLDO2
0
0
1.3 V
3.3 V
0
1
2.8 V
3.3 V
1
0
1.3 V
1.8 V
1
1
2.1 V
3.3 V
Interrupt Management and the INT Pin
The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and the LDOs. The
INT pin is used as a POWER_OK pin to indicate when all enabled supplies are in regulation. The INT pin
remains active (low state) during power up as long as all enabled power rails are below their regulation limit.
Once the last enabled power rail is within regulation, the INT pin transitions to a high state.
During operation, if one of the enabled supplies goes out of regulation, INT transitions to a low state, and the
corresponding bit in the PGOODZ register goes high. If the supply goes back to its regulation limits, INT
transitions back to a high state.
While INT is in an active low state, reading the PGOODZ register via the I2C bus forces INT into a high-Z state.
Since this pin requires an external pull-up resistor, the INT pin transitions to a logic high state even though the
supply in question is still out of regulation. The corresponding bit in the PGOODZ register still indicates that the
power rail is out of regulation.
Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts
since this provides the POWER_OK function. If none of the DCDC converters or LDOs are enabled, /INT defaults
to a low state independently of the settings of the MASK register.
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TIMING DIAGRAMS
Figure 27. HOT_RESET Timing (TPS650231RSB only)
VCC
2.35V
1.9V
1.2V
2.47V
1.9V
0.8V
UVLO*
VRTC
2.52V
2.4V
3.0V
RESPWRON
tNRESPWRON
DCDCx_EN
Ramp within
800 μs
VO DCDCx
slope depending
on load
LDO_EN
VO LDOx
*... internal signal
VSYSIN=VBACKUP=GND;
VINLDO=VCC
Figure 28. Power-Up and Power-Down Timing
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Figure 29. DVS Timing
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS650231 has a 7-bit address:
1001000, other addresses are available upon contact with the factory. Attempting to read data from the register
addresses not listed in this section results in FFh being read out.
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For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS650231 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS650231 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS650231 device must leave the data line high to enable the master to generate the stop
condition
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 30. Bit Transfer on the Serial Interface
CE
DATA
CLK
S
P
START Condition
STOP Condition
Figure 31. START and STOP Conditions
SCLK
SDAT
A6
A5
A4
A0
R/W
0
Start
Slave Address
ACK
R7
R6
R5
R0
ACK
0
D7
D6
D5
D0 ACK
0
0
Register Address
Data
Stop
Note: SLAVE = TPS650231
Figure 32. Serial I/f WRITE to TPS650231 Device
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SCLK
SDAT
A6
Start
A0
R/W
ACK
0
0
R0
R7
A6
ACK
A0
R/W
ACK
1
0
0
Register
Address
Slave Address
D0
D7
ACK
Slave
Drives
the Data
Slave Address
Stop
Master
Drives
ACK and Stop
Repeated
Start
Note: SLAVE = TPS650231
Figure 33. Serial I/f READ from TPS650231: Protocol A
SCLK
SDA
A6
A0
R/W
ACK
0
Start
R0
R7
0
A6
ACK
0
R/W
ACK
D7
D0
ACK
0
1
Stop Start
Register
Address
Slave Address
A0
Slave
Drives
the Data
Slave Address
Stop
Master
Drives
ACK and Stop
Note: SLAVE = TPS650231
Figure 34. Serial I/f READ from TPS650231: Protocol B
DATA
t(BUF)
th(STA)
t(LOW)
tf
tr
CLK
th(STA)
t(HIGH)
tsu(STA)
th(DATA)
STO
STA
tsu(STO)
tsu(DATA)
STA
STO
Figure 35. Serial I/f Timing Diagram
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MIN MAX
Operating conditions:
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 2.5V to 5.5V,
VBACKUP = 3.0V,
TA = -40 °C to +85 °C
UNIT
fMAX
Clock frequency
400
kHz
twH(HIGH)
Clock high time
600
twL(LOW)
Clock low time
1300
tR
DATA and CLK rise time
300
ns
tF
DATA and CLK fall time
300
ns
th(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated)
600
ns
tsu(DATA)
Setup time for repeated START condition
600
ns
th(DATA)
Data input hold time
100
ns
tsu(DATA)
Data input setup time
100
ns
tsu(STO)
STOP condition setup time
600
ns
t(BUF)
Bus free time
1300
ns
ns
ns
VERSION. Register Address: 00h (read only)
VERSION
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
0
0
1
0
0
0
1
1
Read/Write
R
R
R
R
R
R
R
R
34
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PGOODZ. Register Address: 01h (read only)
PGOODZ
B7
Bit name and
function
PWRFAILZ
Set by signal
PWRFAIL
Default value
loaded by:
PWRFAILZ
Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B6
B5
B4
B3
B2
B1
LOWBATTZ
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
LOWBATT
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
LOWBATTZ
PGOOD
VDCDC1
PGOOD
VDCDC2
PGOOD
VDCDC3
PGOOD
LDO2
PGOOD
LDO1
R
R
R
R
R
R
R
B0
R
PWRFAILZ:
0=
indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold.
1=
indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold.
LOWBATTZ:
0=
indicates that the LOWBATT_SNS input voltage is above the 1-V threshold.
1=
indicates that the LOWBATT_SNS input voltage is below the 1-V threshold.
PGOODZ VDCDC1:
0=
indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if
the VDCDC1 converter is disabled.
1=
indicates that the VDCDC1 converter output voltage is below its target regulation voltage
PGOODZ VDCDC2:
0=
indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if
the VDCDC2 converter is disabled.
1=
indicates that the VDCDC2 converter output voltage is below its target regulation voltage
PGOODZ VDCDC3: .
0=
indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if
the VDCDC3 converter is disabled and during a DVM controlled output voltage transition
1=
indicates that the VDCDC3 converter output voltage is below its target regulation voltage
PGOODZ LDO2:
0=
indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is
disabled.
1=
indicates that LDO2 output voltage is below its target regulation voltage
PGOODZ LDO1
0=
indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is
disabled.
1=
indicates that the LDO1 output voltage is below its target regulation voltage
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MASK. Register Address: 02h (read/write)
MASK
Bit name and
function
Default
Default value
loaded by:
Read/Write
Default Value: C0h
B7
B6
B5
B4
B3
B2
B1
MASK
PWRFAILZ
MASK
LOWBATTZ
MASK
VDCDC1
MASK
VDCDC2
MASK
VDCDC3
MASK
LDO2
MASK
LDO1
1
1
0
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
B0
0
The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1
masks PGOODZ<n>.
REG_CTRL. Register Address: 03h (read/write)
Default Value: FFh
The REG_CTRL register is used to disable or enable the power supplies via the serial interface. The contents of
the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition
resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The
REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.
REG_CTRL
B7
B6
Bit name and
function
Default
1
1
Set by signal
Default value
loaded by:
Read/Write
Bit 5
B5
B4
B3
B2
B1
VDCDC1
ENABLE
VDCDC2
ENABLE
VDCDC3
ENABLE
LDO2
ENABLE
LDO1
ENABLE
1
1
1
1
1
LDO_ENZ
LDO_ENZ
DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
B0
1
VDCDC1 ENABLE
DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when
DCDC1_EN returns high.
Bit 4
VDCDC2 ENABLE
DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when
DCDC2_EN returns high.
Bit 3
VDCDC3 ENABLE
DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when
DCDC3_EN returns high.
Bit 2
LDO2 ENABLE
LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when
the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.
Bit 1
LDO1 ENABLE
LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when
the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.
36
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CON_CTRL. Register Address: 04h (read/write)
Default Value: B1h
CON_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
function
DCDC2
PHASE1
DCDC2
PHASE0
DCDC3
PHASE1
DCDC3
PHASE0
LOW
RIPPLE
FPWM
DCDC2
FPWM
DCDC1
FPWM
DCDC3
1
0
1
1
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Default value
loaded by:
Read/Write
The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low
output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to
minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is
taken as the reference and consequently has a fixed zero phase shift.
DCDC2 CONVERTER
DELAYED BY
CON_CTRL<5:4>
00
zero
00
zero
01
1/4 cycle
01
1/4 cycle
10
1/2 cycle
10
1/2 cycle
11
3/4 cycle
11
3/4 cycle
CON_CTRL<7:6>
Bit 3
Bit 2
Bit 1
Bit 0
DCDC3 CONVERTER
DELAYED BY
LOW RIPPLE:
0=
PFM mode operation optimized for high efficiency for all converters
1=
PFM mode operation optimized for low output voltage ripple for all converters
FPWM DCDC2:
0=
DCDC2 converter operates in PWM / PFM mode
1=
DCDC2 converter is forced into fixed frequency PWM mode
FPWM DCDC1:
0=
DCDC1 converter operates in PWM / PFM mode
1=
DCDC1 converter is forced into fixed frequency PWM mode
FPWM DCDC3:
0=
DCDC3 converter operates in PWM / PFM mode
1=
DCDC3 converter is forced into fixed frequency PWM mode
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CON_CTRL2. Register Address: 05h (read/write)
CON_CTRL2
Bit name and
function
Default
Default value
loaded by:
Read/Write
B7
B6
GO
Core adj
allowed
0
1
UVLO +
DONE
RESET(1)
R/W
R/W
B5
0
Default Value: 40h
B4
0
B3
B2
B1
B0
DCDC2
discharge
DCDC1
discharge
DCDC3
discharge
0
0
0
UVLO
UVLO
UVLO
R/W
R/W
R/W
0
The CON_CTRL2 register can be used to take control the inductive converters.
•
•
•
•
RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:
undervoltage lockout (UVLO)
HOT_RESET pulled low
RESPWRON active
VRTC below threshold
Bit 7
GO:
Bit 6
no change in the output voltage for the DCDC1 converter
1=
the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with
the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is
complete. The transition is considered complete in this case when the desired output voltage
code has been reached, not when the VDCDC1 output voltage is actually in regulation at the
desired voltage.
CORE ADJ Allowed:
Bit 2– 0
38
0=
0=
the output voltage is set with the I2C register
1=
DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When
connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V respectively at start-up
0=
the output capacitor of the associated converter is not actively discharged when the converter is
disabled
1=
the output capacitor of the associated converter is actively discharged when the converter is
disabled. This decreases the fall time of the output voltage at light load
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DEFCORE. Register Address: 06h (read/write
DEFCORE
B7
B6
B5
Bit name and
function
Default
0
0
0
Default value
loaded by:
Read/Write
Default Value: 14h/1Eh
B4
B3
B2
B1
B0
CORE4
CORE3
CORE2
CORE1
CORE0
1
DEFDCDC1
DEFDCDC1
DEFDCDC1
DEFDCDC1
RESET(1)
RESET(1)
RESET(1)
RESET(1)
RESET(1)
R/W
R/W
R/W
R/W
R/W
RESET(1): DEFCORE is reset to its default value by one of these events:
• undervoltage lockout (UVLO)
• HOT_RESET pulled low
• RESPWRON active
• VRTC below threshold
CORE4 CORE3
CORE2
CORE1
CORE0
VDCDC1
CORE4
CORE3
CORE2
CORE1
CORE0
VDCDC1
0
0
0
0
0
0.8 V
1
0
0
0
0
1.2 V
0
0
0
0
1
0.825 V
1
0
0
0
1
1.225 V
0
0
0
1
0
0.85 V
1
0
0
1
0
1.25 V
0
0
0
1
1
0.875 V
1
0
0
1
1
1.275 V
0
0
1
0
0
0.9 V
1
0
1
0
0
1.3 V
0
0
1
0
1
0.925 V
1
0
1
0
1
1.325 V
0
0
1
1
0
0.95 V
1
0
1
1
0
1.35 V
0
0
1
1
1
0.975 V
1
0
1
1
1
1.375 V
0
1
0
0
0
1V
1
1
0
0
0
1.4 V
0
1
0
0
1
1.025 V
1
1
0
0
1
1.425 V
0
1
0
1
0
1.05 V
1
1
0
1
0
1.45 V
0
1
0
1
1
1.075 V
1
1
0
1
1
1.475 V
0
1
1
0
0
1.1 V
1
1
1
0
0
1.5 V
0
1
1
0
1
1.125 V
1
1
1
0
1
1.525 V
0
1
1
1
0
1.15 V
1
1
1
1
0
1.55 V
0
1
1
1
1
1.175 V
1
1
1
1
1
1.6 V
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DEFSLEW. Register Address: 07h (read/write)
DEFSLEW
B7
B6
Default Value: 06h
B5
B4
B3
Bit name and
function
B2
B1
B0
SLEW2
SLEW1
SLEW0
1
1
0
UVLO
UVLO
UVLO
R/W
R/W
R/W
Default
Default value
loaded by:
Read/Write
40
SLEW2
SLEW1
SLEW0
VDCDC1 SLEW RATE
0
0
0
0.225 mV/ms
0
0
1
0.45 mV/ms
0
1
0
0.9 mV/ms
0
1
1
1.8 mV/ms
1
0
0
3.6 mV/ms
1
0
1
7.2 mV/ms
1
1
0
14.4 mV/ms
1
1
1
Immediate
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LDO_CTRL. Register Address: 08h (read/write)
LDO_CTRL
Bit name and
function
B7
B6
RSVD
Default
B5
Default Value: set with DEFLDO1 and DEFLDO2
B4
B3
RSVD
B2
B1
B0
LDO1_2
LDO1_1
LDO1_0
LDO2_2
LDO2_1
LDO2_0
DEFLDOx
DEFLDOx
DEFLDOx
DEFLDOx
DEFLDOx
DEFLDOx
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
Default value
loaded by:
Read/Write
The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2. LDO_CTRL[7] and
LDO_CTRL[3] are reserved and should always be written to 0.
The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3.
LDO2_2
LDO2_1
LDO2_0
LDO2 OUTPUT
VOLTAGE
LDO1_2
LDO1_1
LDO1_0
LDO1 OUTPUT
VOLTAGE
0
0
0
1.05 V
0
0
0
1V
0
0
1
1.2 V
0
0
1
1.1 V
0
1
0
1.3 V
0
1
0
1.3 V
0
1
1
1.8 V
0
1
1
2.1 V
1
0
0
2.5 V
1
0
0
2.2 V
1
0
1
2.8 V
1
0
1
2.6 V
1
1
0
3.0 V
1
1
0
2.8 V
1
1
1
3.3 V
1
1
1
3.15 V
DESIGN PROCEDURE
Inductor Selection for the DC-DC Converters
Each of the converters in the TPS650231 typically use a 2.2 mH output inductor. Larger or smaller inductor
values are used to optimize the performance of the device for specific operation conditions. The selected
inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductance
influences directly the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be
selected for highest efficiency.
For a fast transient response, a 2.2-mH inductor in combination with a 22-mF output capacitor is recommended.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is needed
because during heavy load transient the inductor current rises above the value calculated under Equation 4.
1 * Vout
Vin
DI + Vout
L
L ƒ
(4)
I
Lmax
+ I outmax )
DI
L
2
(5)
with:
f = Switching Frequency (2.25 MHz typical)
L = Inductor Value
ΔIL = Peak-to-Peak inductor ripple current
ILMAX = Maximum Inductor current
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents
versus a comparable shielded inductor.
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A more conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS650231 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core
material from inductor to inductor differs and has an impact on the efficiency especially at high switching
frequencies.
See Table 4 and the typical applications for possible inductors.
Table 4. Tested Inductors
DEVICE
INDUCTOR
VALUE
TYPE
COMPONENT SUPPLIER
2.2 mH
LPS4012-222LMB
Coilcraft
2.2 mH
VLCF4020T-2R2N1R7
TDK
For DCDC2 or
DCDC3
2.2 mH
LQH32PN2R2NN0
Murata
2.2 mH
PSI25201T-2R2
Cyntec
For DCDC1
1.5 mH
LQH32PN1R5NN0
Murata
All Converters
Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the
TPS650231 allow the use of small ceramic capacitors with a typical value of 10 mF for each converter without
having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low
ESR values have the lowest output voltage ripple and are recommended. See Table 5 for recommended
components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. Just for completeness, the RMS ripple current is calculated as:
V
1 - out
Vin
1
x
IRMSCout = Vout x
L x ¦
2 x Ö3
(6)
At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the
sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
V
1 - out
Vin
1
DVout = Vout x
x
+ ESR
L x ¦
8 x Cout x ¦
(
)
(7)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output
capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The
typical output voltage ripple is less than 1% of the nominal output voltage.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. Each dc-dc converter requires a 10-mF ceramic input capacitor on its input pin VINDCDCx. The
input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the
input for the dc-dc converters. A filter resistor of up to 10R and a 1-mF capacitor is used for decoupling the VCC
pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow via
this resistor into the VCC pin when all converters are running in PWM mode.
42
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Table 5. Possible Capacitors
CAPACITOR VALUE
CASE SIZE
COMPONENT SUPPLIER
COMMENTS
22 mF
0805
TDK C2012X5R0J226MT
Ceramic
22mF
0805
Taiyo Yuden JMK212BJ226MG
Ceramic
10 mF
0805
Taiyo Yuden JMK212BJ106M
Ceramic
10 mF
0805
TDK C2012X5R0J106M
Ceramic
10 mF
0603
Taiyo Yuden JMK107BJ106
Ceramic
Output Voltage Selection
The DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. For DEFDCDC1 and DEFDCDC3 there are default voltages defined when the pin is tied to a logic low
or logic high signal. See Table 6for the default voltages if the pins are pulled to GND or to Vcc. If a different
voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 36.
The output voltage of VDCDC1 is set with the I2C interface. If the voltage is changed from the default, using the
DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC1
will not change the voltage set with the register. It is not recommended to change the divider ratio of a resistor
divider connected at DEFDCDC1 or DEFDCDC3 during operation as the internal logic may detect a logic high
signal in error during the change from a high voltage to a lower voltage and will scale the output to the voltage
defined by DEFDCDCx = HIGH. As DEFDCDC2 does not have these default fixed voltages, the resistor divider
can be changed during operation.
Table 6.
PIN
DEFDCDC1
DEFDCDC3
LEVEL
DEFAULT OUTPUT VOLTAGE
VCC
1.6 V
GND
1.2 V
VCC
3.3 V
GND
1.8 V
This function is not available on the DCDC2 converter. DEFDCDC2 always needs to be connected to a resistive
divider as shown below.
Using an external resistor divider at DEFDCDCx:
1Ω
V(bat)
VCC
1 mF
VDCDC3
L3
VINDCDC3
CI
CO
DCDC3_EN
VO
L
R1
DEFDCDC3
R2
AGND
PGND
Figure 36. External Resistor Divider
When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input
voltage V(bat). The total resistance (R1+R2) of the voltage divider should be kept in the 1-MΩ range in order to
maintain a high efficiency at light load.
V(DEFDCDCx) = 0.6 V
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R1 + R2
R2
VOUT = VDEFDCDCx x
R1 = R2 x
(
VOUT
VDEFDCDCx
)
- R2
(8)
VRTC Output
It is recommended that a 4.7-mF (minimum) capacitor be added to the VRTC pin.
LDO1 and LDO2
The LDOs in the TPS650231 are general-purpose LDOs which are stable using ceramics capacitors. The
minimum output capacitor required is 2.2 mF. The LDOs output voltage can be changed to different voltages
between 1 V and 3.3 V using the I2C interface. The supply voltage for the LDOs needs to be connected to the
VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and provides the highest
efficiency.
TRESPWRON
This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V.
The timing is generated by charging and discharging the capacitor with a current of 2 mA between a threshold of
0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.
t(reset) = 2 x 128 x
(
(1 V - 0.25 V) x C(reset)
2 mA
)
(9)
Where:
t(reset) is the reset delay time
C(reset) is the capacitor connected to the TRESPWRON pin
VCC-Filter
An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and other
analog circuitry. A typical value of 1 Ω and 1 mF is used to filter the switching spikes, generated by the dc-dc
converters. A larger resistor than 10 Ω should not be used because the current into VCC of up to 3 mA causes a
voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to switch off
too early.
44
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Product Folder Link(s) : TPS650231
TPS650231
www.ti.com
SLVSAE3 – AUGUST 2010
APPLICATION INFORMATION
Typical Configuration for the Texas Instruments® TMS320DM644x DaVinci Processors
TPS650231
Reset Condition of DCDC1
If DEFDCDC1 is connected to ground and DCDC1_EN is pulled high after VINDCDC1 is applied, the output
voltage of DCDC1 defaults to 1.225V instead of 1.2V (high by 2%). Figure 37 illustrates the problem.
VCC/VINDCDC1
DCDC1_EN
1.225 V
1.225 V
1.225 V
VDCDC1
Figure 37. Default DCDC1
Workaround 1: Tie DCDC1_EN to VINDCDC1 (Figure 38)
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TPS650231
SLVSAE3 – AUGUST 2010
www.ti.com
VCC/VINDCDC1
DCDC1_EN
1.20 V
1.20 V
1.20 V
VDCDC1
Figure 38. Workaround 1
Workaround 2: Write the correct voltage to the DEF_CORE register via I2C. This can be done before or after the
converter is enabled. If written before the enable, the only bit changed is DEF_CORE[0]. The voltage will be
1.2V, however, when the enable is pulled high (Figure 39).
VCC/VINDCDC1
DCDC1_EN
I2C Bus
DEF_CORE
??
0x1F
0x11
1.225 V
VDCDC1
0x10
??
0x1F
0x1E
1.20 V
1.20 V
Pull DCDC1_EN High
Write DEF_CORE to 0x10
Write CON_CTRL [7] to 1
0x10
Write DEF_CORE to 0x10
Pull DCDC1_EN High
Figure 39. Workaround 2
Workaround 3: Generate a HOT_RESET after enabling DCDC1 (Figure 40)
VCC/VINDCDC1
DCDC1_EN
HOT_RESET
1.225 V
VDCDC1
1.20 V
1.225 V
1.20 V
Figure 40. Workaround 3
46
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Product Folder Link(s) : TPS650231
TPS650231
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SLVSAE3 – AUGUST 2010
DIFFERENCES OF TPS650231 VERSUS TPS65023 and TPS65023B
ITEM
DESCRIPTION
TPS65023
TPS65023B
TPS650231
VIH
High level input voltage for the SDAT pin
Minimum 1.3V
Minimum 1.65V;
Vcc = 2.5V to 5.25V
Minimum 1.65V;
Vcc = 2.5V to 5.25V
VIH
High level input voltage for the SCLK pin
Minimum 1.3V
Minimum 1.4V,
Vcc = 2.5V to 5.25V
Minimum 1.4V,
Vcc = 2.5V to 5.25V
VIL
Low level input voltage for SCLK and
SDAT pin
Maximum 0.4V
Maximum 0.35V
Maximum 0.35V
th(DATA)
Data input hold time
Minimum 300ns
Minimum 100ns
Minimum 100ns
tsu(DATA)
Data input setup time
Minimum 300ns
Minimum 100ns
Minimum 100ns
1.8V
1.8V
2.1V
1) DEFDCDC2=LOW:
Vo=1.8V
2) DEFDCDC2=HIGH:
Vo=3.3V
3) 0.6V feedback input
1) DEFDCDC2=LOW:
Vo=1.8V
2)DEFDCDC2=HIGH:
Vo=3.3V
3)0.6V feedback input
0.6V feedback input only
(allows voltage scaling
with external resistor
divider without
restrictions)
LDO1 voltage for setting LDO1_[2..0] = 011
DEFDCDC2 pin functionality
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS650231RSBR
ACTIVE
WQFN
RSB
40
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
Purchase Samples
TPS650231RSBT
ACTIVE
WQFN
RSB
40
250
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
Request Free Samples
TPS650231YFFR
ACTIVE
DSBGA
YFF
49
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Purchase Samples
TPS650231YFFT
ACTIVE
DSBGA
YFF
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS650231RSBR
Package Package Pins
Type Drawing
WQFN
RSB
40
TPS650231RSBT
WQFN
RSB
TPS650231YFFR
DSBGA
YFF
TPS650231YFFT
DSBGA
YFF
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.1
8.0
12.0
Q2
3000
330.0
12.4
5.25
5.25
40
250
330.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
49
3000
180.0
8.4
3.3
3.3
0.75
4.0
8.0
Q1
49
250
180.0
8.4
3.3
3.3
0.75
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS650231RSBR
WQFN
RSB
40
3000
340.5
338.1
20.6
TPS650231RSBT
WQFN
RSB
40
250
340.5
338.1
20.6
TPS650231YFFR
DSBGA
YFF
49
3000
190.5
212.7
31.8
TPS650231YFFT
DSBGA
YFF
49
250
190.5
212.7
31.8
Pack Materials-Page 2
X: Max = 3132 µm, Min = 3032 µm
Y: Max = 3116 µm, Min = 3016 µm
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