RSTIN SHUTD CLKRUN VCC POLLMODE NC GND STOP PCLK GND NC ACTIVE SCPS015A – JULY 1997 – REVISED JANUARY 1998 D 5-V Core Logic With PCI Interface D Supports PCI Clock Frequencies up to D D 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 IRQ15 IRQ3 VCC GND IRQ14 IRQ13 NC IRQ8 NC VCC IRQ12 IRQ11 IRQSER IRQ0 IRQ1 IRQ2/SMI VCC NC INTD INTC INTB INTA GND DRIVEMODE IRQ10 IRQ9 IRQ7 IRQ6 GND VCC NC NC IRQ5 NC NC IRQ4 D 33 MHz Accepts IRQSER Serial Interrupt Stream Input From TI PC Card Controllers Provides System Access to All 15 ISA-Style IRQs and 4 PCI-Style Interrupts Offered in 48-Pin TQFP Package description The PCI950 is an IRQSER interrupt deserializer that interfaces with existing and future TI PC Card controllers. The PCI950 accepts the IRQSER output of a TI PC Card controller and converts it to 16 ISA-style interrupts and 4 PCI-style interrupts. Interfacing the PC Card controller with the PCI950 permits system access of all available interrupts and features of the PC Card controller. functional block diagram PCLK RSTIN CLKRUN IRQSER POLLMODE SHUTD STOP DRIVEMODE PCI950 16 IRQ15–0 4 INTA–D ACTIVE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated !" #$ # % & ## '($ # ) # "( "# ) "" $ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCPS015A – JULY 1997 – REVISED JANUARY 1998 Terminal Functions TERMINAL NAME NO. I/O TYPE FUNCTION ACTIVE 25 O Device active. When the PCI950 is busy, this output is low and when the PCI950 is idle, this output is high. CLKRUN 34 I/O PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow the PCI clock rate. When the PCI950 is busy and CLKRUN is sampled high, then CLKRUN is driven low for two clock cycles. If CLKRUN is not used, it can be tied low. See Note 1. Drive mode. When this input is high and the PCI950 samples a low on the IRQSER line during the sample phase of the IRQ data frame, then the PCI950 drives the IRQSER line high during the recovery phase. When this input is low and the PCI950 samples a low level on the IRQSER line during the sample phase of the IRQ data frame, then the PCI950 three-states the IRQSER line during the recovery phase. DRIVEMODE 13 I GND 5, 14, 27, 30, 40 — Device ground terminals INTA, INTB, INTC, INTD 15, 16, 17, 18 O PCI-style interrupts. These are four parallel PCI-style Interrupts, INTA–INTD. The PCI950 provides the PCI interrupts in an open-drain environment, which requires the system vendor to implement a pullup resistor on each implemented interrupt. IRQ0, IRQ1, IRQ3–15 23, 22, 38,12, 9, 4, 3, 44, 2, 1, 48, 47, 42, 41, 37 O ISA-style interrupts. These are 15 parallel ISA interrupts, IRQ0, 1, 3–15. The PCI950 provides the ISA interrupts in an open-drain environment, which requires the system vendor to implement a pullup resistor on each implemented interrupt. IRQ2/SMI 21 O System management interrupt. The PCI950 provides the SMI interrupt in an open-drain environment, which requires the system vendor to implement a pullup resistor on each implemented interrupt. IRQSER 24 I/O Serial interrupt stream from PC Card controller. This input is connected to the IRQSER output from the TI PC Card controller. NC 7, 8, 10, 11, 19, 26, 31, 43, 45 — No connection PCLK 28 I PCI-bus clock. The PCI-bus clock operates at frequencies ranging from 0–33 MHz. POLLMODE 32 I Poll mode. Selects between quiet mode and continuous mode. When this input is low, the PCI950 is in quiet mode. When this input is high, the PCI950 is in continuous mode. The POLLMODE signal is sampled during the rising edge of a start frame. After reset, the PCI950 generates the first cycle, and the stop-frame width in this cycle is set based on the POLLMODE input level. Any change in POLLMODE input causes the PCI950 to generate a start pulse. RSTIN 36 I Device reset. When RSTIN is asserted low, the internal counters are reset and all output buffers are put in a high-impedance state (three stated). After RSTIN is deasserted, the PCI950 defaults to continuous mode. I Shutdown. When SHUTD input is low, the internal clock is stopped and the outputs are placed in a high-impedance state (three stated). When SHUTD input is high, the device is in normal operation. During continuous mode of operation, the recommended use of SHUTD is to first assert STOP input, check that ACTIVE is high, and then assert SHUTD to stop the clock. During quiet mode of operation, the SHUTD input can be asserted after ACTIVE is sampled high. Stop continuous mode. The default number of idle clocks between stop and start frame in continuous mode is one. But the STOP pin can be used to insert more than one idle state. If the PCI950 is in continuous mode and if during an IRQSER cycle the STOP input is driven low, then after completion of the IRQSER cycle any number of idle states can be inserted. The next start frame is initiated by PCI950 when STOP is driven high. If STOP is not to be used, then it must be tied high. See Note 1. SHUTD 35 STOP 29 I VCC 6, 20, 33, 39, 46 — Device 5-V power-supply terminals NOTE 1: Unused active-low inputs must be pulled up to VCC using a 43 kW resistor, and unused active-high inputs must be pulled down to GND using a 43 kW resistor. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCPS015A – JULY 1997 – REVISED JANUARY 1998 functional description The PCI950 accepts the serialized IRQ stream from the PC Card controller for conversion to discrete ISA and PCI interrupts. The serialized IRQ protocol is defined in the document Serialized IRQ Protocol for PCI Systems, revision 6.0. This protocol uses a serial packet consisting of one start frame, several IRQ/data frames, and one stop frame. Start frame: There are two modes of operation for the IRQSER start frame – quiet mode and continuous mode. During continuous mode the PCI950 initiates the start frame. A low level on the POLLMODE input pin selects the quiet mode and a high level selects continuous mode for the PCI950. The total low-pulse width on a start frame is eight clocks. After reset the PCI950 defaults to continuous mode. IRQ/data frame: The PCI950 is designed to decode a fixed length of 21 IRQ/data frames that are sampled in the following sequence: IRQ0, IRQ1, SMI, IRQ3 through IRQ15, IOCHK, INTA, INTB, INTC, and INTD. Stop frame: After the completion of a start frame and 21 IRQ data frames, the PCI950 generates a stop frame. The pulse width of the stop pulse is determined by the status of the POLLMODE input pin sampled during the start frame. Start Frame (see Notes 2 and 3) R T IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 ––– S R T S R T S R T S R T S R T PCLK IRQSER 2 DRIVE PCI950 IRQ3 None None Legend: R = Recovery S = Sample T = Turnaround NOTES: 2. Start frame is eight clocks in duration. 3. Slave or host initiated: POLLMODE is level dependent. Figure 1. IRQSER Start-Frame Timing IRQ15 S R T IOCHK S R T INTA S R INTB T S R INTC T S R Stop Frame I (see Notes 4 and 5) (see Note 6) INTD T S R T I R T PCLK IRQSER DRIVE IRQ15 None PCI950 Legend: R = Recovery S = Sample T = Turnaround I = Idle NOTES: 4. The PCI950 stop pulse is two or three clocks in duration. 5. There may be none, one, or more idle states during the stop frame. 6. When the PCI950 is in continuous mode, there are 17 idle states between the stop frame and the start frame. Figure 2. IRQSER Stop-Frame Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IRQ0 R T S R T –– – INTD S R T 17 Stop Frame Clocks R T Start Frame IRQ0 R T S R T ––– INTD S R T Stop Frame R T *#+"+, *#+"+*#+"+. Start Frame D336 123456 functional description (continued) 4 Figure 1Figure 2 PCLK POLLMODE (see Note 7) (see Note 8) IRQSER DRIVE PCI950 PCI950 PCI950 PCI950 Legend: R = Recovery S = Sample T = Turnaround NOTES: 7. When the POLLMODE input level changes before the rising edge of the start frame, then the stop-frame width in the current IRQSER cycle reflects the change in mode. 8. Any change in the POLLMODE input level after the start frame is complete is reflected in the next IRQSER cycle. Figure 3. POLLMODE Level Change During an IRQSER Cycle /01+0 SCPS015 – JULY 1997 – REVISED JANUARY 1998 functional description (continued) 1234567Figure 1Figure 2Figure 38 Start Frame R T S IRQ0 R T ––– S INTD R T Stop Frame R T PCLK ACTIVE (see Note 9) (see Note 10) IRQSER DRIVE PCI950 PCI950 Legend: R = Recovery S = Sample T = Turnaround NOTES: 9. ACTIVE goes low one clock cycle after the beginning of the PCI950 start pulse. 10. ACTIVE is set high two clock pulses after the PCI950 stop pulse. Figure 4. ACTIVE Output Timing During Quiet Mode Stop Frame R T 16 Clocks Stop Frame R T PCLK STOP (See Notes 11 and 12) ACTIVE IRQSER DRIVE PCI950 PCI950 Legend: R = Recovery T = Turnaround NOTES: 11. STOP can only be used to insert idle states in continuous mode. 12. The recommended sequence for using SHUTD is to: A. Assert STOP. B. Ensure that ACTIVE is not asserted. C. Assert SHUTD. Figure 5. Using STOP During Continuous Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCPS015 – JULY 1997 – REVISED JANUARY 1998 APPLICATION INFORMATION system-level implementation A typical PCI950 system implementation is shown in Figure 6. The PCI950 allows software access to interrupts that may not exist on the periphery of the PC Card controller, thus increasing the overall interrupt resources that can be utilized. Microprocessor Memory Host Bridge/ MCU PCI Bus Super I/O PCI-to-ISA Bridge Deserializer PCI950 ISA Bus PC Card Figure 6. Typical System Installation 6 POST OFFICE BOX 655303 PCI1130 • DALLAS, TEXAS 75265 PC Card SCPS015 – JULY 1997 – REVISED JANUARY 1998 absolute maximum ratings over operating temperature ranges (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 13. Applies to external input and bidirectional buffers 14. Applies to external output and bidirectional buffers recommended operating conditions (see Note 15) Commercial MIN NOM MAX UNIT 4.75 5 5.25 V VCC Supply voltage VIH‡ High-level input voltage 2 VCC V VIL‡ Low-level input voltage 0 0.8 V VI Input voltage 0 VCC V VO§ Output voltage 0 VCC V tt Input transition time [rise time (tr) and fall time (tf), see Figure 7] 0 TA TJ¶ Operating ambient temperature range 0 25 ns 25 70 °C Virtual junction temperature 0 25 ‡ Applies to external inputs and bidirectional buffers without hysteresis § Applies to external output buffers ¶ These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. NOTE 15: Unused pins (input or I/O) must be forced or tied high or low to prevent them from floating. 115 °C electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER PINS TEST CONDITIONS MIN MAX PCI# IOH = –2 mA 2.4 Standard IOH = –4 mA 2.1 PCI# IOL = 6 mA 0.55 Standard IOL = 4 mA 0.5 UNIT VOH Hi h l High-level l output t t voltage lt V VOL Low level output voltage Low-level IOZL 3-state output, high-impedance state current Output pins VI = GND –10 µA IOZH 3-state output, high-impedance state current Output pins VI = VCC 10 µA Input pins L Low-level l l input i current VI = GND –1 IIL I/O pins|| VI = GND –10 Input pins High level input current High-level VI = VCC 1 IIH I/O pins|| VI = VCC 10 V µA A µA # PCI pins are INTA, INTB, INTC, INTC, and SERIRQ. || For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCPS015 – JULY 1997 – REVISED JANUARY 1998 PARAMETER MEASUREMENT INFORMATION LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD† (pF) IOL (mA) IOH (mA) VLOAD (V) 50 8 –8 0 3 50 8 –8 1.5 50 8 –8 ‡ IOL From Output Under Test Test Point VLOAD CLOAD † CLOAD includes the typical load-circuit distributed capacitance. IOH ‡ VLOAD – VOL = 50 Ω, where V OL = 0.6 V, IOL = 8 mA IOL LOAD CIRCUIT VCC Timing Input (see Note A) 50% VCC High-Level Input 0V th tsu 90% VCC Data Input 10% VCC 50% VCC Low-Level Input 0V tf VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES 50% VCC tpd 50% VCC VOH 50% VCC VOL tpd Waveform 1 (see Notes B and C) VOH 50% VCC VOL Waveform 2 (see Notes B and C) tPLZ 50% VCC tPHZ tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 50% VCC 0V tpd 50% VCC VCC 50% VCC 0V VCC tPZL 50% VCC tpd Out-of-Phase Output Output Control (low-level enabling) 0V In-Phase Output 50% VCC VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC VCC 50% VCC 0V tw VCC 50% VCC tr Input (see Note A) 50% VCC 50% VCC VCC ≅ 50% VCC VOL + 0.3 V VOL VOH VOH – 0.3 V ≅ 50% VCC 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the following characteristics: PRR = 1 MHz, ZO = 50 Ω, tr = 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ, VOL and VOH are measured values. Figure 7. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCPS015 – JULY 1997 – REVISED JANUARY 1998 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°–ā7° 0,75 0,45 0,10 4040052/C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SCPS015 – JULY 1997 – REVISED JANUARY 1998 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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