SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 D D D D D D Member of the Texas Instruments Widebus Family Independent Asynchronous Inputs and Outputs 1024 Words × 18 Bits Read and Write Operations Can Be Synchronized to Independent System Clocks Programmable Almost-Full/Almost-Empty Flag D D D D Input-Ready, Output-Ready, and Half-Full Flags Cascadable in Word Width and/or Word Depth Fast Access Times of 20 ns With a 50-pF Load High Output Drive for Direct Bus Interface Package Options Include 68-Pin Ceramic PGA (GB) or Space-Saving 68-Pin Ceramic Quad Flatpack (HV)† description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN54ACT7811 is a 1024 × 18-bit FIFO for high speed and fast access times. It processes data at rates up to 28.5 MHz and access times of 20 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The SN54ACT7811 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry adds the ability to synchronize independent read and write (interrupts, requests) to their respective system clock. The SN54ACT7811 is characterized for operation from – 55°C to 125°C. GB PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 A B C D E F G H J † The SN54ACT7811 HV is not production released. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 GB-Package Terminal Assignments TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL A1 Q15 B7 Q5 F2 D17 H8 D0 A2 Q13 B8 Q4 F8 WRTEN2 H9 DAF A3 Q12 B9 Q1 F9 AF/AE J1 D11 A4 Q11 C1 RESET G1 D16 J2 D10 A5 Q10 C2 Q16 G2 D15 J3 D8 A6 Q8 C8 Q2 G8 WRTCLK J4 NC A7 Q7 C9 Q0 G9 WRTEN1 J5 D7 A8 Q6 D1 OE H1 D14 J6 D6 A9 Q3 D9 HF H2 D13 J7 D5 B1 OR E1 RDEN1 H3 D12 J8 D3 B2 Q17 E2 RDEN2 H4 D9 J9 D2 B3 Q14 E9 IR H6 D4 B5 Q9 F1 RDCLK H7 D1 VCC = B4, C6, C7, D2, D7, E8, G3, G4, G6 NC = No internal connection GND = B6, C3, C4, D3, D8, F3, F7, G7, H5 D15 D16 D17 GND RDCLK RDEN1 RDEN2 OE RESET V CC GND OR VCC Q17 Q16 GND Q15 HV PACKAGE† (TOP VIEW) 9 10 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DAF GND WRTCLK WRTEN1 WRTEN2 VCC AF/AE GND IR HF VCC Q0 Q1 GND Q2 Q3 VCC D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 D3 D2 D1 D0 † The SN54ACT7811 HV is not production released. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC Q6 Q5 GND Q4 NAME SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 logic symbol† Φ FIFO 1024 × 18 RESET WRTCLK WRTEN1 WRTEN2 RDCLK RDEN1 OE RDEN2 DAF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 C1 RESET G8 WRTCLK G9 & F8 F1 IN RDY WRTEN RDCLK HALF FULL ALMOST FULL/EMPTY E1 OUT RDY & D1 EN1 E9 D9 F9 B1 IR HF AF/AE OR RDEN E2 H9 H8 DEF ALMOST FULL 0 0 C9 H7 B9 J9 C8 J8 A9 H6 B8 J7 B7 J6 A8 J5 A7 J3 A6 Data H4 Data 1 B5 J2 A5 J1 A4 H3 A3 H2 A2 H1 B3 G2 A1 G1 C2 F2 17 17 B2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the GB package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 functional block diagram OE D0 – D17 RDCLK RDEN1 RDEN2 Synchronous Read Control Location 1 Location 2 Read Pointer 1024 × 18 RAM WRTCLK WRTEN1 WRTEN2 Synchronous Write Control Write Pointer Location 1023 Location 1024 Register Reset Logic Q0 – Q17 RESET StatusFlag Logic DAF OR IR HF AF/AE 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 Terminal Functions TERMINAL† NAME NO. I/O DESCRIPTION AF/AE boundary is defined by the AF/AE offset value (X). This value can be programmed during reset, or the default value of 256 can be used. The AF/AE flag is high when the FIFO contains (X + 1) or fewer words or (1025 – X) or more words. The AF/AE flag is low when the FIFO contains between (X + 2) and (1024 - X) words. Programming procedure for AF/AE – The AF/AE flag is programmed during each reset cycle. The AF/AE offset value (X) is either a user-defined value or the default of X = 256. Instructions to program AF/AE using both methods are as follows: User-defined X AF/AE F9 O Step 1: Take DAF from high to low. Step 2: If the reset (RESET) input is not already low, take RESET low. Step 3: With DAF held low, take RESET high. This defines the AF/AE flag using X. Step 4: To retain the current offset for the next reset, keep DAF low. Default X To redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset cycle. DAF H9 I Define almost full. The high-to-low transition of DAF stores the binary value of data inputs as the AF/AE offset value (X). With DAF held low, a low pulse on the reset (RESET) input defines the AF/AE flag using X. D0 – D17 F2, G1, G2, H1 – H4, H6 – H8, J1 – J3, J5 – J9 I Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0 – D8 also carry the AF/AE offset value (X) on a high-to-low transition of the DAF input. HF D9 O Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512 or fewer words. IR E9 O Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR is driven low on the rising edge of the second write clock (WRTCLK) pulse. IR is then driven high on the rising edge of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low, IR is driven high on the second WRTCLK pulse after the first valid read. OE D1 I Output enable. The data-out (Q0 – Q17) outputs are in the high-impedance state when OE is low. OE must be high before the rising edge of read clock (RDCLK) to read a word from memory. O Output ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset, OR is set low on the rising edge of the third read clock (RDCLK) pulse. OR is set high on the rising edge of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising edge of the first RDCLK pulse after the last word is read. O Data outputs. The first data word to be loaded into the FIFO is moved to the data-out (Q0 – Q17) register on the rising edge of the third read clock (RDCLK) pulse to occur after the first valid write. The read-enable (RDEN1, RDEN2) inputs do not affect this operation. The following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, OE, and OR are high. OR B1 Q0 – Q17 A1 – A9, B2, B3, B5, B7 – B9, C2, C8, C9 RDCLK F1 I Read clock. Data is read out of memory on a low-to-high transition at RDCLK if the OR output and the OE, RDEN1, and RDEN2 control inputs are high. RDCLK is a free-running clock and functions as the synchronizing clock for all data transfers out of the FIFO. OR is also driven synchronously with respect to RDCLK. RDEN1, RDEN2 E1 E2 I Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out of memory. The read enables are not used to read the first word stored in memory. I Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF, and IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF input at a low level, a low pulse on RESET defines AF/AE using the AF/AE offset value (X), where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines AF/AE using the default value of X = 256. RESET C1 † Terminals listed are for the GB package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 Terminal Functions (Continued) TERMINAL† NAME NO. I/O DESCRIPTION WRTCLK G8 I Write clock. Data is written into memory on a low-to-high transition of WRTCLK if the IR output and the WRTEN1 and WRTEN2 control inputs are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all data transfers into the FIFO. IR output is also driven synchronously with respect to the WRTCLK signal. WRTEN1, WRTEN2 G9 F8 I Write enables. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to be written into memory. The write enables do not affect the storage of the AF/AE offset value (X). † Terminals listed are for the GB package. RESET DAF WRTCLK WRTEN1 WRTEN2 D0 – D17 RDCLK RDEN1 RDEN2 OE Q0 – Q17 OR AF/AE HF IR ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Don’t Care 1 2 3 4 1 2 Don’t Care Don’t Care X† Don’t Care 1 2 3 4 Don’t Care Don’t Care 1 0 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Invalid Don’t Care Don’t Care Don’t Care Don’t Care Store the Value of D0 – D8 as X † X is the binary value of D0 – D8 only. Define the AF/AE Flag Using the Value of X Figure 1. Reset Cycle: Define AF/AE Using the Value of X 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RESET DAF Don’t Care WRTCLK 1 WRTEN1 Don’t Care WRTEN2 Don’t Care 2 3 4 1 2 Don’t Care D0 – D17 RDCLK 1 2 RDEN1 Don’t Care RDEN2 Don’t Care 3 4 1 0 OE Q0 – Q17 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Don’t Care OR AF/AE Don’t Care HF Don’t Care IR Invalid Don’t Care Define the AF/AE Flag Using the Value of X = 256 Figure 2. Reset Cycle: Define AF/AE Using the Default Value POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 1 0 RESET ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Don’t Care DAF WRTCLK 1 0 WRTEN1 WRTEN2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D0 – D17 RDCLK W1 W2 W3 W4 1 2 3 W(X+2) W513 W(1025–X) W1025 1 0 RDEN1 RDEN2 1 0 OE ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Q0 – Q17 Invalid W1 OR AF/AE HF IR Figure 3. Write Cycle 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 RESET ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 1 0 Don’t Care DAF WRTCLK 1 2 WRTEN1 WRTEN2 D0 – D17 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W1025 RDCLK RDEN1 RDEN2 OE Q0 – Q17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ W1 W1 W2 W3 W(X+1) W(X+2) W513 W514 W(1024–X) W(1025–X) W1024 W1025 OR AF/AE HF IR Figure 4. Read Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN MAX 4.5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –8 mA IOL TA Low-level output current 16 mA 125 °C High-level input voltage 2 Operating free-air temperature – 55 V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL VCC = 4.5 V, VCC = 4.5 V, IOH = – 8 mA IOL = 16 mA II IOZ VCC = 5.5 V, VCC = 5.5 V, VI = VCC or 0 V VO = VCC or 0 V ICC§ VI = VCC – 0.2 V or 0 V One input at 3.4 V, Ci Co VI = 0 V, VO = 0 V, TYP‡ MAX 2.4 UNIT V Other inputs at VCC or GND 0.5 V ±5 µA ±5 µA 400 µA 1 mA f = 1 MHz 4 pF f = 1 MHz 8 pF ‡ All typical values are at VCC = 5 V, TA = 25°C. § ICC tested with outputs open 10 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 timing requirements (see Figures 1 through 8) MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time 28.5 Data in (D0 – D17) high or low 14 WRTCLK high 10 WRTCLK low 14 RDCLK high 10 RDCLK low 14 DAF high 10 WRTEN1, WRTEN2 high or low 10 OE, RDEN1, RDEN2 high or low 10 Data in (D0 – D17) before WRTCLK↑ 5 WRTEN1, WRTEN2 high before WRTCLK↑ 5 OE, RDEN1, RDEN2 high before RDCLK↑ 5 Reset: RESET low before first WRTCLK and RDCLK↑† 7 Define AF/AE: D0 – D8 before DAF↓ 5 Define AF/AE: DAF↓ before RESET↑ 7 Define AF/AE (default): DAF high before RESET↑ 5 Data in (D0 – D17) after WRTCLK↑ 1 WRTEN1, WRTEN2 high after WRTCLK↑ 1 OE, RDEN1, RDEN2 high after RDCLK↑ 1 Reset: RESET low after fourth WRTCLK and RDCLK↑† 0 Define AF/AE: D0 – D8 after DAF↓ 1 Define AF/AE: DAF low after RESET↑ 0 Define AF/AE (default): DAF high after RESET↑ 1 MAX UNIT MHz ns ns ns † To permit the clock pulse to be utilized for reset purposes POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 switching characteristics over recommended operating free-air temperature range (see Figures 9 and 10) PARAMETER FROM (INPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = – 55°C to 125°C TO (OUTPUT) MIN fmax tpd tpd† tpd tpd tpd d tPLH tPHL tPLH tPHL ten tdis WRTCLK or RDCLK RDCLK↑ MAX 28.5 Any Q UNIT MHz 3 20 ns WRTCLK↑ IR 1 14 ns RDCLK↑ OR 1 14 ns 5 24 5 24 5 23 5 23 AF/AE 2 23 HF 3 25 1 11 1 14 WRTCLK↑ AF/AE RDCLK↑ WRTCLK↑ HF RDCLK↑ RESET↓ OE Any Q ns ns ns ns † This parameter is measured with CL = 30 pF (see Figure 5). operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 12 TEST CONDITIONS Power dissipation capacitance per 1K bits POST OFFICE BOX 655303 CL = 50 pF, • DALLAS, TEXAS 75265 f = 5 MHz TYP UNIT 65 pF SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 TYPICAL CHARACTERISTICS Figure 2Figure 3Figure 4 TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE TYPICAL POWER DISSIPATION CAPACITANCE vs SUPPLY VOLTAGE 18 pd – Power Dissipation Capacitance – pF 17 t pd – Propagation Delay Time – ns 68 VCC = 5 V TA = 25°C RL = 500 Ω 16 15 14 13 12 11 10 fi = 5 MHz TA = 25°C CL = 50 pF 67 66 65 64 63 62 0 50 100 150 200 250 300 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 VCC – Supply Voltage – V C L – Load Capacitance – pF Figure 5 Figure 6 calculating power dissipation The maximum power dissipation (PT) of the SN54ACT7811 can be calculated by: PT = VCC × [ICC + (N × ∆ICC × dc)] + Σ (Cpd × VCC2 × fi) + Σ (CL × VCC2 × fo) Where: ICC N ∆ ICC dc Cpd CL fi fo = = = = = = = = power-down ICC maximum number of inputs driven by a TTL device increase in supply current duty cycle of inputs at a TTL high level of 3.4 V power dissipation capacitance output capacitive load data input frequency data output frequency POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 APPLICATION INFORMATION expanding the SN54ACT7811 The SN54ACT7811 is expandable in width and depth. Expanding in word depth offers special timing considerations: – After the first data word is loaded into the FIFO, the word is unloaded, and the OR output goes high after (N × 3) RDCLK cycles, where N is the number of devices used in depth expansion. – After the FIFO is filled, the IR output goes low, the first word is unloaded, and the IR is driven high after (N × 2) write clock cycles, where N is the number of devices used in depth expansion. CLOCK WRTCLK SN54ACT7811 WRTCLK RDCLK SN54ACT7811 WRTCLK RDCLK RDCLK WRTEN1 WRTEN1 OR WRTEN1 RDEN1 RDEN1 WRTEN2 WRTEN2 RDEN1 WRTEN2 RDEN2 RDEN2 IR RDEN2 IR OE D0 – D17 D0 – D17 IR 5V Q0 – Q17 D0 – D17 OR OR OE OE Q0 – Q17 Q0 – Q17 Figure 7. Word-Depth Expansion: 2048 Words × 18 Bits, N = 2 WRTCLK WRTEN SN54ACT7811 RDCLK WRTCLK WRTEN1 RDEN1 WRTEN2 RDEN2 IR D0 – D17 RDEN OR OE D18 – D35 RDCLK Q0 – Q17 IR OE Q18 – Q35 OR SN54ACT7811 RDCLK WRTCLK WRTEN1 RDEN1 WRTEN2 RDEN2 IR OR OE D0 – D17 D0 – D17 Q0 – Q17 Figure 8. Word-Width Expansion: 1024 Words × 36 Bits 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 – Q17 SN54ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996 PARAMETER MEASUREMENT INFORMATION 3V Input From Output Under Test 1.5 V 0V RL = 500 Ω tpd CL = 50 pF tpd 3V 1.5 V Output 0V TOTEM-POLE OUTPUTS LOAD CIRCUIT Figure 9. Standard CMOS Outputs 3V 7V 1.5 V Input 1.5 V 0V RL = R1 = R2 tPZL S1 tPLZ R1 From Output Under Test ≈ 3.5 V Test Point CL 1.5 V Output R2 VOL 0.3 V tPHZ tPZH VOH Output 1.5 V 0.3 V ≈0V LOAD CIRCUIT VOLTAGE WAVEFORMS PARAMETER R1, R2 CL† ten tPZH tPZL 500 Ω 50 pF tdi dis tPHZ tPLZ 500 Ω 50 pF S1 Open Closed Open Closed tpd 500 Ω 50 pF Open † Includes probe and test fixture capacitanceFigure 9 Figure 10. 3-State Outputs (Any Q) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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