SN74LVC07A-EP www.ti.com .................................................................................................................................................. SCAS738D – DECEMBER 2003 – REVISED JUNE 2008 HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS FEATURES 1 • • • • Operates From 1.65 V to 5 V Inputs and Open-Drain Outputs Accept Voltages up to 5.5 V Max tpd of 3.6 ns at 5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 PW PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C), Industrial (–40°C/85°C) Temperature Ranges (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability 1 14 2 13 3 12 4 11 5 10 6 7 9 8 VCC 6A 6Y 5A 5Y 4A 4Y Custom Temperature Ranges Available DESCRIPTION/ORDERING INFORMATION This hex buffer/driver is designed for 1.65-V to 5.5-V VCC operation. The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA. Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of this device as a translator in a mixed-system environment. ORDERING INFORMATION PACKAGE (1) TA ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C TSSOP – PW Reel of 2000 SN74LVC07AIPWREP C07AEP –55°C to 125°C TSSOP – PW Reel of 2000 SN74LVC07AMPWREP C07AMEP (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each buffer/driver) INPUT A OUTPUT Y H H L L 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2008, Texas Instruments Incorporated SN74LVC07A-EP SCAS738D – DECEMBER 2003 – REVISED JUNE 2008 .................................................................................................................................................. www.ti.com LOGIC DIAGRAM, EACH BUFFER/DRIVER (POSITIVE LOGIC) A Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Output voltage range –0.5 6.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 113 °C/W 150 °C Continuous current through each VCC or GND θJA Package thermal impedance Tstg Storage temperature range (1) (2) (3) (3) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 5.5 Low-level input voltage V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC =2.7 V to 3.6 V 2 VCC = 4.5 V to 5.5 V 0.7 × VCC VCC = 1.65 V to 1.95 V VIL UNIT V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V 0.3 × VCC V VI Input voltage 0 5.5 V VO Output voltage 0 5.5 V IOL Low-level output current VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 VCC = 4.5 V TA (1) 2 Operating free-air temperature mA 24 SN74LVC07AIPWREP –40 85 SN74LVC07AMPWREP –55 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC07A-EP SN74LVC07A-EP www.ti.com .................................................................................................................................................. SCAS738D – DECEMBER 2003 – REVISED JUNE 2008 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOL = 100 µA 0.2 1.65 V 0.45 2.3 V 0.7 2.7 V 0.4 3V 0.55 IOL = 12 mA IOL = 24 mA II VI = 5.5 V or GND ICC VI = VCC or GND, ΔICC CI (1) UNIT V 3.6 V ±5 µA 3.6 V 10 µA 2.7 V to 3.6 V 500 µA IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND MAX 1.65 V to 5.5 V IOL = 4 mA VOL TYP (1) MIN VI = VCC or GND 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through 4) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX 1 6.6 MIN MAX 1 4.4 VCC = 3.3 V ±0.3 V VCC = 2.7 V MIN VCC = 5 V ±0.5 V MAX MIN MAX MIN MAX 4.3 1 4.6 1 3.6 UNIT ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 1.8 2 2.5 3.78 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC07A-EP UNIT pF 3 SN74LVC07A-EP SCAS738D – DECEMBER 2003 – REVISED JUNE 2008 .................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST S1 tPZL (see Note F) 2 × VCC tPLZ (see Note G) 2 × VCC tPHZ/tPZH 2 × VCC GND CL = 30 pF (see Note A) 1 kΩ LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VCC VCC/2 VOL Output Waveform 2 S1 at 2 × VCC (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VOL + 0.15 V VOL tPHZ VCC/2 VCC VCC − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.15 V. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC07A-EP SN74LVC07A-EP www.ti.com .................................................................................................................................................. SCAS738D – DECEMBER 2003 – REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST S1 tPZL (see Note F) 2 × VCC tPLZ (see Note G) 2 × VCC tPHZ/tPZH 2 × VCC GND CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VCC VCC/2 VOL VOL + 0.15 V VOL tPHZ Output Waveform 2 S1 at 2 × VCC (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VCC VCC − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.15 V. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC07A-EP 5 SN74LVC07A-EP SCAS738D – DECEMBER 2003 – REVISED JUNE 2008 .................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPZL (see Note F) 6V tPLZ (see Note G) 6V tPHZ/tPZH 6V LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 0V 0V 2.7 V 1.5 V 1.5 V 0V 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) tPLZ 3V 1.5 V tPZH 3V 1.5 V VOL 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 2.7 V 1.5 V tPZL 2.7 V Output VOLTAGE WAVEFORMS PULSE DURATION th VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V tsu Data Input 1.5 V Input Output Waveform 2 S1 at 6 V (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ 3V 1.5 V 2.7 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at 1.5 V. G. tPLZ is measured at VOL + 0.3 V. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC07A-EP SN74LVC07A-EP www.ti.com .................................................................................................................................................. SCAS738D – DECEMBER 2003 – REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION VCC = 5 V ± 0.5 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPZL (see Note F) 2 × VCC tPLZ (see Note G) 2 × VCC tPHZ/tPZH 7V LOAD CIRCUIT tw 3V 3V Timing Input 0V 0V 3V 1.5 V 1.5 V 0V 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH 3.5 V 1.5 V VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL 1.5 V VCC VCC/2 tPZL 3V Output VOLTAGE WAVEFORMS PULSE DURATION th VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V tsu Data Input 1.5 V Input VOL tPHZ Output Waveform 2 S1 at 7 V (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V 3.5 V 1.5 V 3.2 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.3 V. H. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC07A-EP 7 PACKAGE OPTION ADDENDUM www.ti.com 21-Jul-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC07AIPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC07AMPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04654-01XE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04654-02XE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC07AIPWREP Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 7.0 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC07AIPWREP TSSOP PW 14 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 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