SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 • FEATURES • • • • • Member of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCC Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) Latch-Up Performance Exceeds 250 mA Per JESD 78 Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages • • • • DESCRIPTION A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009. 3.2 TA = 25°C Process = Nominal - Output Voltage - V 2.8 2.4 VCC = 3.3 V 2.0 1.6 VCC = 2.5 V 1.2 OH VCC = 1.8 V 0.8 V VOL - Output Voltage - V 2.8 TA = 25°C Process = Nominal 2.4 2.0 1.6 1.2 0.8 VCC = 3.3 V 0.4 0.4 0 17 34 51 68 85 102 119 IOL - Output Current - mA 136 153 170 VCC = 2.5 V VCC = 1.8 V -160 -144 -128 -112 -96 -80 -64 -48 IOH - Output Current - mA -32 -16 0 Figure 1. Output Voltage vs Output Current This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC, DOC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2005, Texas Instruments Incorporated SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 DESCRIPTION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16245 is characterized for operation from –40°C to 85°C. TERMINAL ASSIGNMENTS DGG OR DGV PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE FUNCTION TABLE (EACH 8-BIT TRANSCEIVER) INPUTS OE DIR 2 OPERATION L L B data to A bus L H A data to B bus H X Isolation SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 LOGIC SYMBOL(1) 48 1OE 1DIR G3 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR G6 24 6 EN4 [BA] 6 EN5 [AB] 1A1 47 2 1 1B1 2 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 5 2A2 2A3 2A4 2A5 2A6 2A7 2A8 (1) 35 14 33 16 32 17 30 19 29 20 27 22 26 23 2B2 2B3 2B4 2B5 2B6 2B7 2B8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 To Seven Other Channels 24 2OE 36 13 1B1 2B1 To Seven Other Channels 3 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V VO Voltage range applied to any input/output when the output is in the high-impedance or power-off state (2) –0.5 4.6 V VO Voltage range applied to any input/output when the output is in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 4 DGG package 70 DGV package 58 –65 150 UNIT °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. The package thermal impedance is calculated in accordance with JESD 51. SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 Recommended Operating Conditions VCC Supply voltage (1) MIN MAX Operating 1.4 3.6 Data retention only 1.2 VCC = 1.2 V VIH High-level input voltage 0.65 × VCC VCC = 1.65 V to 1.95 V 0.65 × VCC VCC = 3 V to 3.6 V Low-level input voltage 2 GND VCC = 1.4 V to 1.6 V 0.35 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V Input voltage VO Output voltage IOHS Static high-level output current (2) 0.8 0 3.6 Active state 0 VCC 3-state 0 3.6 VCC = 1.4 V to 1.6 V –2 VCC = 1.65 V to 1.95 V –4 VCC = 2.3 V to 2.7 V –8 VCC = 3 V to 3.6 V Static low-level output current (2) IOLS Input transition rise or fall rate TA Operating free-air temperature (1) (2) V V mA –12 VCC = 1.4 V to 1.6 V 2 VCC = 1.65 V to 1.95 V 4 VCC = 2.3 V to 2.7 V 8 VCC = 3 V to 3.6 V ∆t/∆v V 0.7 VCC = 3 V to 3.6 V VI V 1.7 VCC = 1.2 V VIL V VCC VCC = 1.4 V to 1.6 V VCC = 2.3 V to 2.7 V UNIT mA 12 VCC = 1.4 V to 3.6 V –40 5 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009. 5 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOHS = –100 µA VOH 1.4 V to 3.6 V II Control inputs Ioff IOZ (2) ICC VIH = 0.91 V 1.4 V IOHS = –4 mA, VIH = 1.07 V 1.65 V 1.2 IOHS = –8 mA, VIH = 1.7 V 2.3 V 1.75 IOHS = –12 mA, VIH = 2 V 3V 2.3 UNIT 1.05 V 1.4 V to 3.6 V 0.2 IOLS = 2 mA, VIL = 0.49 V 1.4 V 0.4 IOLS = 4 mA, VIL = 0.57 V 1.65 V 0.45 IOLS = 8 mA, VIL = 0.7 V 2.3 V 0.55 IOLS = 12 mA, VIL = 0.8 V 3V 0.7 VI = VCC or GND 3.6 V ±2.5 µA VI or VO = 3.6 V 0 ±10 µA V VO = VCC or GND, VI (OE) = VCC 3.6 V ±12.5 µA VI = VCC or GND, IO = 0 3.6 V 40 µA Ci Control inputs VI = VCC or GND Cio A or B ports VO = VCC or GND (1) (2) MAX VCC – 0.2 IOHS = –2 mA, IOLS = 100 µA VOL MIN TYP (1) VCC 2.5 V 3 3.3 V 3 2.5 V 9 3.3 V 9 pF pF Typical values are measured at TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5) VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) VCC = 1.2 V TYP MIN MAX MIN MAX MIN MAX MIN MAX tpd A or B B or A 3.9 0.8 4 0.7 3 0.6 1.9 0.5 1.7 ns ten OE A or B 8.4 1.5 9.2 1.4 7 1 4.3 0.7 3.7 ns tdis OE A or B 8.4 2.3 9.3 2.2 7 1.1 4 1.2 3.9 ns PARAMETER UNIT Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 0, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 35 38 44 6 6 7 UNIT pF SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V ± 0.1 V 2 × VCC S1 2 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 2 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.1 V VOL tPHZ VOH VCC/2 VOH − 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 7 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 1 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 8 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 Ω S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 9 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES142L – JULY 1998 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test GND CL = 30 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open 500 Ω tw LOAD CIRCUIT VCC VCC Timing Input VCC/2 Input VCC/2 0V VCC/2 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC Output Control (low-level enabling) VCC/2 VCC/2 0V tPZL VCC Input VCC/2 VCC/2 0V tPLH tPHL VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC VCC/2 VOL + 0.3 V VOL tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ Output Waveform 2 S1 at GND (see Note B) tPHZ VCC/2 VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms 10 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74AVC16245DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AVC16245DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AVC16245DGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVC16245DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AVC16245DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AVC16245DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74AVC16245DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AVC16245DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74AVC16245DGVR TVSOP DGV 48 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. 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