ETC PD64012

PD64012
12-channel PoE Manager
Preliminary Datasheet
Description __________________
Features ____________________
PowerDsine’s™ PD64012 Power over Ethernet
(PoE) Manager chip integrates power, analog and
logic functions into a single 64-pin, plastic pack. It is
used in Ethernet switches and Midspans to allow next
generation network devices to share power and data
over the same cable.
♦
IEEE 802.3af-2003 compliant
♦
Drives 12 independent power ports
♦
Can be cascaded for up to 48 ports, using a
master/slave architecture
♦
Supports IETF Power Ethernet MIB (RFC 3621)
The device is a twelve-port, mix-signal, high-voltage
Power over Ethernet driver. The PoE Manager allows
the detection of IEEE 802.3af-2003 compliant
terminals, referred to as powered devices or PDs,
ensuring safe power feeding and removal over
Ethernet ports. With full digital control via a serial
communication interface and a minimum of external
components, the device integrates in multi-port and
highly populated Ethernet switches.
♦
Thermal protection per port
♦
Thermal monitoring capabilities
♦
Multi-point resistor detection
♦
Supports DC modulation method under-current
detection according to IEEE 802.3af-2003
♦
AC & DC disconnect functions
♦
PD classification function
♦
Operates from single input (44 to 57 V)
♦
I2C bus interface
♦
Supports foldback current limiting
♦
Digitally programmable overcurrent protection
per port
♦
Digitally programmable timers
The PD64012 implements all real time functions
according to IEEE 802.3af-2003, including: detection,
classification, and port status monitoring; as well as
system level activities such as: power management
and MIB support, for system management. The PoE
Manager is designed to detect and disable
disconnected ports, using both DC and AC
disconnect methods, as defined in IEEE 802.3af2003.
The
PD64012
has
two
possible
working
configurations: an Auto mode (stand-alone topology)
for basic PoE functions and an Enhanced mode for
extended functions.
VPORT_NEG5
PORT_SENSE5
AGND
VPORT_NEG4
PORT_SENSE4
Reserved
49
50
51
52
53
54
PORT_SENSE2
VPORT_NEG3
55
VPORT_NEG2
PORT_SENSE1
VPORT_NEG1
PORT_SENSE0
VPORT_NEG0
SENSE_NEG
PORT_SENSE3
56
57
58
59
60
61
62
63
64
Reserved
Pin Configuration _____________
VPORT_POS0
1
48
VPERI
VPORT_POS1
2
47
EXT_REG
VPORT_POS2
3
46
ADC2p5
VPORT_POS3
4
45
QGND
44
I2CINI
VCC2p5
PD64012
VPORT_POS4
5
VPORT_POS5
6
43
VPORT_POS6
7
42
ASICINI
VPORT_POS7
8
41
VPORT_POS8
9
40
IREF
RESET_N
VPORT_POS9
10
39
SDA
VPORT_POS10
11
38
SCL
VPORT_POS11
12
37
SCK
VMAIN
13
36
MOSI
CP_IN
14
35
MISO
CP_OUT
15
34
CS0_N
REF_PORT_NEG
16
33
DGND
04202AL1W07
CS1_N
VPORT_NEG6
DISABLE_PORTS
PORT_SENSE6
VPORT_NEG7
PORT_SENSE7
VPORT_NEG8
PORT_SENSE8
PORT_SENSE9
VPORT_NEG9
PORT_SENSE10
VPORT_NEG10
PORT_SENSE11
AGND
VPORT_NEG11
TEST_MODE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PowerDsine
♦
Power management algorithm for up to 48 ports
♦
Internal power-on reset
♦
Power soft-start algorithm
♦
Fast power shutdown, in case of power
supply failure
♦
Automatic on/off sequencer for up to 48 ports
♦
Disable/enable power feeding
♦
Continuous port current monitoring
♦
Supports back-off feature for Midspan
implementation
♦
Additional features for Enhanced mode:
•
•
•
•
•
UART interface
Pre-standard PD detection
Supports non-standard terminals
Advanced power management
Programmable port matrix
Ordering Information
PART
PD64012
TEMP. RANGE
-20 to +85 °C
PIN PACKAGE
LQFP-64
Date code: see the bottom line (04202AL1W07) in
the Pin Configuration drawing. “0420” is the date
code. “04” the year (2004), while “20” is the week.
The Power over Ethernet Pioneers
This document contains information that is proprietary to PowerDsine. As such, it is confidential and its disclosure is strictly prohibited by applicable law. If you and/or your company and PowerDsine
have executed a Non-Disclosure Agreement, then this document is being provided in connection with the Agreement, and the information contained herein is covered by the Agreement and under its
terms may not be disclosed or used and must be protected by you and/or your company.
PD64012
12-CHANNEL PoE MANAGER
Maximum Ratings ______________________________________________
Vmain………………………………………………… -0.3 to 80 V(1)
DGND, AGND, QGND, SENSE_NEG…………..-0.3 to 0.3 V(2)
MISO, MOSI, SCK, SCL, SDA,
CLK, RESETN, CS0_N, CS1_N….………... -0.3 to (VPERI + 0.3) V
VPORT_POSx ………………………………..……
VPORT_NEGx, REF_PORT_NEG
VPORT_POSx - VPORT_NEGx
ESD (Human Body Model)…………….….… -2 to 2 kV(3)
Max junction temperature (Tjunc)…………..…+150 °C
Junction-ambient thermal resistance (θJA)….. 25 °C/W
Junction-case thermal resistance (θJC)………16 °C/W
Lead temperature (soldering, 10 s)…………. 300 °C
Storage temperature…………………………..-40 to +125 °C
-0.3 to 80 V(1)
PORT_SENSEx…………………………..……… -0.3 to 15 V
VCC2p5, ADC2p5………….………………………... -0.3 to 3 V
VPERI……………………………..…………………. 4 V
EXT_REG……………………………………..…… -0.3 to 6 V
I2CINI, ASICINI…………………………………… -0.3 to 3 V
.
Notes: “x” defines port numbers, 0 thru 11, inclusive.
(1) 80 V is the transient voltage that can be applied for at most one minute.
(2) Maximum value between grounds.
(3) ESD testing is performed in accordance with the Human Body Model (CZap = 100 pF, RZap = 1500 Ω).
Stresses beyond those listed above, may cause permanent damage to the device. Exposure to absolute maximum rating conditions for
extended periods, may affect device reliability.
Operating Conditions ___________________________________________
PARAMETER
Operating temperature
Operational limitations (1)
(1)
MIN.
-20
15 to 44
NOM.
MAX.
UNIT
°C
V
+85
55 to 57
44 to 55
Operating functions depend on the input voltage, as shown in the distribution of Figure 1.
AC Disconnect
(only up to 55 V)
PoL 802.3af Compliance
(from 44 to 57 V)
Communications (operates over entire range)
15
44
55
57 V
Figure 1 - Operational Ranges
Electrical Characteristics ________________________________________
DC Characteristics for Digital Inputs and Outputs
PARAMETER
Pin Name
Type
High level input voltage
Low level input voltage
Input voltage hysteresis
Input high current
Input low current
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06-0003-058 (Rev. 2.8) / 5 August 2004
SYMBOL
MIN.
MAX.
UNIT
DISABLE_PORTS
Schmitt Trigger CMOS input, TTL level with internal pullup
VIH
2.0
V
VIL
0.8
V
0.3
V
IIH
+10
+150
µA
IIL
NA
NA
µA
2
REMARKS
© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
DC Characteristics for Digital Inputs and Outputs (continued)
PARAMETER
Pin Name
Type
High level input voltage
Low level input voltage
Input voltage hysteresis
Input high current
Input low current
Pin Name
Type
High level input voltage
Low level input voltage
Input voltage hysteresis
Input high current
Input low current
High level output voltage
Low level output voltage
Tri state output current
Pin Name
Type
High level input voltage
Low level input voltage
Input voltage hysteresis
OFF state output current
SYMBOL
MIN.
MAX.
UNIT
SCL
Schmitt Trigger CMOS input, TTL level with internal pullup
VIH
2.0
V
VIL
0.8
V
0.3
V
IIH
NA
NA
µA
IIL
-150
-10
µA
MOSI, MISO, CS0_N, CS1_N, SCK
CMOS I/O, TTL level with no internal pull up/pull down resistor
VIH
2.0
V
VIL
0.8
V
0.3
V
IIH
-1
+1
µA
IIL
-1
+1
µA
VPERI-0.4V
V
Iout = 3 mA
0.4
V
Iout = 3 mA
-1
+1
µA
RESET_N, SDA
CMOS open drain output with Schmitt Trigger input, TTL level
0.4
V
Iout = 3mA
VIL
0.8
V
0.3
V
-1
+1
µA
REMARKS
Electrical Characteristics for Analog I/O Pads
PARAMETER
Pin Name
Operating voltage
Pin current consumption
Pin Name
Operating voltage
Internal current consumption
Pin Name
Operating voltage
Vmain current consumption
Pin Name
Operating voltage
Pin current consumption
Pin Name
ADC2p5 output voltage
ADC2p5 internal current
consumption
VCC2p5 output voltage
VCC2p5 internal current
consumption
VPERI output voltage
VPERI external current load
EXT_REG output current
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06-0003-058 (Rev. 2.8) / 5 August 2004
MIN.
MAX.
UNIT
REMARKS
VPORT_POSx, VPORT_NEGx, REF_PORT_NEG
44
62
V
Port driver off, Vport differential measurement off, AC
-5
+5
µA
generator off
PORT_SENSEx
With external 2 ohms (1%) to ground
0
1.48
V
20
µA
VMAIN
44
57
V
Total on Vmain
20
mA
CP out
44
67
V
5
mA
ADC2p5, VCC2p5, VPERI, EXT_REG
2.45
2.55
V
6
mA
Recommended external cap. = 47 to 135 nF
2.37
2.62
5
V
mA
Recommended external cap. = 47 to 135 nF
3.13
3.46
6
V
mA
Recommended external cap. = 1 to 4.7 µF
Without external NPN
6
mA
When using external NPN for VPERI
3
© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
Electrical Characteristics for Analog I/O Pads (continued)
PARAMETER
Pin Name
Operating voltage
Current consumption
Pin Name
Output voltage
MIN.
MAX.
ASICINI, I2CINI
0
ADC2p5
-1
+1
IREF
1.21
1.34
UNIT
REMARKS
V
µA
V
With external 24.9 kΩ resistor to ground
Dynamic Characteristics
The PD64012 is an advanced power-limiting device that uses three programmable current level thresholds (Imin, Icut,
Ilim) and two timers (Tmin, Tcut ), to operate as shown in Figure 2. Loads that dissipate more than Icut for longer than
Tcut (OVL_S to OVL) are classified as overloads and are automatically shutdown. Output power dissipation below
Imin for during more than Tmin (UDL_S to UDL) will be classified as no-load and will also be shutdown. Automatic
recovery from overload and no-load conditions are attempted every TOVLREC and TUDLREC periods (typically 5 and 1
seconds, respectively). In any case, output power is limited to Ilim, which is a maximum peak power allowed at the
port.
PARAMETER
Automatic recovery from
overload shutdown
Automatic recovery from
no-load shutdown
Cutoff timers accuracy
Inrush current
Output current
operating range
Output power available,
operating range
Off mode current
CONDITIONS
TOVLREC value, measured from port shutdown
(can be modified through control port)
TUDLREC value, measured from port shutdown
(can be modified through control port)
Typical accuracy of Tcut
IInrsh
Iport
Pport
Imin1
Imin2
PD power maintenance
request drop-out time
limit
Over load current
detection range
Over load time limit
Turn on rise time
TPMDO
TOVL
Trise
Turn off time
Toff
Icut
For t=50 ms, Cload=180 uF max.
Continuous operation after
startup period.
Continuous operation after
startup period, at port output.
Must disconnect for t greater than
TUVL
May or may not disconnect for t
greater than TUVL
Buffer period to handle
transitions
Time limited to TOVL
From 10% to 90% of Vport
(specified for PD load consisting
of 100 uF capacitor in parallel to
200 Ω).
From Vport to 5 Vdc
MIN.
TYP.
MAX.
UNIT
5
s
1
s
10
ms
400
10
450
350
mA
mA
0.57
15.4
W
0
5
mA
10
mA
300
400
ms
350
400
mA
50
15
75
ms
us
500
ms
5
7.5
Thermal Data
Power consumption – the internal power consumption of a single device from the DC input is based on:
Input voltage range………… 44 to 57 VDC
Input current………………… 10 mA typ.; 15 mA max.
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© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
Pmain = Vmain x I main
Pmain typ. = 48 VDC x 10 mA = 0.480 W.
Pmain max. = 57 VDC x 15 mA = 0.855 W
Device Power Dissipation – the PD64012 incorporates 12 power MOSFETs, each characterized by:
Resistance from drain-source Rds(on) = 0.3 Ω typ. ; 0.5 Ω max.
Drain-source current Ids = 360 mA max.
Maximum power dissipation PMOSFET max. of a single PD64012 device (for 12 MOSFETs) :
[(Ids)2 x Rds(on)] x 12 = [(0.36 A)2 x 0.5 Ω] x 12 = 0.78 W
Charge pump (see Analog Section of Block Diagram Description, hereafter) power dissipation PCP is 0.21 W.
Total power dissipation Ptotal by device, under maximum conditions:
Ptotal = Pmain max. + PMOSFET max. + PCP = 0.855 W + 0.78 W + 0.21 W = 1.845 W
Tcut
OVL_S
Ilim
Icut
OVL
Ichannel
Port 1
Port 2
UDL_S
UDL
Imin
Port off
Tmin
Figure 2: Power Limits
Protection Mechanism
The PD64012 includes internal thermal protection to avoid junction overheat. Three types of temperature sensors
are integrated into the device: two are used for protection and one for temperature monitoring.
Hi-temp protection – the device contains thermal shutdowns. This protection system is activated in extreme
conditions.
Lo-temp protection – there are thermal sensors that are intended to protect the functionality of the device, in
cases of temperature rise.
Indicator sensors – four temperature sensors monitor the local temperature in the device. Their average is also
calculated by the PD64012. All values are stored in internal registers for data retrieval. The register values are
calculated by:
Decimal value = 684 - 1.514 x [(Tjunc)+ 40 °C].
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© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
Pins Descriptions ______________________________________________
PIN
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
PIN NAME
VPORT_POS0
VPORT_POS1
VPORT_POS2
VPORT_POS3
VPORT_POS4
VPORT_POS5
VPORT_POS6
VPORT_POS7
VPORT_POS8
VPORT_POS9
VPORT_POS10
VPORT_POS11
Vmain
CP_IN
CP_OUT
REF_PORT_NEG
TEST_MODE
VPORT_NEG11
AGND
PORT_SENSE11
VPORT_NEG10
PORT_SENSE10
VPORT_NEG9
PORT_SENSE9
PORT_SENSE8
VPORT_NEG8
PORT_SENSE7
VPORT_NEG7
PORT_SENSE6
PIN TYPE
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Supply
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Supply
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
DISABLE_PORTS_N Digital input
VPORT_NEG6
Analog I/O
CS1_N
Digital I/O
DGND
Supply
CS0_N
Digital I/O
MISO
Digital I/O
MOSI
Digital I/O
SCK
Digital input
SCL
Digital input
SDA
Digital I/O
RESET_N
Digital I/O
IREF
Analog I/O
ASICINI
Analog input
VCC2p5
Supply
I2CINI
Analog input
QGND
Supply
ADC2p5
Supply
EXT_REG
Analog out
VPERI
Analog out
Reserved
Digital input
VPORT_NEG5
Analog I/O
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06-0003-058 (Rev. 2.8) / 5 August 2004
PIN DESCRIPTION
Port 0 positive voltage feeding
Port 1 positive voltage feeding
Port 2 positive voltage feeding
Port 3 positive voltage feeding
Port 4 positive voltage feeding
Port 5 positive voltage feeding
Port 6 positive voltage feeding
Port 7 positive voltage feeding
Port 8 positive voltage feeding
Port 9 positive voltage feeding
Port 10 positive voltage feeding
Port 11 positive voltage feeding
Main Voltage supply
Charge Pump input, 48V+5V
Charge Pump Pulse Output
Port negative reference
Test Mode Pin (connect to ground)
Port 11 negative voltage feeding
Analog ground
Channel current monitoring
Port 10 negative voltage feeding
Channel current monitoring
Port 9 negative voltage feeding
Channel current monitoring
Channel current monitoring
Port 8 negative voltage feeding
Channel current monitoring
Port 7 negative voltage feeding
Channel current monitoring
Disable all ports power (active low)
Port 6 negative voltage feeding
SPI bus, Chip Select 1
Digital ground
SPI bus, Chip Select 0
SPI bus, Master in/slave out
SPI bus, Master out/slave in
SPI bus, Serial clock I/O
I2C bus, Serial Clock Input
I2C bus, open drain
Active Low Reset I/O
Current reference
Analog input for ASIC initialization
Internal 2.5 V supply (do not use!)
Analog input for I2C initialization
Quiet analog ground
ADC reference (do not use!)
External regulation
Regulated 3.3 V power source
(Connect to ground)
Port 5 negative voltage feeding
6
© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
PIN
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
PIN NAME
AGND
PORT_SENSE5
VPORT_NEG4
PORT_SENSE4
VPORT_NEG3
PORT_SENSE3
PORT_SENSE2
VPORT_NEG2
PORT_SENSE1
VPORT_NEG1
PORT_SENSE0
SENSE_NEG
VPORT_NEG0
Reserved
PIN TYPE
Supply
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Analog I/O
TBD
PIN DESCRIPTION
Analog ground
Channel current monitoring
Port 4 negative voltage feeding
Channel current monitoring
Port 3 negative voltage feeding
Channel current monitoring
Channel current monitoring
Port 2 negative voltage feeding
Channel current monitoring
Port 1 negative voltage feeding
Channel current monitoring
Port sense reference
Port 0 negative voltage feeding
Not connected
Functional Description ________
Operational Modes
The PD64012 supports two main modes of operation,
based on two different architectures, as described
hereafter. The two modes are: Enhanced mode and
Automatic mode.
MOSI
MISO
SCK
I/O Opto
Host
CPU
SPI Bus
I2C or UART
Enhanced mode – in this mode of operation, the
PD64012s communicate with the PD63000 PoE
MCU (dedicated MCU for Power over Ethernet
tasks), through a Serial Parallel Interface (SPI) bus.
In this mode, all PD64012s are directly connected to
the PD63000 through the SPI, in slave mode. The
MCU is used for additional Power over Ethernet
features, such as:
PD63000
PoE MCU
PD64012
#00
CS0_N
CS1_N
CS0
CS1
CS2
CS3
PD64012
#01
CS0_N
CS1_N
PD64012
#10
CS0_N
CS1_N
♦ Legacy PDs detection (including Cisco discovery)
PD64012
#11
♦ Enhanced power management algorithms
♦ LED indicators support
CS0_N
CS1_N
♦ Port matrix control
Pull-down
resistor
♦ Communication protocol translator.
Figure 3: Enhanced Mode
The switch host CPU communicates with the
PD63000, via an isolated I2C or UART bus, as shown
in Figure 3.
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© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
Automatic mode – in this mode the PD64012 PoE
Managers communicate with the host CPU, through
an isolated I2C bus. The PD64012 SPI bus is
dedicated for internal communication among
PD64012s (for power management), as illustrated in
Figure 4.
I/O Opto
I2C BUS
SDA
HOST
CPU
SPI BUS
SDA
CS[0:1]_N
PD64012
#00
Input Opto
SCL
SCK
MOSI
Master MISO
SCL
SDA
Anyone of the devices (for example, PD64012 #00)
may be configured as Master, while the others are
Slaves. This Master/Slave configuration only affects
the Serial Peripheral Interface (SPI) bus. It is critical
that only one of them be set-up as a Master, with the
others acting as Slaves, in order to avoid SPI clock
and data I/Os contentions.
SCL
SCK
PD64012
#01
Slave
MOSI
MISO
SDA
SCL
SCK
PD64012
#10
Slave
MOSI
MISO
SDA
SCL
SCK
PD64012
#11
Slave
MOSI
MISO
Figure 4: Automatic Mode
Mode Configuration Method
The PoE Manager’s configuration is done via the ASIC_INI pin, according to the following table.
The ASIC_INI analog signal is converted into a 10-bit register (A/D). Once a hard Reset pulse is detected, the data
is latched into an internal mode register.
MODE NAME
ASIC_INI
VOLTAGE LEVEL
I2C 2 LSB ADDRESS
(set internally)
ASIC_INI INTERNAL A/D
REGISTER
Enhanced mode
0.31 to 0.63 V
001
00
Auto mode – Slave 1
0.63 to 0.94 V
010
01
Auto mode – Slave 2
0.94 to 1.25 V
011
10
Auto mode – Slave 3
1.25 to 1.56 V
100
11
Auto mode - Master
2.19 to 2.5 V
111
00
Notes:
2
In the Auto mode – the PD64012 is communicating with the host via I C.
In the Enhanced mode – the PD64012 is communicating with the controller via SPI.
Block Diagram Description (see Figure 5)
The PD64002 PoE Manager complies with all requirements of IEEE standard 802.3af-2003, for detection. The
device has been designed around two major sections:
1. A common Digital section, that serves all 12 channels
2. Twelve separate and identical channels for driving ports.
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06-0003-058 (Rev. 2.8) / 5 August 2004
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© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
+ 48V
V M A IN
C lo c k
O s c illa to r
C o m m u n ic a tio n
I/O
R eset
POR
V m a in
48+5v
V o lta g e
R e g u la to r
Pum p
Up
VPO R TPO S
SPI
I2 C
M IS O
MOSI
SS
SCK
SCL
SPI
C la s s ific a tio n
AC D AC
8 -b it
Com
In te rfa c e
A C D is c o n n e c t G e n e ra to r
x12
PoL
Sequencer
R e s is to r L in e
D e te c tio n
I2C
LD DAC
L in e D e te c tio n
x12
SDA
Pow er M anagem ent
V p o rt
M e a s u re m e n t
V p o rt
O v e rlo a d /
D is c o n n e c t
R e c o v e ry
VPORTNEG
C la s s ific a tio n
A C D is c o n n e c t
M a c ro
C hannel R T
C o n tro l S ta tu s
V p o rt L e v e l S h ifte r
1 0 -b it
AD C
O ve rlo a d
L o g ic
V m a in -1 7 V
C u rre n t a n d A C
V o lta g e
M e a s u re m e n t
R e a l T im e
P ro te c tio n
C u rre n t L im itin g
8 -b it
AD C
x12
PO RTSENSE
D C D is c o n n e c t
L o g ic
DDig
igita
ital l
D C D is c o n n e c t
C o m p a ra to r
S en se
R e s is to r
I lim R e g
I lim 8 -b it D A C
I c la s s R e g
I c la s s 8 -b it D A C
AAnnaalo
logg
Figure 5: Internal Block Diagram
Digital Section
Communication I/O
The PD64012 incorporates two communication interfaces. When operating in the Enhanced mode, an SPI bus
connects the PD63000 MCU to the PD64012s. The second interface is the I2C, used in the Automatic mode (with
the host).
Both interfaces are used to communicate the contents of internal registers between the PD64012 logic and the
MCU.
PoE Sequencer
This central block of the Digital section includes a combination of internal state machines (macros). It is fed from
the Overload/Disconnect Recovery circuit and from the Power Management block.
Power Management
Receives data from the Vport Measurement block and receives commands and controls from the Communication
Interface. This, in order to control the power allocated to the system, as defined by the host. Power Management
receives requests to enable ports and decides, by communicating with the Sequencer, whether power is to be
allocated.
Overload /Disconnect Recovery
There is a number of macros which decide on port enable and some on port disconnect.
Port enabling: Classification, Resistor Line Detection and Vport Measurement.
Port disable: AC Disconnect, DC Disconnect and Overload Logic. These macros are connected to the Channel RT
Control Status block. Based on the inputs from these macros, the Channel RT controller starts the shutdown
operation or the recovery process. This is done according to preprogrammed parameters for different time
windows, as shown in Figure 2, Power Limits.
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PD64012
12-CHANNEL PoE MANAGER
Macros (802.3 Standard)
Classification – upon request from the MCU, a state machine applies a regulated 18 V on the port output. The
internal current is measured by a metering circuit, compared with a number of preset ranges and in this manner,
the classification is established.
Line Detection – the MCU generates a request to have four separate voltage levels applied to the output port. A
unique measurement circuit monitors the delta between the second and third levels, and between the third and
fourth levels. The voltage differences are compared with values stored in registers. By comparing the values, the
system can decide whether or not to enable the port.
AC Disconnect – the system applies a sinusoidal signal to the positive terminal of the port. The voltage developed
on the port terminals is proportional to the value of the load. If the load is high, the AC component riding on the port
terminals, will be small and reversed. If the load low, the AC component will be large. A special circuit measures
the level of the AC component and compares it with a value stored in a register. Based on the comparison results,
the system decides to disable the port or not.
DC Disconnect for DC Modulation: senses if the port current falls below 7.5 mA. If so, a flag is raised and timers in
the Channel RT Controller are enabled. The Channel RT Controller acts according to pre-programmed limits for
thresholds and time windows, prior to initiating a disconnect status for that port. The circuitry takes into account
PD’s that modulate their current consumption, disconnecting them only if necessary.
Analog Section
Clock Oscillator
A 4 MHz oscillator, used for internal logic and timers.
Power on Reset (POR)
Monitors the internal regulated +3.3 V and generates a Reset signal, if this value drops below 2.8 V. The Reset
signal resets the ASIC’s logic and generates an output flag to the other PD64012 ASICs, via the RESET_N pin.
Charge Pump
This circuit block generates a voltage which increases the main input voltage by 10 VDC (approx.). This potential
is used to operate the AC Disconnect circuits.
Current Limit
This circuit continuously checks the current for enabled ports. Once the current exceeds a specific level, the
system starts to measure the elapsed time. If this period is greater than a preset threshold, the port is disabled. In
all cases, the output current will not exceed a pre-established maximum.
Real Time Protection
This circuit receives flags from two locations in the PD64012: from the sense resistor and from the main input
voltage (48 V). A 10-bit A/D Converter feeds the Digital section, at the Current and AC Voltage Measurement block.
From there on, the system handles the levels according to pre-programmed limits.
DC Disconnect Comparator
Once the port current drops below a set limit, the comparator provides an indication to the DC Disconnect Logic to
that effect.
PD-IM-7348 Evaluation Board
The performance features of the PD64012 PoE Manager can be fully appreciated with the PD-IM-7348 Evaluation
Board. This board allows to investigate all functions accessible to the designer. The evaluation board supports up
to 48 ports, has both I2C and UART interfaces and can demonstrate the Enhanced and Auto modes.
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PD64012
12-CHANNEL PoE MANAGER
I2C Interface
A standard I2C interface is used to communicate between the PD64012 and the host controller.
The PD64012’s I2C interface is designed to support the following features:
♦
♦
♦
SLAVE mode only
Normal-mode and Fast-mode data rate (0 to 400 kb/s)
7-bit addressing - the 7-bit addressing (128 addresses) uses the following address code:
• First MSB = “0” (forced by internal logic)
• 4 MSB address bits are set via the I2C_INI pin, according to the following table
• “mm” bits are set through the ASIC_INI pin (Enhanced mode = “00”; Automatic mode Master
=”00”; Automatic mode Slave = “01”, “10”, “11”)
• “xxx” - 3 LSB are ignored.
I2C ADDRESS
I2C_INI VOLTAGE LEVEL
I2C_INI INTERNAL A/D REGISTER
Address #0
Address #1
Address #2
Address #3
Address #4
Address #5
Address #6
Address #7
Address #8
Address #9
Address #10
Address #11
Address #12
Address #13
Address #14
Address #15
0 to 0.15 V
0.16 to 0.31 V
0.32 to 0.47 V
0.48 to 0.62 V
0.63 to 0.77 V
0.78 to 0.93 V
0.94 to 1.09 V
1.10 to 1.24 V
1.25 to 1.40 V
1.41 to 1.55 V
1.56 to 1.71 V
1.72 to 1.87
1.88 to 2.02 V
2.03 to 2.18 V
2.19 to 2.33 V
2.34 to 2.5 V
0,0000,mm,xxx
0,0001,mm,xxx
0,0010,mm,xxx
0,0011,mm,xxx
0,0100,mm,xxx
0,0101,mm,xxx
0,0110,mm,xxx
0,0111,mm,xxx
0,1000,mm,xxx
0,1001,mm,xxx
0,1010,mm,xxx
0,1011,mm,xxx
0,1100,mm,xxx
0,1101,mm,xxx
0,1110,mm,xxx
1,1111,mm,xxx
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06-0003-058 (Rev. 2.8) / 5 August 2004
11
NOTES
General call addresses; not to be
used
© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
Package Information
The PD64012 is housed in a 64-pin plastic package, 10 x 10 x 1.4 mm, meeting JEDEC’s MS-026 package outline
and dimensions. Exposed pad (for heat-sinking purposes) dimensions are 6.00 by 7.00 mm.
0.2 H A-B D 4 Pls
7
D
64
PIN 1
IDENTIFIER
0.2 C A-B D
49
(S)
0.05
1
48
A
A2
B
E1
E
VIEW Y
16
Z
(L1)
E/2
VIEW AA
33
17
L
R1
A1
E1/2
0.25
GAGE
PLANE
R
32
D1/2
SECTION AB - AB
D/2
D1
ROTATED° 90 CW
b1
BASE
METAL
D
c
1
c
b
PLATING
J
C SEATING
PLANE
VIEW AA
Z2
(x4)
A
H
b (x64)
X=A,B or D
X
0.08
C A-B D
0.08 C
Z3
(x4)
J
Notes:
1.
Dimensions are in millimeters.
2.
Interpret dimensions and tolerances per ASME
Y14.5m-1994.
3.
Datums A, B and D to be determined at datum
plane H.
4.
Dimensions D and E to be determined at seating
plane C.
5.
Dimension b does not include dambar protrusion.
Allowable dambar protrusion shall not cause the
lead width to exceed the maximum b dimension
by more than 0.08 mm. Dambar cannot be
located on the lower radius or the foot. Minimum
space between protrusion and adjacent lead or
protrusion 0.07mm.
6.
Dimensions D1 and E1 do not include mold
protrusion. Allowable protrusion is 0.25mm per
side. D1 and E1 are maximum plastic body size
dimensions including mold mismatch.
7.
Exact shape of each corner is optional.
8.
These dimensions apply to the flat section of the
lead between 0.10mm and 0.25mm from the lead
tip.
AB
AB
e/2
e (x60)
8
VIEW Y
Dim.
Min.
A
---
1.60
0.05
1.35
0.15
L
L1
1.45
R1
0.17
0.27
R2
0.08
0.17
0.23
0.20
---
0.20
S
F
6.00
7.00
0.16
0.09
12.00 BSC
G
6.00
Z
0°
7.00
7°
10.00 BSC
0.50 BSC
Z1
0°
---
Z2
11 °
13 °
E
12.00 BSC
Z3
11 °
13 °
E1
10.00 BSC
A1
G
A2
b
b1
c
c1
EXPOSED
PAD
F
D
D1
e
0.09
Max.
Dim.
Min.
Max.
0.75
0.45
1.00 REF.
--0.08
---
VIEW J-J
Figure 6: PD64012 Mechanical Dimensions
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06-0003-058 (Rev. 2.8) / 5 August 2004
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© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
Applications
The PD64012 may be integrated into a number of applications, ranging from daughter boards to full integration into
Ethernet switches. Examples of such applications are:
Integrated directly in a switch – facilitates the entire PoE concept, by including the ASIC(s) on the main switch PCB.
Daughter board add-on – in which the ASIC is integrated into a small PCB for PoE, mounted on top of the switch’s
main PCB.
Midspan units – stand alone devices, installed between the Ethernet switch and powered devices (telephone,
camera, wireless LAN, etc..). These Midspan units include the PD64012 ASIC as a PoE control element, to inject
power over the communication lines.
Figures 7 thru 10 provide detailed schematic diagrams for various applications of the PD64012.
+48VMain
Vport_Pos_1
100n
VPeri
45.3k
R1
Vmain
Vperi
Ex_Reg
ADC2P5
Vport_Pos
Vport_Neg
Vport_Neg_1
2R
Vport_Sense
ASIC_INI
x12
R3
R2
I2C_INI
VPeri
R4
x12
Vport_Pos
Vport_Pos_12
Vport_Neg
Vport_Neg_12
Vport_Sense
R8
R7
R6
R5
Sense_Neg
MOSI
To
Opto
Couplers
Reset
MISO
SDA
SCK
SCL
CS_0
Disable_Ports
CS_1
SPI
Communication
Bus
Figure 7 - Single-port Application with AC Disconnect Support
VMain
1u
100n
3.3V (VPeri)
22.6k
45.3k
4.7u 100n
Vmain
Vperi
Ref_Port_Neg
100n
Ex_Reg
Vcc2P5
CP_In
ADC2P5
2.5V
100n
100n
CP_Out
47n
IRef
24.9K
Figure 8 - Typical Power Filtering
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06-0003-058 (Rev. 2.8) / 5 August 2004
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© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
+48VMain
Vport_Pos_1
220n
45.3K
VPeri 3.3v
ADC2P5
R1
Vmain
1u
Ex_Reg
Vperi
100n
Vport_Pos
Vport_Neg
I2C_INI
Vport_Neg_1
2R
Vport_Sense
ASIC_INI
x12
x12
R2
VPeri
Vport_Pos
Vport_Pos_12
Vport_Neg
Vport_Neg_12
Vport_Sense
R5
VPeri 3.3v
DGND
Reset
Reset
Disable_Ports_N
Disable_Ports
I2C or UART
Opto
Isolators
Host CPU
DGND
Sense_Neg
MOSI
MOSI
MISO
MISO
SCK
SCK
CS_1_1
CS_1
CS_1_2
CS_0
PD-64012
#00
CS_1_3
CS_1_4
Reset
MC9S08
Disable_Ports_N
MOSI
DGND
MISO
SCK
PD-64012
#01
CS_1
CS_0
(PD-64012
#10)
Reset
Disable_Ports_N
MOSI
R6
MISO
SCK
CS_1
CS_0
PD-64012
#11
Figure 9 - Enhanced Mode Application
+48VMain
Vport_Pos_1
220n
VPeri 3.3v
Vperi
Vmain
Ex_Reg
ADC2P5
45.3K
Vport_Pos
Vport_Neg
R1
Vport_Neg_1
2R
Vport_Sense
ASIC_INI
x12
R3
R2
I2C_INI
VPeri
R4
R7
R6
R5
x12
Vport_Pos
Vport_Pos_12
Vport_Neg
Vport_Neg_12
Vport_Sense
Sense_Neg
R8
MOSI
Reset
To
Opto
SDA
#00
Master
MISO
SCK
SCL
CS_0
Disable_Ports_N
CS_1
MOSI
Reset
#10
Slave
MISO
SDA
SCK
SCL
CS_0
Disable_Ports_N
CS_1
MOSI
Reset
SDA
#11
Slave
MISO
SCK
SCL
CS_0
Disable_Ports_N
CS_1
Figure 10 - Automatic Mode Application
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06-0003-058 (Rev. 2.8) / 5 August 2004
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© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
Reader Notes
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06-0003-058 (Rev. 2.8) / 5 August 2004
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© PowerDsine 2003
Information in this document subject
to change without prior notice.
PD64012
12-CHANNEL PoE MANAGER
Notice
________________________________________________________
PowerDsine assumes no responsibility or liability arising from the use of this Data Sheet, as described herein, nor does it convey any license under its patent rights or the rights
of others.
The information contained herein is believed to be accurate and reliable at the time of printing. However, due to ongoing product improvements and revisions,
PowerDsine cannot accept responsibility for inadvertent errors, inaccuracies, subsequent changes or omissions of printed material.
PowerDsine Ltd. reserves the right to make changes to products and to their specifications as described in this document, at any time, without prior notice. No rights to
any PowerDsine Ltd. Intellectual property are licensed to any third party, directly, by implication or by any other method.
Covered under one or more of the following patents: 6,643,566; 6,473,608.
No Use with Life-Support or Critical Applications _____________________________________________________________________
PowerDsine’s products are not designed, intended, or authorized for use as components in systems intended for:
(1)
(2)
surgical implant into the body, or other applications intended to support or sustain life, or
any other applications whereby a failure of the PowerDsine’s product could create a situation where personal injury, death or damage to persons, systems, data or
business may occur.
PowerDsine assumes no liability in connection with use in these situations and the disclaimers provided below in this manual shall apply. Should a buyer purchase or use
PowerDsine’s products for any such unintended use or unauthorized applications, buyer shall indemnify PowerDsine and its officers and employees against any and all claims
arising out of or in connection with any claim of personal injury, death or other damage of the type described above, associated with such use.
DISCLAIMERS __________________________________________________________________________________________________
POWERDSINE MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE REGARDING THE SUITABILITY OF THE PRODUCTS
CONTAINED HEREIN FOR ANY PARTICULAR PURPOSE, NOR DOES POWERDSINE ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCTS OR CIRCUIT, AND SPECIFICALLY DISCLAIMS ANY AN ALL LIABILITY, INCLUDING,
WITHOUT LIMITATION, CONSEQUENTIAL OR INCIDENTAL DAMAGES. BY USING OUR PRODUCTS USER AGREES NOT TO MAKE ANY
CLAIM FOR PUNITIVE DAMAGES.
POWERDSINE MAKES NO REPRESENTATION OR WARRANTY, EXPRESSED OR IMPLIED, WITH RESPECT TO THE SUFFICIENCY OR
ACCURACY OR UTILITY OF ANY INFORMATION CONTAINED HEREIN. POWERDSINE EXPRESSLY ADVISES THAT ANY USE OF OR
RELIANCE UPON SAID INFORMATION IS AT THE RISK OF THE USER AND THAT POWERDSINE SHALL NOT BE LIABLE FOR ANY
DAMAGE OR INJURY INCURRED BY ANY PERSON OR ORGANIZATION ARISING OUT OF THE SUFFICIENCY, ACCURACY, OR UTILITY
OF ANY INFORMATION CONTAINED HEREIN OR IN CONNECTION WITH THE USE OF ANY OF THE PRODUCTS DESCRIBED HEREIN.
POWERDSINE IS NOT RESPONSIBLE FOR ANY CHANGES IN THE SPECIFICATIONS OR ERRATA OF THIS PRODUCT. INFORMATION
ON THE BASIC PRODUCT CAN BE FOUND AT MOTOROLA'S HOMEPAGE.
Revision History
Revision Level / Date
Para. Affected/page
Description
2.3 / 10 Dec. 03
Lower temperature range deleted. Remains single range only: -20 to +85 °C.
2.41 / 10 Jan. 04
Ordering
Information/page 1
Mode Configuration
Method/page 8
I2C Interface/page 11
Features/page 1
Deleted primary default value in the table column for Notes.
Changed MIB from draft to RFC 3621.
2.5 / 9 Feb. 04
Front & back pages
Added policy statements and disclaimers.
2.6 / 10 Mar. 04
Several
2.7 / 1 Aug. 04
Macros/page 8
Analog section/page 9
Pin Configuration/1
Added temp. of junction-case, under max ratings; added thermal data on page
4; added protection mechanism on page 5.
Corrected inacuracies in descriptions.
2.4 / 18 Dec. 03
2.8 / 5 Aug. 04
Deleted extreneous values for ASIC_INI and deleted default Mode value.
Added part number and associated description.
© 2003 PowerDsine Ltd.
All rights reserved.
PowerDsine is a registered trademark of PowerDsine LTD.
All other products or trademarks are property of their respective owners.
The product described by this manual is a licensed product of PowerDsine.
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06-0003-058 (Rev. 2.8) / 5 August 2004
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© PowerDsine 2003
Information in this document subject
to change without prior notice.