SED1335 CMOS GRAPHIC LCD CONTROLLER Medium-Scale LCD • For Low Operating Voltage 2.7 to 5.0V • On-Chip Character Generator ROM • ■ DESCRIPTION The SED1335 is a CMOS low-power dot matrix liquid crystal graphic display controller. The device stores in external RAM display data sent by an 8-bit microcomputer, and generates all the signals required by the LCD drivers. The LSI incorporates an internal character generator ROM which supports user-defined characters (also an external CGROM can be supported). The SED1335 can be interfaced to high-speed microprocessors such as the Intel family or Motorola family. The controller supports a set of rich commands that will allow the user to create a layered display of characters and graphics. Also, the controller functions as a pipeline buffer between the MPU and display memory so that low-cost, medium-speed SRAM can be used. ■ FEATURES low-power graphic and character display • CMOS controller MPU interface is compatible with both • Selectable the Intel family and the Motorola family • Smooth scrolling support: • • • • Internal character generator ROM • Supports external character generator ROM: • Horizontal and vertical scroll Scrolling of selected areas of the display Multimode display: 2 layers of overlapping characters and graphics 3 layers of overlapping graphics Selectable display synthesis: Inverse video Flashing display, cursor on/off/blink Under and bar cursor, block cursor Simple animation Programmable cursor • • • • 8 × 8 or 8 × 16 pixel characters Allowing mixing of ROM and RAM character sets Supports 64K bytes of memory: 4K bytes of user-definable characters 60K bytes of display memory in 2 of 32K × 8 100ns SRAM or in 8 of 8K × 8 100ns SRAM Display duty .................... 1/2 to 1/256 Low power dissipation 5mA (typical) 0.05µA (typical), standby Logic power supply .......................... 2.7 to 5.5V Package: .................. Plastic QFP5-60 pin (F0A) Plastic QFP6-60 pin (F0B) ■ SYSTEM BLOCK DIAGRAM DATA CPU CONTROL SED1335F 68xx 80xx SRAM 139 MONO LCD SED1335 ■ BLOCK DIAGRAM External CG ROM I/O Register Refresh Address Counter Dot Counter CG ROM Layered Display Controller Oscillator Circuit XD D0 to D7 A0, CS RES RD, WR MPU Interface SEL1 SEL2 XD0 to XD3 LCD Controller XG Display Address Controller LP, WF YSCL,YDIS VD0 to VD7 VRAM Interface Cursor Address Controller LCD VRD VCE VWR VA0 to VA15 CG RAM XSCL, XECL Video RAM 50 60 1 Index 5 6 45 40 SED1335FOA 10 30 29 15 20 VD3 VD2 VD1 VD0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 NC VA8 VA9 VA10 VA11 VA12 VA13 NC VA14 VA15 VD0 VD1 VD2 45 46 31 30 SED1335FOB Index 60 1 16 15 VA5 VA4 VA3 VA2 VA1 VA0 VWR VCE VRD RES NC NC RD WR SEL2 D2 D3 D4 D5 D6 55 D7 XD3 XD2 XD1 XD0 XECL XSCL VSS LP WF YDIS YD YSCL VD7 VD6 VD5 VD4 VD3 XD CS A0 VDD D0 D1 VD4 VD5 VD6 VD7 YSCL YD YDIS WF LP VSS XSCL XECL XD0 XD1 XD2 XG SEL1 SEL2 WR RD NC NC RES VRD VCE VWR VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 ■ PINOUT 140 XD3 D7 D6 D5 D4 D3 D2 D1 D0 VDD A0 CS XD XG SEL1 SED1335 ■ PIN DESCRIPTION Pin No. Pin Name I/O Functions SED1335FOA SED1335FOB XG 54 17 I Oscillator terminal XD 55 18 O Oscillator terminal VDD 58 21 +5V Power supply VSS 13 36 GND(0V) Power supply SEL1,2 53 • 52 16 • 15 I D0 to D7 59 to 60, 1 to 6 22 to 29 I/O MPU interface format selection A0 57 20 I RD 50 13 I WR 51 14 I CS 56 19 I Chip select Data bus Data type selection 80 series Read strobe signal 68 series “E” clock 80 series Write strobe signal 68 series R/W signal RES 47 10 I Reset VA15 to VA0 27 • 28, 30 to 43 1 to 6, 50 to 59 O VRAM address bus VD7 to VD0 19 to 26 42 to 49 I/O VRAM data bus VWR 44 7 O VRAM write signal VRD 46 9 O VRAM read signal VCE 45 8 O VRAM chip enable XD3 to XD0 7 to 10 30 to 33 O Dot data output bus to X driver XSCL 12 35 O Dot data shift clock for X driver XECL 11 34 O Chip enable shift clock for X driver LP 14 37 O Dot data latch pulse WF 15 38 O Frame signal YSCL 18 41 O Scan data shift clock for Y driver YD 17 40 O Scan data output YDIS 16 39 O Power down signal when display is OFF NC: No Connection ■ ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • Parameter (VSS = 0V) Symbol Ratings Unit Supply voltage VDD –0.3 to 7.0 V Input voltage VIN –0.3 to VDD+0.3 V Power dissipation PD 300 mW Operating temperature Topr –20 to 75 °C Storage temperature Tstg –60 to 150 °C Soldering temperature and time Tsol 260°C, 10s (at lead) — 141 SED1335 • DC Electrical Characteristics (1) Parameter Min Typ Max Unit Operating voltage VDD 4.5 5.0 5.5 V Register data retention voltage VOH 2.0 — 6.0 V High level input voltage T Low level input voltage T L High level output voltage Low level output voltage VIHT 0.5xVDD — VDD V VILT VSS — 0.2xVDD V High level input voltage C M Low level input voltage O High level output voltage S Low level output voltage S C H M I T T Symbol (VSS = 0V, VDD = 4.5 to 5.5V, Ta = –20 to 75°C) Condition VOHT IOH = –5.0mA 2.4 — — V VOLT IOL = 5.0mA — — VSS+0.4 V VIHC 0.8xVDD — VDD V VILC VSS — 0.2xVDD V VDD–0.4 — — V — — VOHC IOH = –2.0mA VOLC IOL = 2.0mA VSS+0.4 V Positive trigger threshold voltage VT+ 0.5VDD 0.7VDD 0.8VDD V Negative trigger threshold voltage VT– 0.2VDD 0.3VDD 0.5VDD V Input leakage current ILI Output leakage current ILO Average operating current Iopr Standby current IQ VIN = VDD/VSS fosc = 10MHz, No-load 256 × 200 dot Sleep XG, CS, RD = VDD VDD D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VCE, VRD, VWR SEL1, SEL2, YD, XD0 to XD3, XSCL, YDIS, LP, WF, CL0, XECL, YSCL RES — 0.05 2.0 µA — 0.10 5.0 µA — 11 15 mA VDD — 0.05 20 µA VDD Oscillation frequency fosc AT X’tal 1.0 — 10.0 MHz External clock frequency fCL Duty 47.5% 1.0 — 10.0 MHz Feed back resistance Rf 0.5 1.0 3.0 MΩ 142 Terminal XG, XD SED1335 • DC Electrical Characteristics (2) Parameter Min Typ Max Unit Operating voltage VDD 2.7 3.5 4.5 V Register data retention voltage VOH 2.0 — 6.0 V High level input voltage T Low level input voltage T L High level output voltage Low level output voltage VIHT 0.8xVDD — VDD V VILT VSS — 0.2xVDD V High level input voltage C M Low level input voltage O High level output voltage S Low level output voltage S C H M I T T Symbol (VSS = 0V, VDD = 2.7 to 4.5V, Ta = –20 to 75°C) Condition VOHT IOH = –3.0mA VDD–0.4 — — V VOLT IOL = 3.0mA — — VSS+0.4 V 0.8xVDD — VDD V VIHC VILC VOHC IOH = –1.0mA VOLC IOL = 1.0mA VSS — 0.2xVDD V VDD–0.4 — — V — — VSS+0.4 V Positive trigger threshold voltage VT+ 0.5VDD 0.7VDD 0.8VDD V Negative trigger threshold voltage VT– 0.2VDD 0.3VDD 0.5VDD V Input leakage current ILI Output leakage current ILO Average operating current Iopr Standby current IQ Oscillation frequency fosc External clock frequency fCL Feed back resistance Rf VIN = VDD/VSS fosc = 6.1MHz, No-load 256 × 200 dot Sleep D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VCE, VRD, VWR SEL1, SEL2, YD, XD0 to XD3, XSCL, YDIS, LP, WF, CL0, XECL, YSCL RES 0.05 2.0 µA — 0.10 5.0 µA 7.0 mA VDD VDD — 3.5 (VDD=3.5V) 0.05 20 µA AT X’tal 1.0 — 8.0 MHz Duty 47.5% 1.0 — 8.0 MHz 0.7 — 4.0 MΩ 143 VDD — — XG, CS, RD = VDD Terminal XG, XD SED1335 • ° Timing Diagrams 8080-Family Interface Timing AO, CS tAW8 tAH8 tCYC WR, RD tCC tDH8 tDS8 D0 to D7 (Write) tACC8 tOH8 D0 to D7 (Read) Ta = –20 to 75°C Signal A0, CS WR, RD D0 to D7 Symbol Parameter tAH8 tAW8 tCYC tCC tDS8 tDH8 tACC8 tOH8 Address hold time Address setup time System cycle time Strobe pulsewidth Data setup time Data hold time RD access time Output disable time VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V min max min max 10 — 10 — 0 — 0 — See note — See note — 120 — 150 — 120 — 120 — 5 — 5 — — 50 — 80 10 50 10 55 Note: For memory control and system control commands: tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245 For all other commands: tCYC8 = 4tC + tCC + 30 144 Unit Condition ns ns ns ns ns ns ns ns CL = 100 pF SED1335 ° 6800-Family Interface Timing E tCYC tAW6 tEW R/W tAH6 AO, CS tDH6 tDS6 D0 to D7 (Write) tACC6 tOH6 D0 to D7 (Read) Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH. Ta = –20 to 75°C Signal Symbol Parameter A0, CS, R/W tCYC6 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6 tEW System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable pulsewidth D0 to D7 E VDD = 4.5 to 5.5V min max See note — 0 — 0 — 100 — 0 — 10 50 — 85 120 — Note: For memory control and system control commands: tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245 For all other commands: tCYC6 = 4tC + tEW + 30 145 VDD = 2.7 to 4.5V min max See note — 10 — 0 — 120 — 0 — 10 75 — 130 150 — Unit Condition ns ns ns ns ns ns ns ns CL = 100 pF SED1335 ° Display Memory Read Timing EXTΦ0 tC tW tCE tW VCE tCYR VA0 to VA15 tASC tAHC tRCH VRD tRCS tCEA tCE3 tOH2 tACV VD0 to VD7 (SED1335F) Ta = –20 to 75°C Signal Symbol EXT φ0 tC tW VCE tCE tCYR VA0 to VA15 tASC tAHC tRCS VRD tRCH VD0 to VD7 tACV tCEA tOH2 tCE3 Parameter VDD = 4.5 to 5.5V min max 100 — Clock period VCE HIGH-level tC – 50 — pulsewidth VCE LOW-level 2tC – 30 — pulsewidth Read cycle time 3tC — Address setup time to — tC – 70 falling edge of VCE Address hold time from 2tC – 30 — falling edge of VCE Read cycle setup time tC – 45 — to falling edge of VCE Read cycle hold time 0.5tC — from rising edge of VCE Address access time — 3tC – 100 VCE access time — 2tC – 80 Output data hold time 0 — VCE to data off time 0 — 146 VDD = 2.7 to 4.5V min max 125 — Unit Condition ns tC – 50 — ns 2tC – 30 — ns 3tC — ns tC – 100 — ns 2tC – 40 — ns tC – 60 — ns 0.5tC — ns — — 0 0 3tC – 115 2tC – 90 — — ns ns ns ns CL = 100 pF SED1335 ° Display Memory Write Timing EXTφ0 tC tCA tW tCE VCE tASC tAHC tCYW VA0 to VA15 tAS tWSC tAH2 tWHC VRW tDH2 tDSC tDHC VD0 to VD7 Ta = –20 to 75°C Signal Symbol Parameter EXT φ0 tC Clock period VCE HIGH-level pulsewidth VCE LOW-level pulsewidth Write cycle time Address hold time from falling edge of VCE Address setup time to falling edge of VCE Address hold time from rising edge of VCE Address setup time to falling edge of VWR Address hold time from rising edge of VWR Write setup time to falling edge of VCE Write hold time from falling edge of VCE Data input setup time to falling edge of VCE Data input hold time from falling edge of VCE Data hold time from rising edge of VWR tW VCE tCE tCYW tAHC tASC VA0 to VA15 tCA tAS tAH2 tWSC VWR tWHC tDSC VD0 to VD7 tDHC tDH2 VDD = 4.5 to 5.5V min max 100 — VDD = 2.7 to 4.5V min max 125 — tC – 50 — tC – 50 — ns 2tC – 30 — 2tC – 30 — ns 3tC — 3tC — ns 2tC – 30 — 2tC – 40 — ns tC – 70 — tC – 110 — ns 0 — 0 — ns 0 — 0 — ns 10 — 10 — ns tC – 80 — tC – 115 — ns 2tC – 20 — 2tC – 20 — ns tC – 85 — tC – 125 — ns 2tC – 30 — 2tC – 30 — ns 5 50 5 50 ns Unit Condition ns CL = 100 pF Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read from the memory is placed on the bus. 147 SED1335 ° SLEEP IN Command Timing VCE SLEEP IN write SYSTEM SET write tWRL WR (command input) tWRD YDIS Ta = –20 to 75°C Signal Symbol tWRD WR tWRL Parameter VDD = 4.5 to 5.5V min max VCE falling-edge delay time YDIS falling-edge delay time VDD = 2.7 to 4.5V min max Unit *1 — *1 — ns — *2 — *2 ns Condition CL = 100 pF Notes: 1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation) 2. tWRL = 36tC × [TC/R] × [L/F] + 70 • External Oscillator Signal Timing tRCL tFCL EXTφ0 tWL tWH tCL Ta = –20 to 75°C Signal EXT φ0 Symbol Parameter tRCL tFCL External clock rise time External clock fall time External clock HIGH-level pulsewidth External clock LOW-level pulsewidth External clock period tWH tWL tC VDD = 4.5 to 5.5V min max — 15 — 15 VDD = 2.7 to 4.5V min max — 15 — 15 Unit *1 *2 *1 *2 ns *1 *2 *1 *2 ns 100 — 125 — ns Notes: 1. (tC – tRCL – tFCL) × ns ns 475 < tWH, tWL 1000 2. 148 (tC – tRCL – tFCL) × 525 > tWH, tWL 1000 Condition SED1335 ° LCD Output Timing The following characteristics are for a 1/64 duty cycle. Row 62 63 64 1 2 3 4 60 61 62 63 64 LP 1 frame time YD WF WF 1 line time Row 64 Row 1 Row 2 LP XSCL XD0 to XD3 (14) (15) (16) tr (1) (15) (16) (1) (2) (3) tWX tf (15) (16) tCX XSCL tDS tDH tLS XD0 to XD3 tWL tLD LP tDHY tDF WF(B) YD 149 (1) SED1335 Ta = –20 to 75°C Signal Symbol tr tf XSCL XD0 to XD3 LP WF YD tCX tWX tDH tDS tLS tWL tLD tDF tDHY VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V min max min max Rise time — 30 — 40 Fall time — 30 — 40 Shift clock cycle time 4tC — 4tC — XSCL clock pulsewidth 2tC – 60 — 2tC – 60 — X data hold time 2tC – 50 — 2tC – 50 — X data setup time 2tC – 100 — 2tC – 105 — Latch data setup time 2tC – 50 — 2tC – 50 — LP pulsewidth 4tC – 80 — 4tC – 120 — LP delay time from XSCL 0 — 0 — Permitted WF delay — 50 — 50 Y data hold time 2tC – 20 — 2tC – 20 — Parameter Unit ns ns ns ns ns ns ns ns ns ns ns Condition CL = 100pF Note: The SED1335F reads display memory data from the address of the top left corner of the display screen, then scans horizontally until it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data is sent starting from the left side of the display line. 150 SED1335 ■ EXAMPLE OF APPLICATION 10MHz A1 to A7 A0 Chip Selector CS IORD MPU VA13 to VA15 VCE D0 to D7 D0 to D7 RD WR RESET VWR VRD VA0 to VA12 A B C Y7 Y6 Y0 CS7 CS6 CS0 VA12 A0 to A12 WE A0 to A12 WE A11 SRM2064 CS1 (RAM1) CS2 SRM2064 CS1 (RAM2) CS2 2732 (IXT.CG) OE D0 to D7 D0 to D7 OE D0 to D7 OE CE VD0 to VD7 LCD SED1600F *2 FR EI SED1600F D0 to D3 V3 *2 FR EI LP XSCL V2 SED1600F LP XSCL *2 FR EI D0 to D3 V1 D0 to D3 *1 (Y Driver) LP XSCL Voltage Converters Poff LAT DI INH FR YSCL SED1630F XECL XSCL LP WF YDIS YD YSCL RESET RD WR RES XD0 to XD3 SED1335FOA A0 XD HC138 XG V4 Vreg V5 (X Driver) LCD UNIT Recommend X Driver: SED1742F, SED1600F Recommend Y Driver: SED1743F, SED1610F, SED1631 151 SED1335 ■ CHARACTER CODE TABLE (Built-in Character Generator) 0 1 2 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 3 4 5 6 7 8 9 A B C D Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 2 3 4 5 6 7 A B C D 1 152 E F