PEDL66579-03 1Semiconductor MSM66579 Family This version: Nov. 1999 Preliminary 16-Bit Microcontroller GENERAL DESCRIPTION The MSM66579 family of highly functional CMOS 16-bit single chip microcontrollers utilizes the nX-8/500S, Oki’s proprietary CPU core. Four channels of serial ports, consisting of two channels of synchronous serial ports with 32-byte FIFO registers and two channels of UART/synchronous serial ports, enable easy interfacing with external peripheral LSI devices such as an encoder/decoder or servocontroller. A switching function permits selection of separate address and data lines or multiplexed lines for the bus interface to correspond to various peripheral LSI devices. With features such as a clock gear function, dual clock function, programmable pull-up ports in which individual bits can be programmed, and a small, thin package, the MSM66579 family of microprocessors is optimally suited for the system control of small-sized low power devices. The flash ROM versions (MSM66Q577L and MSM66Q579L) programmable with a single 2.7V (minimum) power supply and flash ROM version (MSM66Q577) programmable with a single 5V power supply are also included in the family. These versions are easily adaptable to quick specification changes and to new product revisions. APPLICATIONS Digital Audio Control Systems PC peripheral Control Systems Office Electronics Control Systems ORDERING INFORMATION Order Code or Product Name Package Low voltage mask ROM version (2.4 to 3.6 V) MSM66577L-TB MSM66577-TB MSM66Q577L-TB MSM66Q577-TB Remark 5 V mask ROM version 100-pin plastic TQFP (TQFP 100-P-1414-0.50-K) MSM66577L flash ROM version MSM66577 flash ROM version MSM66579L-TB Low voltage mask ROM version (2.4 to 3.6 V) MSM66Q579L-TB MSM66579L flash ROM version 1/37 PEDL66579-03 1Semiconductor MSM66579 Family FEATURES Name MSM66577L MSM66577 MSM66579L Operating temperature –30°C to +70°C Power supply voltage/ maximum frequency VDD = 2.4 to 3.6 V/f = 14 MHz VDD = 4.5 to 5.5 V/f = 30 MHz VDD = 2.4 to 3.6 V/f = 28 MHz Minimum instruction execution time 143 ns at 14 MHz 61 µs at 32.768 kHz 67 ns at 30 MHz 61 µs at 32.768 kHz Internal ROM size (max. external) 128 KB (1 MB) Internal RAM size (max. external) I/O ports 71 ns at 28 MHz 61 µs at 32.768 kHz 4 KB (1 MB) 12 KB (1 MB) 74 I/O pins (with programmable pull-up resistors) 8 input-only pins 16-bit free running timer × 1ch Compare out/capture input × 2ch 16-bit timer (auto reload/timer out) × 1ch 8-bit auto reload timer × 2ch (can also be used as 16-bit timer × 1ch) Timers 8-bit auto reload timer × 1ch 8-bit auto reload timer × 3ch (also functions as serial communication baud rate generator) 8-bit auto reload timer × 1ch (also functions as watchdog timer) Watch timer (Real-timer counter) × 1ch 8-bit PWM × 4ch (can also be used as 16-bit PWM × 2ch) Synchronous, with 32-byte FIFO × 2ch Serial port UART/Synchronous × 2ch A/D converter 10-bit A/D converter × 8ch D/A converter 8-bit D/A converter × 2ch Non-maskable × 1ch Maskable × 8ch External interrupt Interrupt priority 3 levels Separate address and data busses/multiplexed address and data busses Others Bus release function Dual clocks Flash ROM version MSM66Q577L MSM66Q577 MSM66Q579L 2/37 PEDL66579-03 1Semiconductor MSM66579 Family SPECIAL FEATURES 1. High-performance CPU The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support. 2. A variety of power saving modes Attaching a 32.768-kHz crystal produces a real-time clock signal from the internal clock timer. Use of a single clock in place of dual clocks is possible. Switching the CPU clock to this clock signal, 1/2 × main clock, or 1/4 × main clock, then produces operation in a low power consumption mode. The clock gear function allows a 1/2 × or 1/4 × main clock to be selected for the CPU operating clock. The family provides a wide range of standby control functions. In addition to the usual STOP mode that stops the oscillator, there are the quick restart STOP mode that shuts down the CPU and peripherals but leaves the oscillator running, and the HALT mode that shuts down the CPU but leaves the peripherals running. 3. Variety of multifunctional serial ports The family includes two channels of built-in synchronous serial ports with 32-byte FIFO implementing an auto transfer function. The family allows multi-byte 1-frame information which consists of address, command, and data to be easily and efficiently transmitted to or received from a serial interface type peripheral LSI device. The family also allows multi-byte character information to be easily and efficiently transmitted to or received from an LCD module. In addition, the family has two channels of combined UART/synchronous serial ports, and provides four channels of serial interfaces. UART/synchronous SIO UART/synchronous SIO Synchronous SIO with 32-byte FIFO Synchronous SIO with 32-byte FIFO 4. MSM66Q577L, MSM66Q577 and MSM66Q579L with flash memory programmable with single power supply In addition to the regular mask ROM version, the family includes these versions with 128KB of flash memory that can be programmed using a single power supply. For the MSM66Q577L and MSM66Q579L, an internal booster circuit derives the necessary program voltage from the device's low (2.7 V min) power supply, and the program voltage for the MSM66Q577 is provided with a single 5 V power supply. 5. High-precision A/D and D/A converters The family includes a high-precision 10-bit analog-to-digital converter with eight channels and 8-bit digital-toanalog converter with two channels. 6. Multifunction PWM The family supports both 8- and 16-bit PWM operation. Choosing between the time-base counter output or overflow from an 8-bit auto-reload timer as the PWM counter clock source provides a wide number of possibilities over a broad frequency range. The 16-bit PWM configuration supports a high-speed synchronization mode that generates a high-precision output signal with less ripple suitable for digital-to-analog control applications. 3/37 PEDL66579-03 1Semiconductor MSM66579 Family 7. Programmable pull-up resistors Building the pull-up resistors into the chip contributes to overall design compactness. Making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These programmable pull-up resistors are available for all I/O pins not already assigned specific functions (such as the oscillator connection pins). 8. Wide support for external interrupts There are a total of nine interrupt channels for use in communicating with external devices: eight for maskable interrupts and one for non-maskable interrupts. 4/37 PEDL66579-03 1Semiconductor MSM66579 Family BLOCK DIAGRAM CLKOUT XTOUT RXD1 TXD1 RXC1 TXC1 TM4OUT RXD6 TXD6 RXC6 TXC6 16 bit Timer0 8 bit Timer1 Peripheral Control ALU Control Registers SIO1 (UART/SYNC) ALU Control ACC 8 bit Time4/BRG SSP PSW LRB PC DSR TSR CSR SIO6 Memory Control Pointing Registers Instruction Decoder SIO4 (32 byte FIFO SYNC) RAM 4K/12K SIO5 (32 byte FIFO SYNC) 8 bit Timer6/WDT PWMOUT0 PWMOUT2 8 bit PWM0 PWMOUT1 8 bit PWM1 ROM 128K 8 bit Timer9 AO0 AO1 NMI EXINT0 to EXINT7 10 bit A/D Converter RTC Port Control VREF AGND AI0 to AI7 TBC CAP/CMP 16 bit FRC EA SELMBUS PSEN RD WR WAIT D0 to D7 (AD0 to AD7*) A0 to A19 (AD8 to AD19*) PWMOUT3 CPCM0 CPCM1 XT0 XT1 OSC0 OSC1 HOLD HLDACK RES (UART/SYNC) 8 bit Timer5/BRG SIOI5 SIOO5 SIOCK5 System 8 bit Timer2 8 bit Timer3/BRG SIOI4 SIOO4 SIOCK4 CPU Core Bus Port Control TM0OUT TM0EVT TM1OUT TM1EVT TM2OUT TM2EVT 8 bit D/A Converter Interrupt P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P14 P15 *: Address output/data I/O when selecting multiplexed bus type. 5/37 PEDL66579-03 1Semiconductor MSM66579 Family 80 85 90 75 1 5 70 10 65 15 60 20 55 50 45 40 P1-7/A15 P1-6/A14 P1-5/A13 P1-4/A12 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 P4-7/A7 P4-6/A6 P4-5/A5 P4-4/A4 P4-3/A3 P4-2/A2 P4-1/A1 P4-0/A0 GND P0-7/D7(AD7*) P0-6/D6(AD6*) P0-5/D5(AD5*) P0-4/D4(AD4*) P0-3/D3(AD3*) P0-2/D2(AD2*) P0-1/D1(AD1*) P0-0/D0(AD0*) P6-6/TM2EVT P6-7/TM2OUT P5-4/CPCM0 P5-5/CPCM1 P5-6/TM0OUT P5-7/TM0EVT RES NMI EA VDD XT0 XT1 GND OSC0 OSC1 VDD P11-0/WAIT P11-1/HOLD P11-2/CLKOUT P11-3/XTOUT SELMBUS P3-0/ALE P3-1/PSEN P3-2/RD P3-3/WR 35 25 30 SIOCK4/P10-3 SIOO4/P10-4 SIOI4/P10-5 RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 TM4OUT/P8-4 PWM2OUT/P8-6 PWM3OUT/P8-7 PWM0OUT/P7-6 PWM1OUT/P7-7 VDD GND HLDACK/P9-7 EXINT4/P9-0 EXINT5/P9-1 EXINT6/P9-2 EXINT7/P9-3 EXINT0/P6-0 EXINT1/P6-1 EXINT2/P6-2 EXINT3/P6-3 TM1EVT/P6-4 TM1OUT/P6-5 95 100 TXC6/P15-3 RXC6/P15-2 TXD6/P15-1 RXD6/P15-0 SIOCK5/P14-0 SIOO5/P14-1 SIOI5/14-2 GND AO0/P14-6 AO1/P14-7 AGND AI7/P12-7 AI6/P12-6 AI5/P12-5 AI4/P12-4 AI3/P12-3 AI2/P12-2 AI1/P12-1 AI0/P12-0 VREF VDD A19/P2-3 A18/P2-2 A17/P2-1 A16/P2-0 PIN CONFIGURATION (TOP VIEW) 100-pin Plastic TQFP *: Address output/data I/O when selecting multiplexed bus type. 6/37 PEDL66579-03 1Semiconductor 85 1 80 5 75 10 70 15 65 20 60 25 55 50 45 P2-1/A17 P2-0/A16 P1-7/A15 P1-6/A14 P1-5/A13 P1-4/A12 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 P4-7/A7 P4-6/A6 P4-5/A5 P4-4/A4 P4-3/A3 P4-2/A2 P4-1/A1 P4-0/A0 GND P0-7/D7(AD7*) P0-6/D6(AD6*) P0-5/D5(AD5*) P0-4/D4(AD4*) P0-3/D3(AD3*) P0-2/D2(AD2*) P0-1/D1(AD1*) P0-0/D0(AD0*) P3-3/WR P3-2/RD P3-1/PSEN P5-4/CPCM0 P5-5/CPCM1 P5-6/TM0OUT P5-7/TM0EVT RES NMI EA VDD XT0 XT1 GND OSC0 OSC1 VDD P11-0/WAIT P11-1/HOLD P11-2/CLKOUT P11-3/XTOUT SELMBUS P3-0/ALE 40 30 35 TXD6/P15-1 RXC6/P15-2 TXC6/P15-3 SIOCK4/P10-3 SIOO4/P10-4 SIOI4/P10-5 RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 TM4OUT/P8-4 PWM2OUT/P8-6 PWM3OUT/P8-7 PWM0OUT/P7-6 PWM1OUT/P7-7 VDD GND HLDACK/P9-7 EXINT4/P9-0 EXINT5/P9-1 EXINT6/P9-2 EXINT7/P9-3 EXINT0/P6-0 EXINT1/P6-1 EXINT2/P6-2 EXINT3/P6-3 TM1EVT/P6-4 TM1OUT/P6-5 TM2EVT/P6-6 TM2OUT/P6-7 90 100 95 RXD6/P15-0 SIOCK5/P14-0 SIOO5/P14-1 SIOI5/P14-2 GND AO0/P14-6 AO1/P14-7 AGND AI7/P12-7 AI6/P12-6 AI5/P12-5 AI4/P12-4 AI3/P12-3 AI2/P12-2 AI1/P12-1 AI0/P12-0 VREF VDD A19/P2-3 A18/P2-2 MSM66579 Family 100-pin Plastic QFP *: Address output/data I/O when selecting multiplexed bus type. 7/37 PEDL66579-03 1Semiconductor MSM66579 Family PIN DESCRIPTIONS In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin. Description Function Symbol Type Port P0_0/D0 (AD0) to P0_7/D7 (AD7) I/O Primary function 8-bit I/O port 10 mA sink capability Pull-up resistors can be Type I/O specified for each individual bit P1_0/A8 to P1_7/A15 P2_0/A16 to P2_3/A19 selecting a multiplexed bus) O External memory access Address output port I/O 4-bit I/O port Pull-up resistors can be specified for each individual bit O External memory access Address output port 4-bit I/O port 10 mA sink capability Pull-up resistors can be O External memory access Address latch enable signal output pin specified for each individual bit O I/O P3_3/WR P4_0/A0 I/O P5_4/CPCM0 I/O External program memory access Read strobe output pin P3_2/RD P5_5/CPCM1 (Address output/data I/O port when I/O P3_1/PSEN P4_7/A7 External memory access Data I/O port 8-bit I/O port Pull-up resistors can be specified for each individual bit P3_0/ALE to Secondary function 8-bit I/O port Pull-up resistors can be specified for each individual bit 4-bit I/O port Pull-up resistors can be specified for each individual bit O External memory access Read strobe output pin O External memory access Write strobe output pin O External memory access Address output port (When selecting a separate bus type) I/O I/O Capture 0 input / Compare 0 output pin Capture 1 input / Compare 1 output pin P5_6/TM0OUT O Timer 0 timer output pin P5_7/TM0EVT I Timer 0 external event input pin I External interrupt 0 input pin I External interrupt 1 input pin I External interrupt 2 input pin I External interrupt 3 input pin I Timer1 external event input pin P6_5/TM1OUT O Timer 1 timer output pin P6_6/TM2EVT I Timer 2 external event pin P6_7/TM2OUT O Timer 2 timer output pin P6_0/EXINT0 8-bit I/O port Pull-up resistors can be specified for each individual bit P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P6_4/TM1EVT I/O 8/37 PEDL66579-03 1Semiconductor MSM66579 Family Description Function Symbol Type Port P7_6/PWM0OUT P7_7/PWM1OUT I/O P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 Primary function Type Secondary function 2-bit I/O port Pull-up resistors can be specified for each individual bit O PWM0 output pin O PWM1 output pin 7-bit I/O port Pull-up resistors can be specified for each individual bit I SIO1 receive data input pin O SIO1 transmit data output pin I/O I/O SIO1 receive clock I/O pin I/O SIO1 transmit clock I/O pin P8_4/TM4OUT O Timer 4 timer output pin P8_6/PWM2OUT O PWM2 output pin P8_7/PWM3OUT O PWM3 output pin I External Interrupt 4 input pin I External Interrupt 5 input pin I External Interrupt 6 input pin P9_3/EXINT7 I External Interrupt 7 input pin P9_7/HLDACK O HOLD mode output pin P9_0/EXINT4 5-bit I/O port Pull-up resistors can be P9_1/EXINT5 P9_2/EXINT6 I/O P10_3/SIOCK4 P10_4/SIOO4 I/O P10_5/SIOI4 P11_0/WAIT P11_1/HOLD specified for each individual bit 3-bit I/O port Pull-up resistors can be specified for each individual bit 4-bit I/O port 10 mA sink capability I/O P11_2/CLKOUT Pull-up resistors can be specified for each individual bit P11_3/XTOUT P12_0/AI0 to I/O SIO4 transmit-receive clock I/O pin I SIO4 receive data input pin O SIO4 transmit data output pin I External data memory access wait input pin I HOLD mode request input pin O Main clock pulse output pin O Sub clock pulse output pin 8-bit input port A/D converter analog input port I I P12_7/AI7 P14_0/SIOCK5 P14_1/SIOO5 5-bit I/O port Pull-up resistors can be specified for each individual bit I/O SIO5 transmit-receive clock I/O pin O SIO5 transmit data output pin I SIO5 receive data input pin P14_6/AO0 O D/A converter analog output port P14_7/AO1 O D/A converter analog output port I SIO6 receive data input pin O SIO6 transmit data output pin P14_2/SIOI5 I/O P15_0/RXD6 P15_1/TXD6 P15_2/RXC6 P15_3/TXC6 I/O 4-bit I/O port Pull-up resistors can be specified for each individual bit I/O SIO6 receive clock I/O pin I/O SIO6 transmit clock I/O pin 9/37 PEDL66579-03 1Semiconductor Function Power supply Oscillation MSM66579 Family Symbol Type Description VDD I Power supply pin Connect all VDD pins to the power supply.* GND I GND pin Connect all GND pins to GND.* VREF I Analog reference voltage pin AGND I Analog GND pin XT0 I Sub clock oscillation input pin Connect to a crystal oscillator of f = 32.768 kHz. XT1 O Sub clock oscillation output pin Connect to a crystal oscillator of f = 32.768 kHz. The clock output is opposite in phase to XT0. OSC0 I Main clock oscillation input pin Connect to a crystal or ceramic oscillator. Or, input an external clock. OSC1 O Main clock oscillation output pin Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clock is used. Reset RES I Reset input pin Other NMI I Non-maskable interrupt input pin EA I External program memory access input pin If the EA pin is enabled (low level), the internal program memory is masked and the CPU executes the program code in external program memory through all address space. SELMBUS I SELMBUS = H: Address/data separate bus type SELMBUS = L: Multiplexed bus type * Each of the family devices has unique pattern routes for the internal power and ground. Connect the power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation. 10/37 PEDL66579-03 1Semiconductor MSM66579 Family ABSOLUTE MAXIMUM RATINGS Parameter Symbol Digital power supply voltage Condition VDD Input voltage VI Output voltage VO Analog reference voltage GND = AGND = 0 V Ta = 25°C VREF Analog input voltage VAI Power dissipation PD TSTG Storage Temperature Rating Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V –0.3 to VDD + 0.3 V –0.3 to VDD + 0.3 V –0.3 to VREF V Ta = 70°C 100-pin TQFP per package 100-pin QFP 650 mW 750 mW — –50 to +150 °C Range Unit RECOMMENDED OPERATING CONDITIONS Parameter Digital power supply voltage Analog reference voltage Symbol VDD Condition MSM66577 fOSC ≤ 30 MHz 4.5 to 5.5 MSM66577L fOSC ≤ 14 MHz 2.4 to 3.6 MSM66579L fOSC ≤ 28 MHz 2.4 to 3.6 MSM66Q577 fOSC ≤ 30 MHz 4.5 to 5.5 MSM66Q577L fOSC ≤ 14 MHz 2.7 to 3.3 MSM66Q579L fOSC ≤ 28 MHz 2.7 to 3.3 V VREF — VDD –0.3 to VDD V Analog input voltage VAI — AGND to VREF V Memory hold voltage VDDH fOSC = 0 Hz 2.0 to 5.5 V Operating frequency Ambient temperature Fan out MSM66577 VDD = 4.5 to 5.5 V 2 to 30 MSM66577L VDD = 2.4 to 3.6 V 2 to 14 MSM66579L VDD = 2.4 to 3.6 V 2 to 28 MSM66Q577 VDD = 4.5 to 5.5 V 2 to 30 MSM66Q577L VDD = 2.7 to 3.3 V 2 to 14 MSM66Q579L VDD = 2.7 to 3.3 V 2 to 28 fXT — 32.768 kHz Ta — –30 to +70 °C MOS load 20 — P0, P3, P11 6 — P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15 1 — fOSC N TTL load MHz 11/37 PEDL66579-03 1Semiconductor MSM66579 Family ALLOWABLE OUTPUT CURRENT VALUES MSM66577L/577/579L (VDD = 2.4 to 3.6 V/4.5 to 5.5 V, Ta = –30 to +70°C) MSM66Q577L/Q577/Q579L (VDD = 2.7 to 3.3 V/4.5 to 5.5 V, Ta = –30 to +70°C) Parameter “H” output pin (1 pin) “H” output pins (sum total) “L” output pin (1 pin) Pin Symbol Min. Typ. All output pins IOH — — –2 Sum total of all output pins ∑IOH — — –40 IOL — — P0, P3, P11 Other ports Sum total of P0, P3, P11 Max. 10 5 80 Sum total of P1, P2, P4 “L” output pins (sum total) Sum total of P5, P6, P9 Sum total of P7, P8, P10, P14, P15 Sum total of all output pins ∑IOL — — Unit mA 50 140 [Note] Each of the family devices has unique pattern routes for the internal power and ground. Connect the power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation. 12/37 PEDL66579-03 1Semiconductor MSM66579 Family ELELCTRICAL CHARACTERISTICS DC Characteristics 1 (VDD = 4.5 to 5.5 V) (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter “H” input voltage *1 “H” input voltage *2,*3,*4,*5,*6,*7 “L” input voltage *1 “L” input voltage *2,*3,*4,*5,*6,*7 “H” output voltage Symbol Condition VIH — VIL VOH *2 “L” output voltage *1, *4 Input leakage current 0.44VDD — VDD+0.3 0.80VDD — VDD+0.3 –0.3 — 0.16VDD –0.3 — 0.2VDD IO = –400 µA VDD–0.4 — — IO = –2.0 mA VDD–0.6 — — IO = –200 µA VDD–0.4 — — IO = –2.0 mA VDD–0.6 — — IO = 3.2 mA — — 0.4 Input current *7 Output leakage current *1, *2, *4 Pull-up resistance V — — 0.8 — — 0.4 IO = 5.0 mA — — 0.8 — — 1/–1 IIH/IIL VI = VDD/0 V — — 1/–250 — — 15/–15 ILO VO = VDD/0 V — — ±10 µA Rpull VI = 0 V 25 50 100 kΩ — 5 — — 7 — During A/D operation — — 4 mA When A/D is stopped — — 10 µA OSC is stopped, XT is not used. VDD = 2 V, Ta = 25°C *8 — 0.2 10 OSC is stopped, XT is not used. *8 — 1 100 f = 30 MHz, No Load — 40 60 mA f = 30 MHz, No Load — 60 90 mA f = 32.768 kHz, No Load — 70 120 µA *3, *6 *5 Unit IO = 1.6 mA *2 Input current Input capacitance CI Output capacitance CO Analog reference supply current IREF Supply current (STOP mode) Max. IO = 10.0 mA VOL “L” output voltage Typ. — *1, *4 “H” output voltage Min. IDDS Supply current (HALT mode) IDDH Supply current IDD f = 1 MHz, Ta = 25°C *1: Applicable to P0 *2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15 *3: Applicable to P12 *4: Applicable to P3, p11 µA pF µA *5: Applicable to RES *6: Applicable to SELMBUS, EA, NMI *7: Applicable to OSC0 *8: Ports used as inputs are at VDD or 0 V. Other ports are unloaded. 13/37 PEDL66579-03 1Semiconductor MSM66579 Family DC Characteristics 2 (VDD = 2.4 to 3.6 V) MSM66577L/579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Parameter “H” input voltage *1 “H” input voltage *2,*3,*4,*5,*6,*7 “L” input voltage *1 “L” input voltage *2,*3,*4,*5,*6,*7 “H” output voltage Symbol Condition VIH — VIL — IO = –400 µA *1, *4 VOH “H” output voltage *2 “L” output voltage *1, *4 VOL “L” output voltage *2 Input leakage current *3, *6 Input current *5 Input current *7 Output leakage current *1, *2, *4 IIH/IIL Min. Typ. Max. 0.44VDD — VDD+0.3 0.80VDD — VDD+0.3 –0.3 — 0.16VDD –0.3 — 0.2VDD VDD–0.4 — — IO = –2.0 mA VDD–0.8 — — IO = –200 µA VDD–0.4 — — IO = –1.0 mA VDD–0.8 — — IO = 3.2 mA — — 0.5 IO = 5.0 mA — — 0.9 IO = 1.6 mA — — 0.5 IO = 2.5 mA — — 0.9 — — 1/–1 — — 1/–250 — — 15/–15 VI = VDD/0 V Unit V µA ILO VO = VDD/0 V — — ±10 µA Pull-up resistance Rpull VI = 0 V 40 100 200 kΩ Input capacitance CI — 5 — Output capacitance CO — 7 — Analog reference supply current IREF During A/D operation — — 2 mA When A/D is stopped — — 5 µA OSC is stopped, XT is not used. VDD = 2 V, Ta = 25°C *8 — 0.2 10 OSC is stopped, XT is not used. *8 — 1 100 f = 14 MHz, No Load — — TBD mA f = 14 MHz, No Load — — TBD mA f = 32.768 kHz, No Load — — TBD µA Supply current (STOP mode) IDDS Supply current (HALT mode) IDDH Supply current IDD f = 1 MHz, Ta = 25°C *1: Applicable to P0 *2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15 *3: Applicable to P12 *4: Applicable to P3, p11 pF µA *5: Applicable to RES *6: Applicable to SELMBUS, EA, NMI *7: Applicable to OSC0 *8: Ports used as inputs are at VDD or 0 V. Other ports are unloaded. 14/37 PEDL66579-03 1Semiconductor MSM66579 Family AC Characteristics 1 (VDD = 4.5 to 5.5 V) (1) Separate Bus Type External program memory control (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 30 MHz 33.3 — Clock pulse width (HIGH level) tφWH 13 — Clock pulse width (LOW level) tφWL 13 — PSEN pulse width tPW 2 tφ – 15 — PSEN pulse delay time tPD — 45 Address setup time tAS tφ – 25 — Address hold time tAH 0 9 Instruction setup time tIS 30 — Instruction hold time Read data access time CL = 50 pF tIH 0 — tACC — 3 tφ – 70 Unit ns Note: tφ = tcyc/2 tcyc CPUCLK tφWH tφWL PSEN tPD A0 to A19 tPW PC0 to 19 tAH tAS D0 to D7 INST0 to 7 tACC tIS tIH Bus timing during no wait cycle time 15/37 PEDL66579-03 1Semiconductor MSM66579 Family External data memory control (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 30 MHz 33.3 — Clock pulse width (HIGH level) tφWH 13 — Clock pulse width (LOW level) tφWL 13 — RD pulse width tRW 2 tφ – 15 — WR pulse width tWW 2 tφ – 15 — RD pulse delay time tRD — 45 WR pulse delay time tWD Address setup time tAS Address hold time — 45 tφ – 25 — tAH tφ – 3 tφ +3 Read data setup time tRS 30 — Read data hold time tRH 0 — Read data access time tACC — 3tφ –70 Write data setup time tWS 2tφ – 30 — Write data hold time tWH tφ – 3 tφ + 3 CL = 50 pF tcyc Unit ns Note: tφ = tcyc/2 CPUCLK tφWH tφWL RD tRD A0 to A19 tRW RAP0 to 19 tAS tAH DIN0 to 7 D0 to D7 tACC tRS tRH WR tWW tWD RAP0 to 19 A0 to A19 tAS D0 to D7 tAH DOUT0 to 7 tWS tWH Bus timing during no wait cycle time 16/37 PEDL66579-03 1Semiconductor MSM66579 Family (2) Multiplexed bus type External program memory control (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 30 MHz 33.3 — Clock pulse width (HIGH level) tφWH 13 — Clock pulse width (LOW level) tφWL 13 — ALE pulse width TAW 2 tφ – 10 — PSEN pulse width tPW 2 tφ – 14 — PSEN pulse delay time tPAD tφ – 10 tφ + 10 Low address setup time tALS 2tφ – 20 2tφ + 3 Low address hold time tALH tφ – 10 tφ + 10 High address setup time tAHS 3tφ – 30 4tφ + 3 High address hold time tAHH 0 tφ + 10 Instruction setup time tIS 24 — Instruction hold time tIH 0 tφ – 3 CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK tφWH ALE tφWL tAW PSEN tPAD AD0 to AD7 PC0 to 7 tALS A8 to A19 tPW INST0 to 7 tALH tIS tIH PC8 to 19 tAHS tAHH Bus timing during no wait cycle time 17/37 PEDL66579-03 1Semiconductor MSM66579 Family External data memory control (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 30 MHz 33.3 — Clock pulse width (HIGH level) tφWH 13 — Clock pulse width (LOW level) tφWL 13 — ALE pulse width tAW 2 tφ – 10 — RD pulse width tRW 2 tφ – 14 — WR pulse width tWW 2 tφ – 14 — RD pulse delay time tRAD tφ – 10 tφ +10 WR pulse delay time tWAD tφ – 10 tφ +10 Low address setup time tALS 2 tφ – 20 2 tφ +3 CL = 50 pF Low address hold time tALH tφ – 10 tφ +10 High address setup time tAHS 3 tφ – 30 3 tφ +3 High address hold time tAHH tφ – 10 tφ +10 Read data setup time tRS 24 — Read data hold time tRH 0 tφ – 3 Write data setup time tWS 2tφ – 12 — Write data hold time tWH tφ – 3 tφ + 3 tcyc Unit ns Note: tφ = tcyc/2 CPUCLK tφWH ALE tφWL tAW RD tRAD tRW A AD0 to AD7 DIN0 to 7 RAP0 to 7 tALS tALH A8 to A19 tRH tRS RAP8 to 19 tAHH tAHS WR tWAD AD0 to AD7 RAP0 to 7 tALS tALH A8 to A19 tWW DOUT0 to 7 tWS tWH RAP8 to 19 tAHS tAHH Bus timing during no wait cycle time 18/37 PEDL66579-03 1Semiconductor MSM66579 Family (3) Serial port control Serial ports 1 and 6 (SIO1 and 6) Master mode (Clock synchronous serial port) (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 30 MHz 33.3 — Serial clock cycle time tSCKC 4 tcyc — Output data setup time tSTMXS 2 tφ – 5 — Output data hold time tSTMXH 5 tφ – 10 — Input data setup time tSRMXS 13 — Input data hold time tSRMXH 0 — CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH 19/37 PEDL66579-03 1Semiconductor MSM66579 Family Slave mode (Clock synchronous serial port) (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 30 MHz 33.3 — Serial clock cycle time tSCKC 4 tcyc — Output data setup time tSTMXS 2 tφ – 15 — Output data hold time tSTMXH 4 tφ – 10 — Input data setup time tSRMXS 13 — Input data hold time tSRMXH 3 — CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH Measurement points for AC timing V DD 0V 0.8V 0.8V 0.2V 0.2V 20/37 PEDL66579-03 1Semiconductor MSM66579 Family Serial ports 4 and 5 (SIO4 and 5) Master mode (Clock synchronous serial port) VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 30 MHz 33.3 — Serial clock cycle time tSCKC 6 tcyc — Output data setup time tSTMXS 6 tφ – 5 — Output data hold time tSTMXH 4.5 tφ – 10 — Input data setup time tSRMXS 13 — Input data hold time tSRMXH 0 — CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK SIOCK tSCKC SDOUT (SIOO) tSTMXH tSTMXS SDIN (SIOI) tSRMXS tSRMXH 21/37 PEDL66579-03 1Semiconductor MSM66579 Family Slave mode (Clock synchronous serial port) (VDD = 4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 30 MHz 33.3 — Serial clock cycle time tSCKC 6 tcyc — Output data setup time tSTMXS 3 tφ – 15 — Output data hold time tSTMXH 6 tφ – 10 — Input data setup time tSRMXS 13 — Input data hold time tSRMXH 3 — CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK SIOCK tSCKC SDOUT (SIOO) tSTMXH tSTMXS SDIN (SIOI) tSRMXS tSRMXH Measurement points for AC timing VDD 0V 0.8 V 0.8 V 0.2 V 0.2 V 22/37 PEDL66579-03 1Semiconductor MSM66579 Family AC Characteristics 2 (VDD = 2.4 to 3.6 V) (1) Separate Bus Type External program memory control MSM66577L/579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 14 MHz 71.4 — Clock pulse width (HIGH level) tφWH 28 — Clock pulse width (LOW level) tφWL 28 — PSEN pulse width tPW 2 tφ – 20 — PSEN pulse delay time tPD Address setup time tAS Address hold time Instruction setup time Instruction hold time Read data access time — 75 tφ – 40 — tAH 0 18 tIS 60 — tIH 0 — tACC — 3 tφ – 120 CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK tφWH tφWL PSEN tPD A0 to A19 tPW PC0 to 19 tAH tAS D0 to D7 INST0 to 7 tACC tIS tIH Bus timing during no wait cycle time 23/37 PEDL66579-03 1Semiconductor MSM66579 Family External data memory control MSM66577L/579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 14 MHz 71.4 — Clock pulse width (HIGH level) tφWH 28 — Clock pulse width (LOW level) tφWL 28 — RD pulse width tRW 2 tφ – 20 — WR pulse width tWW 2 tφ – 20 — RD pulse delay time tRD — 75 WR pulse delay time tWD — 75 Address setup time tAS tφ – 40 — CL = 50 pF Address hold time tAH tφ – 6 tφ +6 Read data setup time tRS 60 — Read data hold time tRH 0 — Read data access time tACC — 3tφ –120 Write data setup time tWS 2tφ – 40 — Write data hold time tWH tφ – 6 tφ + 6 tcyc Unit ns Note: tφ = tcyc/2 CPUCLK tφWH tφWL RD tRD tRW RAP0 to 19 A0 to A19 tAH tAS D0 to D7 DIN0 to 7 tACC tRS tRH WR tWD tWW RAP0 to 19 A0 to A19 tAS D0 to D7 tAH DOUT0 to 7 tWS tWH Bus timing during no wait cycle time 24/37 PEDL66579-03 1Semiconductor MSM66579 Family (2) Multiplexed bus type External program memory control MSM66577L/579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Symbol Condition Min. Max. Cycle time Parameter tcyc fOSC = 14 MHz 71.4 — Clock pulse width (HIGH level) tφWH 28 — Clock pulse width (LOW level) tφWL 28 — ALE pulse width tAW 2 tφ – 15 — PSEN pulse width tPW 2 tφ – 18 — PSEN pulse delay time tPAD tφ – 6 tφ + 6 Low address setup time tALS 2tφ – 40 2tφ + 6 CL = 50 pF Low address hold time tALH tφ – 15 tφ + 15 High address setup time tAHS 3tφ – 50 4tφ + 6 High address hold time tAHH 0 tφ + 15 Instruction setup time tIS 58 — Instruction hold time tIH 0 tφ – 6 Unit ns Note: tφ = tcyc/2 tcyc CPUCLK tφWH ALE tφWL tAW PSEN tPAD AD0 to AD7 PC0 to 7 tALS A8 to A19 tPW INST0 to 7 tALH tIS tIH PC8 to 19 tAHS tAHH Bus timing during no wait cycle time 25/37 PEDL66579-03 1Semiconductor MSM66579 Family External data memory control MSM66577L/579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 30 MHz 71.4 — Clock pulse width (HIGH level) tφWH 28 — Clock pulse width (LOW level) tφWL 28 — ALE pulse width tAW 2 tφ – 18 — RD pulse width tRW 2 tφ – 18 — WR pulse width tWW 2 tφ – 18 — RD pulse delay time tRAD tφ – 6 tφ +6 WR pulse delay time tWAD tφ – 6 tφ +6 Low address setup time tALS 2 tφ – 12 2 tφ Low address hold time tALH tφ – 6 tφ +6 High address setup time tAHS 3 tφ – 12 3 tφ +12 High address hold time tAHH tφ – 6 tφ +6 Read data setup time tRS 48 — CL = 50 pF Read data hold time tRH 0 tφ – 6 Write data setup time tWS 2tφ – 24 — Write data hold time tWH tφ – 6 tφ + 6 Unit ns Note: tφ = tcyc/2 tcyc CPUCLK tφWH ALE tφWL tAW RD tRAD tRW A AD0 to AD7 DIN0 to 7 RAP0 to 7 tALS tALH A8 to A19 tRH tRS RAP8 to 19 tAHH tAHS WR tWAD AD0 to AD7 RAP0 to 7 tALS tALH A8 to A19 tWW DOUT0 to 7 tWS tWH RAP8 to 19 tAHS tAHH Bus timing during no wait cycle time 26/37 PEDL66579-03 1Semiconductor MSM66579 Family (3) Serial port control Serial ports 1 and 6 (SIO1 and 6) Master mode (Clock synchronous serial port) MSM66577L/579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 14 MHz 71.4 — Serial clock cycle time tSCKC 4 tcyc — Output data setup time tSTMXS 2 tφ – 10 — Output data hold time tSTMXH 5 tφ – 20 — Input data setup time tSRMXS 21 — Input data hold time tSRMXH 0 — CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH 27/37 PEDL66579-03 1Semiconductor MSM66579 Family Slave mode (Clock synchronous serial port) MSM66577L/579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Parameter Cycle time Symbol tcyc Condition fOSC = 14 MHz Min. 71.4 Max. — Serial clock cycle time tSCKC 4 tcyc — Output data setup time tSTMXS 2 tφ – 30 — Output data hold time tSTMXH 4 tφ – 20 — CL = 50 pF Input data setup time tSRMXS 21 — Input data hold time tSRMXH 7 — Unit ns Note: tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH Measurement points for AC timing VDD 0V 0.8 V 0.8 V 0.2 V 0.2 V 28/37 PEDL66579-03 1Semiconductor MSM66579 Family Serial ports 4 and 5 (SIO4 and 5) Master mode (Clock synchronous serial port) MSM66577L/ 579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 14 MHz 71.4 — Serial clock cycle time tSCKC 5.6 tcyc — Output data setup time tSTMXS 5.6 tφ – 10 — Output data hold time tSTMXH 4.2 tφ – 20 — Input data setup time tSRMXS 21 — Input data hold time tSRMXH 0 — CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK SIOCK tSCKC SDOUT (SIOO) tSTMXH tSTMXS SDIN (SIOI) tSRMXS tSRMXH 29/37 PEDL66579-03 1Semiconductor MSM66579 Family Slave mode (Clock synchronous serial port) MSM66577L/579L (VDD = 2.4 to 3.6 V, Ta = –30 to +70°C) MSM66Q577L/Q579L (VDD = 2.7 to 3.3 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 14 MHz 71.4 — Serial clock cycle time tSCKC 5.6 tcyc — Output data setup time tSTMXS 2.8 tφ – 30 — Output data hold time tSTMXH 5.6 tφ – 20 — Input data setup time tSRMXS 21 — Input data hold time tSRMXH 7 — CL = 50 pF Unit ns Note: tφ = tcyc/2 tcyc CPUCLK SIOCK tSCKC SDOUT (SIOO) tSTMXH tSTMXS SDIN (SIOI) tSRMXS tSRMXH Measurement points for AC timing VDD 0V 0.8 V 0.8 V 0.2 V 0.2 V 30/37 PEDL66579-03 1Semiconductor MSM66579 Family A/D Converter Characteristics 1 (VDD = 4.5 to 5.5 V) (Ta = –30 to 70°C, VDD = VREF = 4.5 to 5.5 V, AGND = GND = 0 V) Parameter Resolution Symbol Condition Min. Typ. Max. Unit n Refer to measurement circuit 1 — 10 — Bit — — ±3 Analog input source impedance — — ±2 — — +3 — — –3 — — ±1 10.7 — — Linearity error EL Differential linearity error ED Zero scale error EZS Full-scale error EFS tconv = 10.7 µs Cross talk ECT Refer to measurement circuit 2 Conversion time tCONV RI ≤ 5 kΩ Set according to ADTM set data LSB µs/ch A/D Converter Characteristics 2 (VDD = 2.4 to 3.6 V) (Ta = –30 to 70°C, VDD = VREF = 2.7 to 3.6 V, AGND = GND = 0 V) Parameter Symbol Condition Min. Typ. Resolution n EL Refer to measurement circuit 1 — Linearity error — Differential linearity error ED Zero scale error EZS Analog input source impedance Full-scale error EFS tconv = 10.7 µs Cross talk ECT Refer to measurement circuit 2 Conversion time tCONV RI ≤ 5 kΩ Set according to ADTM set data Max. Unit 10 — Bit — ±3 — — ±2 — — +3 — — –3 — — ±1 27.4 — — LSB µs/ch [Note] The A/D conversion time should be set according to ADTV set data. Set the number of conversion clock cycles according to frequencies of operation so that the A/D conversion time is 32 µs or more. 31/37 PEDL66579-03 1Semiconductor MSM66579 Family Reference voltage VREF 0.1 µF – 47 µF + + 0.1 µF RI AI0 to AI7 AGND + +5 V VDD GND 47 µF 0V Analog input CI RI (impedance of analog input source) ≤5 kΩ CI ≅ 0.1 µF Measurement Circuit 1 32/37 PEDL66579-03 1Semiconductor – MSM66579 Family 5 kΩ AI0 + AI1 Analog input 0.1 µF to Cross talk is the difference between the A/D conversion results when the same analog input is applied to AI0 through AI7 and the A/D conversion results of the circuit to the left. AI7 VREF or AGND Measurement Circuit 2 Definition of Terminology 1. Resolution Resolution is the value of minimum discernible analog input. With 10 bits, since 210 = 1024, resolution of (VREF – AGND) ÷ 1024 is possible. 2. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of a 10-bit A/D converter (not including quantization error). Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024 equal steps. 3. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB = (VREF – AGND) ÷ 1024. Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000H to 001H. 5. Full-scale error Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 3FEH to 3FFH. 33/37 PEDL66579-03 1Semiconductor MSM66579 Family D/A Converter Characteristics (VDD = 2.4 to 3.6 V/4.5 to 5.5 V, Ta = –30 to +70°C) Parameter Symbol Resolution n Linearity error EL Absolute precision — Conversion time Analog output impedance Condition — Min. Typ. Max. Unit — — 8 Bit — — 1 — — 2 LSB tCONV CL = 50 pF — 20 50 µs — — — 20 — kΩ Definition of Terminology 1. Resolution Resolution is the value of minimum discernible analog output. With 8 bits, since 28 = 256, resolution of (VDD – GND) ÷ 256 is possible. 2. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of an 8-bit D/A converter. Ideal conversion characteristics can be obtained by dividing the voltage between VDD and GND into 256 equal steps. 3. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog input voltage that corresponds to 1 converted bit of digital input is 1LSB = (VDD – GND) ÷ 256. Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. Absolute precision Absolute precision is a gross error including a linearity error and the effect of noise. 34/37 PEDL66579-03 1Semiconductor MSM66579 Family PACKAGE DIMENSIONS TQFP100-P-1414-0.50-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 m or more 0.55 TYP. Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 35/37 PEDL66579-03 1Semiconductor MSM66579 Family (Unit:mm) QFP100-P-1420-0.65-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 m or more 1.29 TYP. Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 36/37 PEDL66579-03 1Semiconductor MSM66579 Family NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 1999 Oki Electric Industry Co., Ltd. 37/37