SED1336 CMOS GRAPHIC LCD/TV CONTROLLER Medium-Scale LCD • For Output to LCD-Screen • Virtual Screen Display RAM • Enhanced Control • Simultaneous LCDFunction & TV Display • ■ DESCRIPTION The SED1336 is a CMOS low-power dot matrix liquid crystal graphic display controller with built-in TV support. The built-in TV support IC is capable of displaying characters and graphic images simultaneously on TV monitors and flat panels. The SED1336 has a built-in TV control circuit that generates either NTSC or PAL system synchronous signals, memory. The device stores the display data in external SRAM that is sent by an 8-bit microcomputer, and generates all the control signals required by the LCD drivers. The controller incorporates an internal character generator ROM which supports user-defined characters. An external CG ROM can also be supported to provide additional characters. The SED1336 can be interfaced to high-speed microprocessors such as the Intel 80xx family or the Motorola 68xx family. The controller supports a set of commands that allow the user to create a layered display of characters and graphics. ■ FEATURES • Low-power CMOS fabrication with both Intel 80XX and Motorola • Compatible 68XX high-speed MPU • Display duty: • • • Selectable display synthesis • Programmable cursor movement • Multimode display: LCD ............... 1/2 to 1/256 can be selected TV ...................................... 256 × 200 dots Internal and external character generator ROM Simultaneous LCD and TV operation • • • 2 layers of overlapping character and graphic 3 layers of overlapping graphic Supports 64K bytes of memory Single power supply ..................... 3.0V to 5.5V Package ................... Plastic QFP6-60 pin (F0A) ■ SYSTEM BLOCK DIAGRAM DATA CPU CONTROL SED1336F MONO LCD TV SRAM 153 SED1336 ■ BLOCK DIAGRAM Display Address Controller Refresh Address Counter Dot Counter TV Controller CG ROM OSC XD D0 to D7 A0, CS RD, WR RES SEL1 SEL0 XD0 to XD3 Layered Display Controller MPU Interface VD4 VD5 VD6 VD7 SNC YD YDIS WF LP VSS XSCL VSD XD0 XD1 XD2 ■ PIN ASSIGNMENT DIAGRAM 45 46 31 30 SED1336F0A Index 16 15 60 1 VA5 VA4 VA3 VA2 VA1 VA0 VWR VCE VRD RES NC NC RD WR NT/PL VD3 VD2 VD1 VD0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 NC XSCL YDIS LCD Controller 154 XD3 D7 D6 D5 D4 D3 D2 D1 D0 VDD A0 CS XD XG SEL1 XG Cursor Address Controller I/O Register VSD VD0 to VD7 VCE VA0 to VA15 VRAM Interface LCD WITH SED1180/SED1190 TV LP, WF External CG ROM CG RAM SNC Video RAM SED1336 ■ PIN DESCRIPTION Name VA0 to VA5 VA6 to VA15 VWR VCE VRD RES NC CLO Number 6 to 1 59 to 50 7 8 9 10 11, 60 12 Output VRAM address bus Output Output Output Input — Output RD 13 Input WR 14 Input 15 16 17 18 19 20 21 22 to 29 30 to 33 34 35 36 37 38 39 40 41 42 to 49 Input Input Input Output Input Input Supply Input/output Output Output Output Supply Output Output Output Output Output Input/output VRAM write signal Memory control signal VRAM read signal Reset No connection Clock output 8080-family: Read signal 6800-family: Enable clock (E) 8080-family: Write signal 6800-family: R/W signal NTSC or PAL TV mode select 8080- or 6800-family interface select Oscillator connection Oscillator connection Chip select Data type select 3.0 to 5.5V supply Data bus Data to LCD X-driver Video data Data shift clock Ground Latch pulse Frame signal Power-down signal when display is blanked Scan start pulse TV sync signal VRAM data bus NT/PL SEL1 OSC1 OSC2 CS A0 VDD D0 to D7 XD0 to XD3 VSD XSCL VSS LP WF YDIS YD SNC VD0 to VD7 Type Description ■ ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • Parameter Supply voltage range Input voltage range Power dissipation Operating temperature range Storage temperature range Soldering temperature (10 seconds). See note 1. Symbol VDD VIN PD Topr Tstg Tsolder Rating –0.3 to 7.0 –0.3 to VDD + 0.3 300 –20 to 75 –65 to 150 260 Unit V V mW °C °C °C 1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique that does not heatstress the package. 2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take appropriate care with the power supply and the layout of the supply lines. 3. All supply voltages are referenced to VSS = 0V. 155 SED1336 • DC Electrical Characteristics Parameter Supply voltage Register data retention voltage Input leakage current Output leakage current Operating supply current Quiescent supply current VDD = 4.5 to 5.5V, VSS = 0V, Ta = –20 to 75°C Symbol VDD VHO ILI ILO Iopr IQ Condition VI = VDD. See note 6. VI = VSS. See note 6. See note 4. Sleep mode, VOSC1 = VCS = VRD = VDD Min 4.5 2.0 — — — Typ 5.0 — 0.05 0.10 11 Max 5.5 6.0 2.0 5.0 15 Unit V V µA µA mA — 0.05 20.0 µA Oscillator frequency External clock frequency Oscillator feedback resistance TTL HIGH-level input voltage LOW-level input voltage fOSC fCL Rf Measured at crystal, 47.5% duty cycle. See note 7. 1.0 1.0 0.5 — — 1.0 10.0 10.0 3.0 MHz MHz MΩ VIHT VILT 0.8VDD VSS — — VDD 0.2VDD V V HIGH-level output voltage VOHT 2.4 — — V LOW-level output voltage CMOS HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Open-drain LOW-level output voltage Schmitt-trigger Rising-edge threshold voltage Falling-edge threshold voltage VOLT See note 1. See note 1. IOH = –5.0 mA. See note 1. IOL = 5.0 mA. See note 1. — — VSS + 0.4 V — — — — VDD 0.2VDD — VSS + 0.4 V V V V VIHC VILC VOHC VOLC See note 2. 0.8VDD See note 2. VSS IOH = –2.0 mA. See note 2. VDD – 0.4 IOH = 1.6 mA. See note 2. — VOLN IOL = 6.0 mA. See note 5. — — VSS + 0.4 V VT+ VT– See note 3. See note 3. 0.5VDD 0.2VDD 0.7VDD 0.3VDD 0.8VDD 0.5VDD V V Notes: 1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs. 5. SNC and VSD are n-channel, open-drain outputs. The voltage on the outputs should not exceed VDD as internal diodes connect the pins to VDD (SED1336F only). 2. SEL1 and NT/PL are CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS and CLO are CMOS-level outputs. 3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF. 156 6. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 7. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to reduce leakage currents. SED1336 VDD = 3.0 to 4.5V, VSS = 0V, Ta = –20 to 75°C Parameter Supply voltage Register data retention voltage Input leakage current Output leakage current Symbol VDD VHO ILI ILO Condition See note 8. VI = VDD. See note 6. VI = VSS. See note 6. Min 3.0 2.0 — — — — Typ 3.5 — 0.05 0.10 3.5 — Max 4.5 6.0 2.0 5.0 — 7.0 Unit V V µA µA Operating supply current Iopr VDD = 3.5V. See note 4. See note 4. Quiescent supply current IQ Sleep mode, VOSC1 = VCS = VRD = VDD — 0.05 20.0 µA Oscillator frequency External clock frequency Oscillator feedback resistance TTL HIGH-level input voltage LOW-level input voltage fOSC fCL Rf Measured at crystal, 47.5% duty cycle. See note 7. 1.0 1.0 0.7 — — — 8.0 8.0 3.0 MHz MHz MΩ VIHT VILT 0.8VDD VSS — — VDD 0.2VDD V V HIGH-level output voltage VOHT 2.4 — — V LOW-level output voltage CMOS HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Open-drain LOW-level output voltage Schmitt-trigger Rising-edge threshold voltage Falling edge threshold voltage VOLT See note 1. See note 1. IOH = –3.0 mA. See note 1. IOL = 3.0 mA. See note 1. — — VSS + 0.4 V — — — — VDD 0.2VDD — VSS + 0.4 V V V V VIHC VILC VOHC VOLC See note 2. 0.8VDD See note 2. VSS IOH = –2.0 mA. See note 2. VDD – 0.4 IOH = 1.6 mA. See note 2. — mA VOLN IOL = 6.0 mA. See note 5. — — VSS + 0.4 V VT+ VT– See note 3. See note 3. 0.5VDD 0.2VDD 0.7VDD 0.3VDD 0.8VDD 0.5VDD V V Notes: 1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs. 5. SNC and VSD are n-channel, open-drain outputs. The voltage on the outputs should not exceed VDD as internal diodes connect the pins to VDD. 2. SEL1 and NT/PL are CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS and CLO are CMOS-level outputs. 6. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 7. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to reduce leakage currents. 4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF. 8. VDD = 2.7 to 4.5V (SED1335F) 157 SED1336 • ° Timing Diagrams 8080-Family Interface Timing AO, CS tAW8 tAH8 tCYC WR, RD tCC tDH8 tDS8 D0 to D7 (Write) tACC8 tOH8 D0 to D7 (Read) Ta = –20 to 75°C Signal A0, CS WR, RD D0 to D7 Symbol Parameter tAH8 tAW8 tCYC tCC tDS8 tDH8 tACC8 tOH8 Address hold time Address setup time System cycle time Strobe pulsewidth Data setup time Data hold time RD access time Output disable time VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V min max min max 10 — 10 — 0 — 0 — See note — See note — 120 — 140 — 120 — 120 — 5 — 5 — — 50 — 70 10 50 10 50 Note: For memory control and system control commands: tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245 For all other commands: tCYC8 = 4tC + tCC + 30 158 Unit Condition ns ns ns ns ns ns ns ns CL = 100 pF SED1336 ° 6800-Family Interface Timing E tCYC tAW6 tEW R/W tAH6 AO, CS tDH6 tDS6 D0 to D7 (Write) tACC6 tOH6 D0 to D7 (Read) Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH. Ta = –20 to 75°C Signal Symbol Parameter A0, CS, R/W tCYC6 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6 tEW System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable pulsewidth D0 to D7 E VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V min max min max See note — See note — 0 — 10 — 0 — 0 — 100 — 120 — 0 — 0 — 10 50 10 70 — 85 — 120 120 — 140 — Note: For memory control and system control commands: tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245 For all other commands: tCYC6 = 4tC + tEW + 30 159 Unit Condition ns ns ns ns ns ns ns ns CL = 100 pF SED1336 ° Display Memory Read Timing EXTΦ0 tC tW tCE tW VCE tCYR VA0 to VA15 tASC tAHC tRCH VRD tRCS tCEA tCE3 tOH2 tACV VD0 to VD7 (SED1335F) Ta = –20 to 75°C Signal Symbol EXT φ0 tC tW VCE tCE tCYR VA0 to VA15 tASC tAHC tRCS VRD tRCH VD0 to VD7 tACV tCEA tOH2 tCE3 Parameter VDD = 4.5 to 5.5V min max 100 — Clock period VCE HIGH-level tC – 50 — pulsewidth VCE LOW-level 2tC – 30 — pulsewidth Read cycle time 3tC — Address setup time to — tC – 70 falling edge of VCE Address hold time from 2tC – 30 — falling edge of VCE Read cycle setup time tC – 45 — to falling edge of VCE Read cycle hold time 0.5tC — from rising edge of VCE Address access time — 3tC – 100 VCE access time — 2tC – 80 Output data hold time 0 — VCE to data off time 0 — 160 VDD = 3.0 to 4.5V min max 125 — Unit Condition ns tC – 50 — ns 2tC – 30 — ns 3tC — ns tC – 100 — ns 2tC – 40 — ns tC – 55 — ns 0.5tC — ns — — 0 0 3tC – 110 2tC – 85 — — ns ns ns ns CL = 100 pF SED1336 ° Display Memory Write Timing EXTφ0 tC tCA tW tCE VCE tASC tAHC tCYW VA0 to VA15 tAS tWSC tAH2 tWHC VRW tDH2 tDSC tDHC VD0 to VD7 Ta = –20 to 75°C Signal Symbol Parameter EXT φ0 tC Clock period VCE HIGH-level pulsewidth VCE LOW-level pulsewidth Write cycle time Address hold time from falling edge of VCE Address setup time to falling edge of VCE Address hold time from rising edge of VCE Address setup time to falling edge of VWR Address hold time from rising edge of VWR Write setup time to falling edge of VCE Write hold time from falling edge of VCE Data input setup time to falling edge of VCE Data input hold time from falling edge of VCE Data hold time from rising edge of VWR tW VCE tCE tCYW tAHC tASC VA0 to VA15 tCA tAS tAH2 tWSC VWR tWHC tDSC VD0 to VD7 tDHC tDH2 VDD = 4.5 to 5.5V min max 100 — VDD = 3.0 to 4.5V min max 125 — tC – 50 — tC – 50 — ns 2tC – 30 — 2tC – 30 — ns 3tC — 3tC — ns 2tC – 30 — 2tC – 40 — ns tC – 70 — tC – 100 — ns 0 — 0 — ns 0 — 0 — ns 10 — 10 — ns tC – 80 — tC – 110 — ns 2tC – 20 — 2tC – 20 — ns tC – 85 — tC – 120 — ns 2tC – 30 — 2tC – 30 — ns 5 50 5 50 ns Unit Condition ns CL = 100 pF Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read from the memory is placed on the bus. 161 SED1336 ° SLEEP IN Command Timing VCE SLEEP IN write SYSTEM SET write tWRL WR (command input) tWRD YDIS Ta = –20 to 75°C Signal Symbol tWRD WR tWRL Parameter VCE falling-edge delay time YDIS falling-edge delay time VDD = 4.5 to 5.5V min max VDD = 3.0 to 4.5V min max Unit *1 — *1 — ns — *2 — *2 ns Condition CL = 100 pF 1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation) 2. tWRL = 36tC × [TC/R] × [L/F] + 70 ° External Oscillator Signal Timing tRCL tFCL EXTφ0 tWL tWH tCL Ta = –20 to 75°C Signal EXT φ0 Symbol Parameter tRCL tFCL External clock rise time External clock fall time External clock HIGH-level pulsewidth External clock LOW-level pulsewidth External clock period tWH tWL tC 1. (tC – tRCL – tFCL) × 475 < tWH, tWL 1000 2. (tC – tRCL – tFCL) × 525 > tWH, tWL 1000 VDD = 4.5 to 5.5V min max — 15 — 15 VDD = 3.0 to 4.5V min max — 15 — 15 Unit ns ns *1 *2 *1 *2 ns *1 *2 *1 *2 ns 100 — 125 — ns 162 Condition SED1336 ° LCD Output Timing The following characteristics are for a 1/64 duty cycle. Row 62 63 64 1 2 3 4 60 61 62 63 64 LP 1 frame time YD WF WF 1 line time Row 64 Row 1 Row 2 LP XSCL XD0 to XD3 (14) (15) (16) tr (1) (15) (16) (1) (2) (3) tWX tf (15) (16) tCX XSCL tDS tDH tLS XD0 to XD3 tWL tLD LP tDHY tDF WF(B) YD 163 (1) SED1336 Ta = –20 to 75°C Signal Symbol tr tf XSCL XD0 to XD3 LP WF YD tCX tWX tDH tDS tLS tWL tLD tDF tDHY VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V min max min max Rise time — 30 — 35 Fall time — 30 — 35 Shift clock cycle time 4tC — 4tC — XSCL clock pulsewidth 2tC – 60 — 2tC – 60 — X data hold time 2tC – 50 — 2tC – 50 — X data setup time 2tC – 100 — 2tC – 100 — Latch data setup time 2tC – 50 — 2tC – 50 — LP pulsewidth 4tC – 80 — 4tC – 100 — LP delay time from XSCL 0 — 0 — Permitted WF delay — 50 — 50 Y data hold time 2tC – 20 — 2tC – 20 — Parameter Unit ns ns ns ns ns ns ns ns ns ns ns Condition CL = 100 pF Note: The SED1336F reads display memory data from the address of the top left corner of the display screen, then scans horizontally until it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data is sent starting from the left side of the display line. 164