E2E0059-19-81
¡ Semiconductor
MSM63184A
¡ Semiconductor
This version:MSM63184A
Aug. 1999
4-Bit Microcontroller with Built-in 640-Dot Matrix LCD Drivers, Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The MSM63184A is an enhanced version of the MSM63184B in which supply currents have been
improved.
The MSM63184A is a CMOS 4-bit microcontroller with built-in 640-dot matrix LCD drivers and
operates at 0.9 V (min.). The MSM63184A is suitable for applications such as games, toys,
watches, etc. which are provided with an LCD display.
The MSM63184A is an M6318x series mask ROM-version product of OLMS-63K family, which
employs Oki's original CPU core nX-4/250.
The MSM63P180 is the one-time-programmable ROM version of MSM63188A, having one-time
PROM (OTP) as internal program memory.
The MSM63P180 is used to evaluate the software development.
FEATURES
• Rich instruction set
439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: 32.768 kHz crystal oscillator
: 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
8K words
Basic instruction length is 16 bits/1 word
• Data memory space
640 nibbles
• External data memory space
Expandable beyond 64 Kbytes by using I/O port.
1/29
¡ Semiconductor
• Stack level
Call stack level
Register stack level
MSM63184A
: 8 levels
: 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output/high-impedance output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
Input port
: 2 ports ¥ 4 bits
Output port
: 4 ports ¥ 4 bits
Input-output port
: 5 ports ¥ 4 bits
• Buzzer function
Buzzer output
Buzzer output modes
: 0.946 to 5.461 kHz (adjustable in 15 steps)
: Intermittent sound 1, 2; simple sound; continuous sound
• LCD driver
Number of segments
: 640 Max. (40 SEG ¥ 16 COM)
1/1 to 1/16 duty
1/4 or 1/5 bias (regulator built-in)
Selectable as all-on mode/all-off mode/power down mode/normal display mode
Adjustable contrast
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage
: Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V,
2.20 ±0.20 V or 2.80 ±0.30 V
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
2/29
¡ Semiconductor
MSM63184A
• Timers and counter
Watchdog timer ¥ 1
Overflows in 2 sec.
100 Hz timer ¥ 1
Measurable in steps of 1/100 sec.
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Shift register
Shift clock
Data length
• Interrupt sources
External interrupt
Internal interrupt
• Operating voltage
When backup used
When backup not used
• Package:
128-pin plastic QFP (QFP128-P-1420-0.50-K)
Chip
: 1x or 1/2x system clock; external clock
: 8 bits
: 3
: 7 (watchdog timer interrupt is a nonmaskable interrupt)
: 0.9 to 2.7 V
(Low-speed clock operating)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
: 1.8 to 5.5 V
(Operating frequency: 300 to 500 kHz)
2.2 to 5.5 V
(Operating frequency: 300 kHz to 1 MHz)
2.7 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
: (Product name: MSM63184A-xxxGS-K)
: (Product name: MSM63184A-xxx)
xxx indicates a code number.
Differences Between the MSM63184B and the MSM63184A
The MSM63184A has the following improved characteristics.
• Supply currents (IDD1, IDD2, IDD3) in DC characteristics
• The VDDL voltage during a halt of high-speed clock oscillation
3/29
¡ Semiconductor
MSM63184A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied
to the circuits corresponding to the signal names inside
from VDDI (power supply for
interface).
nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
SP
C
ALU
RSP
G
MIE
INSTRUCTION
DECODER
STACK
CAL: 8-level
REG: 16-level
PC
Z
ROM
8KW
BUS
CONTROL
D0-7*
EXTMEM
A0-15*
RD*
WR*
IR
RAM
640N
INT
1
SFT
INT184
TST1
TST2
RST
INT
4
BUZZER
TBC
TST
DATA BUS
RESET
OSC
INT
1
INT
1
INPUT
PORT
CB1
OUTPUT
PORT
P6.0-P6.3
P8.0-P8.3
BACKUP
P9.0-P9.3
I/O
PORT
INT
2
VDD2
PA.0-PA.3
PD.0-PD.3
VDD3
PE.0-PE.3
BIAS
VDD5
C1
VDDL
P5.0-P5.3
P7.0-P7.3
WDT
CB2
C2
P1.0-P1.3
P4.0-P4.3
VDD1
VDD4
P0.0-P0.3
100HzTC
VDDH
VDD
BD
BDB
INT
1
BLD
XT0
XT1
OSC0
OSC1
TBCCLK*
HSCLK*
SIN*
SOUT*
SCLK*
LCLK*
FRAME*
LCD
&
DSPR
COM1-16
SEG0-39
VDDI
VSS
4/29
¡ Semiconductor
MSM63184A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
(NC)
P6.0
P6.1
P6.2
P6.3
P1.0
P1.1
P1.2
P1.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P8.0
P8.1
P8.2
P8.3
PE.0
PE.1
PE.2
PE.3
PD.0
PD.1
PD.2
PD.3
P0.0
P0.1
P0.2
P0.3
P4.0
P4.1
P4.2
P4.3
P5.0
(NC)
VSS
VDD1
VDD2
VDD3
VDD4
VDD5
C1
C2
VDDH
CB1
CB2
(NC)
VDD
VDDL
OSC1
OSC0
RESET
XT1
XT0
TST2
TST1
P5.3
P5.2
P5.1
(NC)
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
SEG38
SEG39
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
VDDI
BDB
BD
P7.0
P7.1
P7.2
P7.3
(NC)
PIN CONFIGURATION (TOP VIEW)
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
5/29
¡ Semiconductor
MSM63184A
PAD CONFIGURATION
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P6.0
P6.1
P6.2
P6.3
P1.0
P1.1
P1.2
P1.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P8.0
P8.1
P8.2
P8.3
PE.0
PE.1
PE.2
PE.3
PD.0
PD.1
PD.2
PD.3
P0.0
P0.1
P0.2
P0.3
P4.0
P4.1
P4.2
P4.3
P5.0
Pad Layout
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
P5.1
P5.2
P5.3
TST1
TST2
XT0
XT1
RESET
OSC0
OSC1
VDDL
VDD
CB2
CB1
VDDH
C2
C1
VDD5
VDD4
VDD3
VDD2
VDD1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Y
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P7.3
P7.2
P7.1
P7.0
BD
BDB
VDDI
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG39
SEG38
SEG37
Chip Size
Chip Thickness
Coordinate Origin
Pad Hole Size
Pad Size
Minimum Pad Pitch
:
:
:
:
:
:
X
5.35 mm ¥ 4.66 mm
350 mm (typ.)
Chip center
100 mm ¥ 100 mm
110 mm ¥ 110 mm
140 mm
Note: The chip substrate voltage is VSS.
6/29
¡ Semiconductor
MSM63184A
Pad Coordinates
Pad No.
Pad
Pad
Pad
X (µm) Y (µm) Pad No.
X (µm) Y (µm) Pad No.
X (µm) Y (µm)
Name
Name
Name
1
SEG36
–2520
–2135
42
VDD4
2530
–1065
83
P9.2
–560
2135
2
SEG35
–2380
–2135
43
VDD5
2530
–915
84
P9.1
–700
2135
3
SEG34
–2240
–2135
44
C1
2530
–765
85
P9.0
–840
2135
4
SEG33
–2100
–2135
45
C2
2530
–615
86
PA.3
–980
2135
5
SEG32
–1960
–2135
46
VDDH
2530
–465
87
PA.2
–1120
2135
6
SEG31
–1820
–2135
47
CB1
2530
–315
88
PA.1
–1260
2135
7
SEG30
–1680
–2135
48
CB2
2530
–165
89
PA.0
–1400
2135
8
SEG29
–1540
–2135
49
VDD
2530
–15
90
P1.3
–1540
2135
9
SEG28
–1400
–2135
50
VDDL
2530
135
91
P1.2
–1680
2135
10
SEG27
–1260
–2135
51
OSC1
2530
285
92
P1.1
–1820
2135
11
SEG26
–1120
–2135
52
OSC0
2530
435
93
P1.0
–1960
2135
12
SEG25
–980
–2135
53
RESET
2530
585
94
P6.3
–2100
2135
13
SEG24
–840
–2135
54
XT1
2530
735
95
P6.2
–2240
2135
14
SEG23
–700
–2135
55
XT0
2530
885
96
P6.1
–2380
2135
15
SEG22
–560
–2135
56
TST2
2530
1030
97
P6.0
–2520
2135
16
SEG21
–420
–2135
57
TST1
2530
1170
98
P7.3
–2530
1607
17
SEG20
–280
–2135
58
P5.3
2530
1328
99
P7.2
–2530
1467
18
SEG19
–140
–2135
59
P5.2
2530
1468
100
P7.1
–2530
1327
19
SEG18
0
–2135
60
P5.1
2530
1608
101
P7.0
–2530
1187
20
SEG17
140
–2135
61
P5.0
2520
2135
102
BD
–2530
1029
21
SEG16
280
–2135
62
P4.3
2380
2135
103
BDB
–2530
889
22
SEG15
420
–2135
63
P4.2
2240
2135
104
VDDI
–2530
749
23
SEG14
560
–2135
64
P4.1
2100
2135
105
COM1
–2530
609
24
SEG13
700
–2135
65
P4.0
1960
2135
106
COM2
–2530
469
25
SEG12
840
–2135
66
P0.3
1820
2135
107
COM3
–2530
329
26
SEG11
980
–2135
67
P0.2
1680
2135
108
COM4
–2530
189
27
SEG10
1120
–2135
68
P0.1
1540
2135
109
COM5
–2530
49
28
SEG9
1260
–2135
69
P0.0
1400
2135
110
COM6
–2530
–91
29
SEG8
1400
–2135
70
PD.3
1260
2135
111
COM7
–2530
–231
30
SEG7
1540
–2135
71
PD.2
1120
2135
112
COM8
–2530
–371
31
SEG6
1680
–2135
72
PD.1
980
2135
113
COM9
–2530
–511
32
SEG5
1820
–2135
73
PD.0
840
2135
114
COM10
–2530
–651
33
SEG4
1960
–2135
74
PE.3
700
2135
115
COM11
–2530
–791
34
SEG3
2100
–2135
75
PE.2
560
2135
116
COM12
–2530
–931
35
SEG2
2240
–2135
76
PE.1
420
2135
117
COM13
–2530
–1071
36
SEG1
2380
–2135
77
PE.0
280
2135
118
COM14
–2530
–1211
37
SEG0
2520
–2135
78
P8.3
140
2135
119
COM15
–2530
–1351
38
VSS
2530
–1665
79
P8.2
0
2135
120
COM16
–2530
–1491
39
VDD1
2530
–1515
80
P8.1
–140
2135
121
SEG39
–2530
–1631
40
VDD2
2530
–1365
81
P8.0
–280
2135
122
SEG38
–2530
–1771
41
VDD3
2530
–1215
82
P9.3
–420
2135
123
SEG37
–2530
–1970
7/29
¡ Semiconductor
MSM63184A
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63184A are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol
Power
Supply
Pin
Type
VDD
52
—
Positive power supply
VSS
40
—
Negative power supply
Description
VDD1
41
Power supply pins for LCD bias (internally generated).
VDD2
42
Capacitors (0.1 mF) should be connected between these pins and
VDD3
43
VDD4
44
VDD5
45
C1
C2
—
VSS.
46
—
Capacitor connection pins for LCD bias generation.
47
—
A capacitor (0.1 mF) should be connected between C1 and C2.
VDDI
110
—
VDDL
53
—
VDDH
48
—
CB1
49
—
Pins to connect a capacitor for voltage multiplier.
CB2
50
—
A capacitor (1.0 mF) should be connected between CB1 and CB2.
XT0
58
I
XT1
57
O
and CG (5 to 25 pF) should be connected between XT0 and VSS.
OSC0
55
I
High-speed clock oscillation pins.
OSC1
54
O
oscillation resistor (ROS) should be connected to these pins.
TST1
60
I
Input pins for testing.
TST2
59
I
Positive power supply pin for external interface
(power supply for input, output, and input-output ports)
Positive power supply pin for internal logic (internally generated).
A capacitor (0.1 mF) should be connected between this pin and VSS.
Voltage multiplier pin for power supply backup (internally generated)
A capacitor (1.0 mF) should be connected between this pin and VSS.
Low-speed clock oscillation pins.
A 32.768 kHz crystal should be connected between XT0 and XT1,
Oscillation
A ceramic resonator and capacitors (CL0, CL1) or external
A pull-down resistor is internally connected to these pins.
Test
The user cannot use these pins.
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
Reset
RESET
56
I
Then, setting this pin to "L" level starts executing an instruction
from address 0000H.
A pull-down resistor is internally connected to this pin.
Buzzer
BD
108
O
Buzzer output pin (non-inverted output)
BDB
109
O
Buzzer output pin (inverted output)
8/29
¡ Semiconductor
MSM63184A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Port
Symbol
Pin
P0.0/INT5
73
P0.1/INT5
72
P0.2/INT5
71
P0.3/INT5
70
P1.0/INT5
97
P1.1/INT5
96
P1.2/INT5
95
P1.3/INT5
94
P4.0/A0
69
P4.1/A1
68
P4.2/A2
67
P4.3/A3
66
P5.0/A4
65
P5.1/A5
63
P5.2/A6
62
P5.3/A7
61
P6.0/A8
101
P6.1/A9
100
P6.2/A10
99
P6.3/A11
98
P7.0/A12
107
P7.1/A13
106
P7.2/A14
105
P7.3/A15
104
Type
Description
4-bit input ports.
I
Pull-up resistor input, pull-down resistor input, or
high-impedance input is selectable for each bit.
I
4-bit output ports.
O
P-channel open drain output, N-channel open drain output,
CMOS output, or high-impedance output is selectable for each
bit.
O
O
O
9/29
¡ Semiconductor
MSM63184A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Port
Symbol
Pin
P8.0/RD
85
P8.1/WR
84
P8.2
83
or high-impedance input is selectable for each bit.
P8.3/INT4
82
In output mode, P-channel open drain output, N-channel open
P9.0/D0
89
drain output, CMOS output, or high-impedance output is
P9.1/D1
88
P9.2/D2
87
P9.3/D3
86
PA.0/D4
93
PA.1/D5
92
PA.2/D6
91
PA.3/D7
90
PD.0/FRAME
77
PD.1/LCLK
76
PD.2/TBCCLK
75
PD.3/HSCLK
74
PE.0/SIN
81
PE.1/SOUT
80
PE.2/SCLK
79
PE.3/INT2
78
Type
Description
4-bit input-output ports.
I/O
In input mode, pull-up resistor input, pull-down resistor input,
selectable for each bit.
I/O
I/O
I/O
I/O
10/29
¡ Semiconductor
MSM63184A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin
COM1
111
COM2
112
COM3
113
COM4
114
COM5
115
COM6
116
COM7
117
COM8
118
COM9
119
COM10
120
COM11
121
COM12
122
COM13
123
COM14
124
COM15
125
COM16
126
SEG0
38
SEG1
37
SEG2
36
SEG3
35
SEG4
34
SEG5
33
SEG6
32
SEG7
31
SEG8
30
SEG9
29
SEG10
28
SEG11
27
SEG12
26
SEG13
25
SEG14
24
SEG15
23
SEG16
22
SEG17
21
SEG18
20
SEG19
19
SEG20
18
SEG21
17
SEG22
16
SEG23
15
SEG24
14
Type
Description
LCD common signal output pins
O
LCD segment signal output pins
O
11/29
¡ Semiconductor
MSM63184A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin
SEG25
13
SEG26
12
SEG27
11
SEG28
10
SEG29
9
SEG30
8
SEG31
7
SEG32
6
SEG33
5
SEG34
4
SEG35
3
SEG36
2
SEG37
1
SEG38
128
SEG39
127
Type
Description
LCD segment signal output pins
O
12/29
¡ Semiconductor
MSM63184A
Table 2 shows the secondary functions of each pin of the MSM63184A.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin
Type
PE.3/INT2
78
I
P8.3/INT4
82
I
Description
External 2 interrupt input pins.
The change of input signal level causes an interrupt to occur.
External 4 interrupt input pins.
The change of input signal level causes an interrupt to occur.
P0.0/INT5
73
External 5 interrupt input pins.
External
P0.1/INT5
72
The change of input signal level causes an interrupt to occur.
Interrupt
P0.2/INT5
71
The Port 0 Interrupt Enable register (P0IE) and Port 1 Interrupt
P0.3/INT5
70
P1.0/INT5
97
P1.1/INT5
96
P1.2/INT5
95
P1.3/INT5
94
PD.0/FRAME
77
O
Frame output pin for LCD driver expansion
Expansion
PD.1/LCLK
76
O
Clock output pin for LCD driver expansion
Oscillation
PD.2/TBCCLK
75
O
Low-speed oscillation clock output pin
Output
PD.3/HSCLK
74
O
High-speed oscillation clock output pin
LCD
Enable register (P1IE) enable or disable an interrupt for each bit.
I
External
Shift
Register
PE.0/SIN
81
I
Shift register receive data input pin
PE.1/SOUT
80
O
Shift register transmit data output pin
PE.2/SCLK
79
O
Shift register clock input-output pin.
Clock output when this device is used as a master processor.
Clock input when this device is used as a slave processor.
13/29
¡ Semiconductor
MSM63184A
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
External
Memory
Symbol
Pin
P4.0/A0
69
P4.1/A1
68
P4.2/A2
67
P4.3/A3
66
P5.0/A4
65
P5.1/A5
63
P5.2/A6
62
P5.3/A7
61
P6.0/A8
101
P6.1/A9
100
P6.2/A10
99
P6.3/A11
98
P7.0/A12
107
P7.1/A13
106
P7.2/A14
105
P7.3/A15
104
P9.0/D0
89
P9.1/D1
88
P9.2/D2
87
Type
Description
Address output bus for external memory
O
Data bus for external memory
P9.3/D3
86
PA.0/D4
93
PA.1/D5
92
PA.2/D6
91
PA.3/D7
90
P8.0/RD
85
O
Read signal output pin for external memory (negative logic)
P8.1/WR
84
O
Write signal output pin for external memory (negative logic)
I/O
14/29
¡ Semiconductor
MSM63184A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage 1
VDD1
Ta = 25°C
–0.3 to +1.6
V
Power Supply Voltage 2
VDD2
Ta = 25°C
–0.3 to +2.9
V
Power Supply Voltage 3
VDD3
Ta = 25°C
–0.3 to +4.2
V
Power Supply Voltage 4
VDD4
Ta = 25°C
–0.3 to +5.5
V
Power Supply Voltage 5
VDD5
Ta = 25°C
–0.3 to +6.8
V
Power Supply Voltage 6
VDD
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 7
VDDI
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 8
VDDH
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 9
VDDL
Ta = 25°C
–0.3 to +6.0
V
Input Voltage 1
VIN1
VDD Input, Ta = 25°C
–0.3 to VDD + 0.3
V
Input Voltage 2
VIN2
VDDI Input, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 1
VOUT1
VDD1 Output, Ta = 25°C
–0.3 to VDD1 + 0.3
V
Output Voltage 2
VOUT2
VDD2 Output, Ta = 25°C
–0.3 to VDD2 + 0.3
V
Output Voltage 3
VOUT3
VDD3 Output, Ta = 25°C
–0.3 to VDD3 + 0.3
V
Output Voltage 4
VOUT4
VDD4 Output, Ta = 25°C
–0.3 to VDD4 + 0.3
V
Output Voltage 5
VOUT5
VDD5 Output, Ta = 25°C
–0.3 to VDD5 + 0.3
V
Output Voltage 6
VOUT6
VDD Output, Ta = 25°C
–0.3 to VDD + 0.3
V
Output Voltage 7
VOUT7
VDDI Output, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 8
VOUT8
VDDH Output, Ta = 25°C
–0.3 to VDDH + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
15/29
¡ Semiconductor
MSM63184A
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Ceramic Oscillation Frequency
External RC Oscillator Resistance
Symbol
Condition
Range
Unit
Top
—
–20 to +70
°C
VDD
—
0.9 to 2.7
V
VDDI
—
0.9 to 5.5
V
kHz
fXT
fCM
—
30 to 35
VDD = 1.2 to 2.7 V
300k to 500k
VDD = 1.5 to 2.7 V
200k to 1M
Hz
VDD = 1.2 to 2.7 V
100 to 300
VDD = 1.5 to 2.7 V
50 to 300
Symbol
Condition
Range
Unit
ROS
kW
• When backup is not used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Ceramic Oscillation Frequency
External RC Oscillator Resistance
Top
—
–20 to +70
°C
VDD
—
1.8 to 5.5
V
VDDI
—
1.8 to 5.5
V
fXT
—
30 to 35
kHz
VDD = 1.8 to 5.5 V
300k to 500k
VDD = 2.2 to 5.5 V
300k to 1M
VDD = 2.7 to 5.5 V
200k to 2M
fCM
ROS
VDD = 1.8 to 5.5 V
100 to 300
VDD = 2.2 to 5.5 V
50 to 300
VDD = 2.7 to 5.5 V
30 to 300
Hz
kW
16/29
¡ Semiconductor
MSM63184A
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
VDD2 Voltage
VDD2 Voltage Temperature Deviation
VDD1 Voltage
VDD3 Voltage
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaMin.
Typ.
Max. Unit suring
Symbol
Condition
Circuit
1/5 bias, 1/4 bias
VDD2
1.7
1.8
1.9
V
(Ta = 25°C)
DVDD2
—
VDD1
1/5 bias, 1/4 bias
Typ.– 0.2 1/2 ¥ VDD2 Typ.+ 0.2
1/5 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
VDD3
1/4 bias (connect
VDD3 and VDD2)
VDD4 Voltage
VDD4
VDD5 Voltage
VDD5
VDDH Voltage
(Backup used)
VDDL Voltage
VDDH
VDDL
Crystal Oscillation Start Voltage
VSTA
Crystal Oscillation Hold Voltage
VHOLD
—
Typ.– 0.2
–4
VDD2
—
Typ.+ 0.2
1/5 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
1/4 bias
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
1/5 bias
Typ.– 0.5 5/2 ¥ VDD2 Typ.+ 0.5
1/4 bias
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
High-speed clock oscillation
stopped
VDD = 1.5 V
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
VDD = 1.5 V
High-speed clock
oscillation stopped
mV/°C
V
V
V
V
2.8
—
3.0
V
2.0
—
2.7
V
1
0.8
1.3
1.8
V
High-speed clock oscillation
(VDD = 1.2 to 5.5 V)
1.2
—
5.5
V
Oscillation start time:
within 5 seconds
1.0
—
—
V
Backup
0.9
—
—
V
Backup not used
1.7
—
—
V
Crystal Oscillation Stop Detect Time
TSTOP
—
0.1
—
5.0
ms
External Crystal Oscillator Capacitance
CG
—
5
—
25
pF
Internal Crystal Oscillator Capacitance
CD
—
20
25
30
pF
—
30
—
pF
External Ceramic Oscillator
Capacitance
Internal RC Oscillator Capacitance
CL0, 1
COS
POR Voltage
VPOR1
Non-POR Voltage
VPOR2
CSA2.00MG (Murata
MFG.-make) used
VDD = 3.0 V
—
8
12
16
pF
VDD = 1.5 V
0.0
—
0.4
V
VDD = 3.0 V
0.0
—
0.7
V
VDD = 1.5 V
1.2
—
1.5
V
VDD = 3.0 V
2.0
—
3.0
V
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system
reset occurs.
2. "POR" denotes Power On Reset.
3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises
up to VDD.
4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and
again rises up to VDD.
17/29
¡ Semiconductor
MSM63184A
DC Characteristics (continued)
• When backup is used
(VDD = VDDI = 1.5 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
MeaParameter Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
CPU is in HALT state.
5.3
6.5
Ta = –20 to +50°C —
mA
Supply Current 1 IDD1 (High-speed clock oscillation
5.3
8.0
Ta = –20 to +70°C —
stopped)
Supply Current 2
IDD2
CPU is in HALT state.
Ta = –20 to +50°C
LCD is in Power Down mode.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
4.2
5.0
—
4.2
6.5
mA
1
Supply Current 3
IDD3
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
—
15
20
mA
Supply Current 4
IDD4
CPU is in operation at high-speed oscillation
(RC oscillation, f = approx. 720 kHz, ROS = 51 kW)
—
600
800
mA
Supply Current 5
IDD5
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 1 MHz)
—
700
900
mA
• When backup is not used
(VDD = VDDI = 3.0 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
MeaParameter Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
CPU is in HALT state.
2.4
2.9
Ta = –20 to +50°C —
mA
Supply Current 1 IDD1 (High-speed clock oscillation
Ta = –20 to +70°C —
2.4
3.4
stopped)
Supply Current 2
Supply Current 3
Supply Current 4
Supply Current 5
IDD2
IDD3
IDD4
IDD5
CPU is in HALT state.
Ta = –20 to +50°C
LCD is in Power Down mode.
(High-speed clock oscillation
Ta = –20 to +70°C
stopped)
—
1.8
2.2
—
1.8
2.8
—
7.2
9.0
f = approx. 800 kHz,
ROS = 51 kW
—
450
600
f = approx. 500 kHz,
ROS = 100 kW
—
350
450
—
850
1000
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
CPU is in operation at
high-speed oscillation
(RC oscillation)
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 2 MHz)
mA
mA
1
mA
mA
18/29
¡ Semiconductor
MSM63184A
DC Characteristics (continued)
Parameter
IOH1
VDDI = 1.5 V
–2.0
–1.2
–0.2
mA
VOH1 = VDDI – 0.5 V VDDI = 3.0 V
–5.0
–3.0
–1.0
mA
···
Output Current 1
(P4.0 to P4.3)
(P5.0 to P5.3)
(P6.0 to P6.3)
Symbol
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
(PD.0 to PD.3)
(PE.0 to PE.3)
IOL1
VOL1 = 0.5 V
Output Current 2
(BD, BDB)
Output Current 3
(SEG0 to SEG39)
(COM1 to COM16)
IOH2
(OSC1)
–1.5
mA
1.2
2.0
mA
VDDI = 3.0 V
1.0
3.0
5.0
mA
VDDI = 5.0 V
1.5
4.0
8.0
mA
VDD = 1.5 V
–2.5
–1.3
–0.4
mA
VDD = 3.0 V
–6.0
–4.0
–2.0
mA
VDD = VDDH = 5.0 V
–9.0
–5.5
–3.0
mA
VDD = 1.5 V
0.4
1.3
2.5
mA
VDD = 3.0 V
2.0
4.0
6.0
mA
VDD = VDDH = 5.0 V
3.0
5.5
9.0
mA
—
—
–4
mA
IOH3
VOH3 = VDD5 – 0.2 V (VDD5 level)
IOHM3
VOHM3 = VDD4 + 0.2 V (VDD4 level)
4
—
—
mA
IOHM3S
VOHM3S = VDD4 – 0.2 V (VDD4 level)
—
—
–4
mA
IOMH3
VOMH3 = VDD3 + 0.2 V (VDD3 level)
4
—
—
mA
IOMH3S
VOMH3S = VDD3 – 0.2 V (VDD3 level)
—
—
–4
mA
IOML3
VOML3 = VDD2 + 0.2 V (VDD2 level)
4
—
—
mA
IOML3S
VOML3S = VDD2 – 0.2 V (VDD2 level)
—
—
–4
mA
IOLM3
VOLM3 = VDD1 + 0.2 V (VDD1 level)
4
—
—
mA
IOLM3S
VOLM3S = VDD1 – 0.2 V (VDD1 level)
—
—
–4
mA
VOL3 = VSS + 0.2 V (VSS level)
4
—
—
mA
IOH4R
IOH4C
IOL4C
···
–4.0
0.2
VOL2 = 0.7 V
IOL4R
Output Leakage
(P4.0 to P4.3)
(P5.0 to P5.3)
(P6.0 to P6.3)
–8.0
IOL2
IOL3
Output Current 4
VOH2 = VDD – 0.7 V
VDDI = 5.0 V
VDDI = 1.5 V
VOH4R = VDDH – 0.5 V VDD = VDDH = 3.0 V
–2.5
–1.5
–0.75
mA
(RC oscillation)
VDD = VDDH = 5.0 V
–3.5
–2.0
–1.0
mA
VOL4R = 0.5 V
VDD = VDDH = 3.0 V
0.75
1.5
2.5
mA
(RC oscillation)
VDD = VDDH = 5.0 V
1.0
2.0
3.5
mA
mA
VOH4C = VDDH – 0.5 V VDD = VDDH = 3.0 V
–300
–180
–60
(ceramic oscillation)
VDD = VDDH = 5.0 V
–450
–280
–100
mA
VOL4C = 0.5 V
VDD = VDDH = 3.0 V
60
120
300
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
100
200
450
mA
IOOH
VOH = VDDI
—
—
0.3
mA
IOOL
VOL = VSS
–0.3
—
—
mA
2
(PE.0 to PE.3)
19/29
¡ Semiconductor
MSM63184A
DC Characteristics (continued)
Parameter
···
Input Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
Symbol
IIH1
IIL1
(PE.0 to PE.3)
VIH1 = VDDI
(when pulled down)
VIL1 = VSS
(when pulled up)
2
10
30
mA
30
90
180
mA
VDDI = 5.0 V
70
250
600
mA
VDDI = 1.5 V
–30
–10
–2
mA
VDDI = 3.0 V
–180
–90
–30
mA
VDDI = 5.0 V
–600
–250
–70
mA
0.0
—
1.0
mA
VIH1 = VDDI (in a high impedance state)
IIL1Z
VIL1 = VSS (in a high impedance state)
IIL2
–1.0
—
0.0
mA
VIL2 = VSS
VDD = VDDH = 3.0 V
–200
–110
–30
mA
(when pulled up)
VDD = VDDH = 5.0 V
–600
–350
–150
mA
IIH2R
VIH2R = VDDH (RC oscillation)
0.0
—
1.0
mA
IIL2R
VIL2R = VSS (RC oscillation)
–1.0
—
0.0
mA
VDD = VDDH = 3.0 V
0.1
0.5
1.0
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
0.75
1.5
3.0
mA
VDD = VDDH = 3.0 V
–1.0
–0.5
–0.1
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
–3.0
–1.5
–0.75
mA
IIH2C
IIL2C
VIH2C = VDDH
VIL2C = VSS
Input Current 3
(RESET)
VDDI = 1.5 V
VDDI = 3.0 V
IIH1Z
Input Current 2
(OSC0)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
IIH3
VIH3 = VDD
IIL3
VIL3 = VSS
IIH4
VIH4 = VDD
IIL4
VIL4 = VSS
VDD = 1.5 V
10
50
80
mA
VDD = 3.0 V
150
350
600
mA
VDD = VDDH = 5.0 V
Input Current 4
(TST1, TST2)
0.5
1.0
2.0
mA
–1.0
—
0.0
mA
VDD = 1.5 V
50
150
300
mA
VDD = 3.0 V
0.5
1.0
1.5
mA
VDD = VDDH = 5.0 V
1.25
2.5
4.0
mA
–1.0
—
0.0
mA
3
20/29
¡ Semiconductor
MSM63184A
DC Characteristics (continued)
Parameter
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
VIH1
VDDI = 1.5 V
1.2
—
1.5
V
VDDI = 3.0 V
2.4
—
3.0
V
VDDI = 5.0 V
4.0
—
5.0
V
VDDI = 1.5 V
0.0
—
0.3
V
0.0
—
0.6
V
VDDI = 5.0 V
0.0
—
1.0
V
Input Voltage 2
VDD = VDDH = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = VDDH = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDD = 1.5 V
1.35
—
1.5
V
···
VDDI = 3.0 V
(PE.0 to PE.3)
(OSC0)
VIL1
VIH2
VIL2
Input Voltage 3
(RESET, TST1, TST2)
VDD = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = 1.5 V
0.0
—
0.15
V
VDD = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDDI = 1.5 V
0.05
0.1
0.3
V
VDDI = 3.0 V
0.2
0.5
1.0
V
(PE.0 to PE.3)
VDDI = 5.0 V
0.25
1.0
1.5
V
Hysteresis Width 2
VDD = 1.5 V
0.05
0.1
0.3
V
VIH3
VIL3
DVT1
···
Hysteresis Width 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
4
(RESET, TST1, TST2)
CIN
VDD = 3.0 V
0.2
0.5
1.0
V
VDD = VDDH = 5.0 V
0.25
1.0
1.5
V
—
—
—
5
pF
1
···
Input Pin Capacitance
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
DVT2
(PD.0 to PD.3)
(PE.0 to PE.3)
21/29
¡ Semiconductor
MSM63184A
Measuring circuit 1
CB1
CG
Cb12
XT0
CB2
C1
32.768 kHz
Crystal
XT1
C12
C2
q
*1
w
OSC0
OSC1
VSS VDD VDDI VDD1
A
Ca
V
Ca, Cb, Cc, Cd, Ce, Cl, C12
Cb12, Ch
CG
CL0
CL1
Ceramic Resonator
VDD2
VDD3
VDD4
VDD5
VDDH VDDL
Cb
Cc
Cd
Ce
Ch
V
: 0.1 mF
: 1 mF
: 15 pF
: 30 pF
: 30 pF
: CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
V
V
V
Cl
V
V
*1 RC Oscillator
q
ROS
w
Ceramic Oscillator
q
CL0
Ceramic Resonator
w
CL1
Measuring circuit 2
*3
VIH
A
*2
INPUT
VIL
VSS
OUTPUT
VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the specified output pins.
22/29
¡ Semiconductor
MSM63184A
Measuring circuit 3
*4
A
INPUT
OUTPUT
VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
Measuring circuit 4
VIH
Waveform
Monitoring
*4
INPUT
VIL
VSS
OUTPUT
VDD
VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*4 Measured at the specified input pins.
23/29
¡ Semiconductor
MSM63184A
AC Characteristics (Serial Interface, Shift Register)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise
specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
SCLK Input Fall Time
tf
—
—
—
1.0
ms
SCLK Input Rise Time
tr
—
—
—
1.0
ms
SCLK Input "L" Level
Pulse Width
tCWL
—
0.8
—
—
ms
SCLK Input "H" Level
Pulse Width
tCWH
—
0.8
—
—
ms
tCYC
VDDI = 5 V to VDD
1.8
—
—
ms
tCYC1(O)
CPU in operation state at 32 kHz
—
30.5
—
ms
—
0.5
—
ms
SCLK Input Cycle Time
SCLK Output Cycle Time
CPU in operation at 2 MHz
tCYC2(O)
VDD = VDDH = 2.7 V to 5.5 V
SOUT Output Delay Time
tDDR
Cl = 10 pF
—
—
0.4
ms
SIN Input Setup Time
tDS
—
0.5
—
—
ms
SIN Input Hold Time
tDH
—
0.8
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
tCYC
SCLK (PE.2)
5 V (VDDI)
0 V (VSS)
tr
tf
tCWH
tCWL
tDDR
tDDR
5 V (VDDI)
SOUT (PE.1)
0 V (VSS)
tDS
SIN (PE.0)
tDH
tDS
5 V (VDDI)
0 V (VSS)
24/29
¡ Semiconductor
MSM63184A
AC Characteristics (External Memory Interface)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise
specified)
(1) Reading from External Memory
(a) When CPU operates at 32.768 kHz
Symbol
Condition
Min.
Typ.
Read Cycle Time
Parameter
Max.
Unit
tRC
—
—
RD Output Delay Time
tOE
—
—
61.0
—
ms
—
5.0
ms
Output Valid Time
tOHA
—
External Memory Output Delay Time
tDO
—
—
—
5.0
ms
—
—
5.0
ms
Symbol
Condition
Min.
Typ.
Max.
Unit
Read Cycle Time
RD Output Delay Time
tRC
—
1.0
—
—
ms
tOE
—
—
—
100
ns
Output Valid Time
tOHA
—
—
—
100
ns
External Memory Output Delay Time
tDO
—
—
—
150
ns
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Parameter
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB obj, xadr16
MOVXB obj, [RA]
S1
S2
S1
S2
S1
S2
System clock
tRC
P7 - P4
(A15 - A0)
Port setup value
Address output
Port setup value
5 V (VDDI)
0 V (VSS)
P8.0
(RD)
tOE
PA, P9
(D7 - D0)
5 V (VDDI)
0 V (VSS)
Port setup value
Input data
tOHA
Port setup value
5 V (VDDI)
0 V (VSS)
tDO
25/29
¡ Semiconductor
MSM63184A
(2) Writing to External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
tWC
—
—
61.0
—
ms
Address Setup Time
tAS
—
—
30.5
—
ms
Write Time
tW
—
—
15.3
—
ms
Write Recovery Time
tWR
—
—
15.3
—
ms
Data Setup Time
tDS
—
—
45.8
—
ms
Data Hold Time
tDH
—
—
15.3
—
ms
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
tWC
—
1.0
—
—
ms
Address Setup Time
tAS
—
0.4
—
—
ms
Write Time
tW
—
0.2
—
—
ms
Write Recovery Time
tWR
—
0.2
—
—
ms
Data Setup Time
tDS
—
0.7
—
—
ms
Data Hold Time
tDH
—
0.2
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB [RA], obj or MOVXB xadr16, obj
S1
S2
S1
S2
S1
S2
System clock
tWC
P7 - P4
(A15 - A0)
PA, P9
(D7 - D0)
Port setup value
Address output
Port setup value
Output data
tDS
tDH
Port setup value
Port setup value
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
P8.1
(WR)
tAS
tW
tWR
26/29
¡ Semiconductor
MSM63184A
APPLICATION CIRCUITS
•RC oscillation is selected as high-speed
oscillation.
•Ports are powered from external memory
power source.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12,
Ch, and CG, are for reference only.
LCD
Crystal
32.768 kHz
COM1-16
SEG0-39
XT0
OSC0
ROS
CG
5 to
25 pF
Ch
1.0 mF
1.5 V
Cv 0.1 mF
1.0 mF
Cb12
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
C12
OSC1
VDD
P8.3
P8.2
CB1
Open
PE.3
PE.2
PE.1
PE.0
PD.3
PD.2
PD.1
PD.0
CB2
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
C1
0.1 mF
Push SW
Buzzer
XT1
VDDH
C2
MSM63184A
SW Matrix
(8 ¥ 8)
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
RESET
TST1
TST2
BD
VDDI
BDB
P4-7
VDD
VSS
P9, PA
P8.0
P8.1
A15-0
External
D7-0 Memory
RD (64K ¥ 8 bits)
WR VSS
5.0 V
Note: VDDI is the power supply pin for the input, output, and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
27/29
¡ Semiconductor
MSM63184A
APPLICATION CIRCUITS (continued)
•Ceramic oscillation is selected as high-speed
oscillation.
•Ports, external memory, and IC share their
power supply.
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG,
CL0, and CL1 are for reference only.
LCD
Crystal
32.768 kHz
COM1-16
CL0 30 pF
SEG0-39
XT0
OSC0
XT1
VDDH
OSC1
VDD
P8.3
P8.2
Ceramic
Resonator
(Example: 1 MHz)
CG
5 to 25 pF
VDD
CL1
30 pF
5.0 V
Cv 0.1 mF Open
Cl
0.1 mF
Ce
0.1 mF
Cd
0.1 mF
Cc
0.1 mF
Cb
0.1 mF
Ca
0.1 mF
CB1
CB2
VDDL
VDD5
VDD4
VDD3
VDD2
VDD1
C1
C12
0.1 mF
Push SW
Open
Buzzer
PE.3
PE.2
PE.1
PE.0
PD.3
PD.2
PD.1
PD.0
C2
MSM63184A
SW Matrix
(8 ¥ 8)
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
RESET
TST1
TST2
BD
VDDI
BDB
P4-7
VDD
VDD
VSS
P9, PA
P8.0
P8.1
A15-0
External
D7-0 Memory
RD (64K ¥ 8 bits)
WR VSS
Note: VDDI is the power supply pin for the input, output, and input-output ports.
Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this
device or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
28/29
¡ Semiconductor
MSM63184A
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-1420-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.19 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
29/29
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan