SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 FEATURES • • • • • • • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Operates From 2.7 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 8.5 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors All Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR DESCRIPTION/ORDERING INFORMATION This 16-bit (dual-octal) noninverting bus transceiver is designed for 2.7-V to 3.6-V VCC operation. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE The SN74LVCR162245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated. All outputs, which are designed to sink up to 12 mA, include 26-Ω resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR. ORDERING INFORMATION PACKAGE (1) TA SSOP – DL –40°C to 85°C TSSOP – DGG VFBGA – GQL VFBGA – ZQL (Pb-free) (1) ORDERABLE PART NUMBER Tube SN74LVCR162245DL Tape and reel SN74LVCR162245DLR Tape and reel SN74LVCR162245DGGR Tape and reel SN74LVCR162245KR 74LVCR162245ZQLR TOP-SIDE MARKING LVCR162245 LVCR162245 LEP245 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995–2005, Texas Instruments Incorporated SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K TERMINAL ASSIGNMENTS (1) 1 (1) 2 3 4 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 VCC VCC 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND 2A4 2A3 H 2B5 2B6 VCC VCC 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OE GND NC - No internal connection FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS 2 5 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 48 1A1 1OE 47 2 1B1 To Seven Other Channels 2DIR 24 25 2A1 2OE 36 13 2B1 Pin numbers shown are for the DGG and DL packages. 3 SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX –0.5 4.6 Except I/O ports (2) –0.5 VCC + 4.6 I/O ports (2) (3) –0.5 VCC + 0.5 –0.5 VCC + 0.5 Supply voltage range UNIT V VI Input voltage range VO Output voltage range (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 or VO > VCC ±50 mA IO Continuous output current VO = 0 to VCC ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg (1) (2) (3) (4) DGG package 70 DL package 63 GQL/ZQL package 42 Storage temperature range –65 V V °C/W °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current ∆t/∆V Input transition rise or fall rate TA Operating free-air temperature (1) 4 MIN MAX 2.7 3.6 2 UNIT V V 0.8 V 0 VCC V 0 VCC V VCC = 2.7 V –8 VCC = 3 V –12 VCC = 2.7 V 8 VCC = 3 V 12 –40 mA mA 10 ns/V 85 °C All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC (1) TEST CONDITIONS IOH = –100 µA VOH MIN to MAX IOH = –4 mA, VIH = 2 V IOH = –8 mA, VIH = 2 V IOH = –6 mA, VIH = 2 V IOH = –12 mA, VIH = 2 V Il VIL = 0.8 V IOL = 8 mA, VIL = 0.8 V IOL = 6 mA, VIL = 0.8 V IOL = 12 mA, VIL = 0.8 V 0.4 0.6 V 0.55 0.8 ±5 3.6 V 75 µA µA –75 VI = 0 to 3.6 V 3.6 V ±500 µA VO = 0 V or (VCC to 5.5 V) 3.6 V ±10 µA 3.6 V ≤ VI ≤ 5.5 V (4) ∆ICC 0.2 3V VI = VCC or GND ICC 2 3V VI = 2 V IOZ (3) V 2.7 V VI = 0.8 V Il(hold) 2 2.4 3V VI = VCC or GND UNIT 2.2 MIN to MAX IOL = 4 mA, MAX VCC – 0.2 2.7 V IOL = 100 µA VOL MIN TYP (2) One input at VCC – 0.6 V, IO = 0 20 3.6 V Other inputs at VCC or GND 20 2.7 V to 3.6 V 500 µA µA Ci Control inputs VI = VCC or GND 3.3 V 2.5 pF Cio A or B ports VO = VCC or GND 3.3 V 3.5 pF (1) (2) (3) (4) For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. All typical values are at VCC = 3.3 V, TA = 25°C. For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is negligible. This applies in the disabled state only. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B ten OE tdis OE PARAMETER VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MIN MAX MIN MAX B or A 1.5 7.5 1.5 8.5 ns A or B 1.5 9 1.5 10 ns A or B 1.5 7.5 1.5 8.5 ns Operating Characteristics VCC = 3.3 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, f = 10 MHz TYP 20 2 UNIT pF 5 SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 2.7 V 1.5 V 0V 1.5 V Data Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 1.5 V 0V tPLH 1.5 V VOL tPHL VOH Output VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS tPLZ 3V 1.5 V tPZH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPLH 1.5 V 1.5 V tPZL VOH Output 2.7 V Output Control tPHL 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Input th Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 24-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 74LVCR162245DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVCR162245DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVCR162245DLG4 ACTIVE SSOP DL 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVCR162245DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVCR162245ZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74LVCR162245DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCR162245DL ACTIVE SSOP DL 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCR162245DLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCR162245KR ACTIVE GQL 56 1000 SNPB Level-1-240C-UNLIM BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty 25 25 TBD Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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