TI SN74LVC540ADW

SN54LVC540A, SN74LVC540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS297H – JANUARY 1993 – REVISED JUNE 1998
D
D
D
D
D
description
The SN54LVC540A octal buffer/driver is designed
for 2.7-V to 3.6-V VCC operation and the
SN74LVC540A octal buffer/driver is designed for
1.65-V to 3.6-V VCC operation.
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54LVC540A . . . FK PACKAGE
(TOP VIEW)
A3
A4
A5
A6
A7
OE2
D
SN54LVC540A . . . J OR W PACKAGE
SN74LVC540A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
A2
A1
OE1
VCC
D
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Power Off Disables Outputs, Permitting
Live Insertion
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and DIPs (J)
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
D
These devices are ideal for driving bus lines or
buffer memory address registers. These devices
feature inputs and outputs on opposite sides of the
package that facilitate printed circuit board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2)
input is high, all outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LVC540A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC540A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LVC540A, SN74LVC540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS297H – JANUARY 1993 – REVISED JUNE 1998
FUNCTION TABLE
INPUTS
A
OUTPUT
Y
L
L
H
L
H
L
H
X
X
Z
X
H
X
Z
OE1
OE2
L
L
logic symbol†
1
OE1
&
19
EN
OE2
A1
A2
A3
A4
A5
A6
A7
A8
2
18
1
3
17
4
16
5
15
6
14
7
13
8
12
9
11
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE1
OE2
A1
1
19
2
18
To Seven Other Channels
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Y1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54LVC540A, SN74LVC540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS297H – JANUARY 1993 – REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVC540A
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
IOL
High level output current
High-level
Low level output current
Low-level
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
1.5
UNIT
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
SN74LVC540A
MIN
V
1.7
2
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.7
0.8
V
0.8
0
5.5
0
5.5
V
High or low state
0
0
VCC
5.5
0
3 state
VCC
5.5
V
VCC = 1.65 V
VCC = 2.3 V
0
–4
–8
VCC = 2.7 V
VCC = 3 V
–12
–12
–24
–24
VCC = 1.65 V
VCC = 2.3 V
mA
4
8
VCC = 2.7 V
VCC = 3 V
12
12
24
24
mA
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LVC540A, SN74LVC540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS297H – JANUARY 1993 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
2.7 V to 3.6 V
IOH = –4 mA
IOH = –8 mA
SN74LVC540A
TYP†
MAX
MIN
1.65 V to 3.6 V
IOH = –100
100 µA
VOH
SN54LVC540A
TYP†
MAX
VCC
MIN
VCC–0.2
VCC–0.2
1.65 V
1.2
2.3 V
IOH = –12
12 mA
IOH = –24 mA
V
1.7
2.7 V
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
1.65 V to 3.6 V
IOL = 100 µA
UNIT
0.2
2.7 V to 3.6 V
0.2
IOL = 4 mA
IOL = 8 mA
1.65 V
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
0.4
3V
0.55
0.55
II
VI = 0 to 5.5 V
3.6 V
±5
±5
µA
Ioff
VI or VO = 5.5 V
IOZ
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V‡
VOL
ICC
±10
µA
±15
±10
µA
10
10
10
10
500
500
0
3.6 V
IO = 0
∆ICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
Co
VO = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This applies in the disabled state only.
36V
3.6
2.7 V to 3.6 V
V
µA
µA
3.3 V
4
4
pF
3.3 V
5.5
5.5
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC540A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.7 V
MIN
4
VCC = 3.3 V
± 0.3 V
MAX
MIN
MAX
UNIT
tpd
A
Y
7.1
1
5.3
ns
ten
OE
Y
8
1
6.6
ns
tdis
OE
Y
8.2
1
7.4
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVC540A, SN74LVC540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS297H – JANUARY 1993 – REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC540A
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
MIN
MAX
tpd
A
Y
†
†
†
†
ten
OE
Y
†
†
†
tdis
OE
Y
†
†
†
PARAMETER
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
7.1
1.4
5.3
ns
†
8
1.1
6.6
ns
†
8.2
1.8
7.4
ns
1
ns
tsk(o)‡
† This information was not available at the time of publication.
‡ Skew between any two outputs of the same package switching in the same direction
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per buffer/driver
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
TYP
†
†
31
†
†
3
UNIT
pF
† This information was not available at the time of publication.
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• DALLAS, TEXAS 75265
5
SN54LVC540A, SN74LVC540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS297H – JANUARY 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1k Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1k Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVC540A, SN74LVC540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS297H – JANUARY 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54LVC540A, SN74LVC540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS297H – JANUARY 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOL
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
Input
1.5 V
1.5 V
tsu
Input
1.5 V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
8
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Copyright  1998, Texas Instruments Incorporated