TI PGA870IRHDT

PG
A8
70
PGA870
www.ti.com
SBOS436 – DECEMBER 2009
High-Speed, Fully Differential, Programmable-Gain Amplifier
Check for Samples: PGA870
FEATURES
DESCRIPTION
•
•
•
•
The PGA870 is a wideband programmable-gain
amplifier (PGA) for high-speed signal chain and data
acquisition systems. The PGA870 has been
optimized to provide high bandwidth, low distortion,
and low noise, making it ideally suited as a 14-bit
analog-to-digital converter (ADC) driver for wireless
base station signal chain applications. The wide gain
range of –11.5 dB to +20 dB can be adjusted in
0.5-dB gain steps through a 6-bit control word applied
to the parallel interface. The gain control interface
may be configured as a level-triggered latch or an
edge-triggered latch, or it may be placed in an
unlatched (transparent) mode. In addition to the 6-bit
gain control, the PGA870 contains a power-down pin
(PD) that can be used to put the device into a
low-current, power-down mode. In this mode, the
quiescent current drops to 2 mA, but the gain control
circuitry remains active, allowing the gain of the
PGA870 to be set before device power-up. The
PGA870 is offered in a QFN-28 PowerPAD™
package.
1
23
•
•
•
•
•
•
•
Wideband +5-V Operation: 650-MHz Bandwidth
Low Impedance, Voltage Mode Output
Wide Gain Range: –11.5 dB to +20 dB
Precise 0.5-dB Gain Steps
Step-to-Step Gain Error = ±0.03 dB
HD2: –93 dBc at 100 MHz
HD3: –88 dBc at 100 MHz
IMD3: –98 dBc at 100 MHz, –95 dBc at 200 MHz
OIP3: +47 dBm at 100 MHz;
Exceeds +45 dBm for Frequencies to 300 MHz
Flexible Gain Control Interface:
– Supports latched and unlatched options
– Gain may be set in power-down state
– Fast setup and hold times: 2.5 ns
Low Disable Current: 2 mA
Pb-Free (RoHS-Compliant) and Green Package
APPLICATIONS
•
•
•
•
RELATED PRODUCTS
Programmable Gain IF Amplifier:
– Differential signal chains
– Single-ended to differential conversion
Fast Gain Control Loops for:
– Test/measurement
– Digital radio signal chains
ADC Driver for Wireless Base Station Signal
Chains: GSM, WCDMA, MC-GSM
Radar/Ranging Systems
DEVICE
DESCRIPTION
THS4509
Wideband, low-noise, low-distortion, fully
differential amplifier
THS7700
High-speed, fully differential 16-bit ADC
driver
THS9000
50-MHz to 400-MHz IF/RF Amplifier
ADS6149
14-Bit, 250-MSPS ADC with DDR
LVDS/CMOS Outputs
ADS6145
6b Gain Adjust
14-Bit, 125-MSPS ADC with DDR
LVDS/CMOS Outputs
Fast Gain Control Loop
+5 V
6b
FS = 250 MHz
6b
Signal Source
Programmable
Attenuator
Bandpass
Filter
PGA870
ADS6149
FPGA
Control Logic
Latch Mode 1
Powerdown 1
Gain Strobe 1
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
PGA870
SBOS436 – DECEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PGA870
QFN-28
RHD
(1)
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PGA870
PGA870IRHDT
Tape and Reel, 250
PGA870
PGA870IRHDR
Tape and Reel, 3000
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Power supply
Internal power dissipation
PGA870
UNIT
6
V
See Thermal Characteristics
Input voltage range
VS
V
–40 to +125
°C
Maximum junction temperature (TJ)
+150
°C
Maximum junction temperature (TJ), continuous operation, long-term reliability
+140
°C
Human body model (HBM)
2000
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
Storage temperature range
ESD rating
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
DISSIPATION RATINGS (1)
POWER RATING (2)
(TJ= +125°C)
(1)
(2)
PACKAGE
θJP(°C/W)
θJA(°C/W)
TA= +25°C
TA= +85°C
QFN-28
4.1
35
2.9 W
0.87 W
These data were taken with the JEDEC High-K test PCB. For the JEDEC low-K test PCB, θJA is 350°C/W.
Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase and
long-term reliability starts to be reduced. Thermal management of the final printed circuit board should strive to keep the junction
temperature at or below +125° C for best performance and reliability.
2
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
www.ti.com
SBOS436 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS: VS+= +5 V
Boldface limits are tested at +25°C.
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL= 200 Ω differential, G = 20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
PGA870IRHD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
AC PERFORMANCE
Small-signal bandwidth
G = 20 dB, VO = 100 mVPP
650
MHz
C
Large-signal bandwidth
G = 20 dB, VO = 2 VPP
650
MHz
C
100
MHz
C
Bandwidth for 0.1-dB flatness
Slew rate (differential)
2-V step
2900
V/µs
C
Rise time
2-V step
0.55
ns
C
Fall time
2-V step
0.55
ns
C
Settling time to 1%
2-V step
3
ns
C
Settling time to 0.1%
2-V step
5
ns
C
HARMONIC DISTORTION
Gain = +20 dB, VO = 2 VPP, RL = 200 Ω
Second-order harmonic distortion
Third-order harmonic distortion
f = 50 MHz
–108
dBc
C
f = 100 MHz
–93
dBc
C
f = 200 MHz
–71
dBc
C
f = 50 MHz
–95
dBc
C
f = 100 MHz
–88
dBc
C
f = 200 MHz
–75
dBc
C
f1(MHz)
Second-order intermodulation
distortion
Third-order intermodulation distortion
Output third-order intercept
Noise figure
2-MHz tone
spacing
2-MHz tone
spacing
VOUT = 2 VPP,
RL = 200 Ω
f2(MHz)
C
49
51
-87
dBc
C
99
101
-90
dBc
C
199
201
-89
dBc
C
49
51
-103
dBc
C
99
101
–98
dBc
C
199
201
–95
dBc
C
49
51
50
dBm
C
99
101
47
dBm
C
199
201
45
dBm
C
13
dB
C
30
mV
A
35
mV
B
20
μV/°C
B
-40
dB
B
150-Ω system, Gain = +20 dB, f = 100 MHz
DC
Output offset voltage
Average offset voltage drift
TA= +25°C
–30
TA= –40°C to +85°C
–35
TA= –40°C to +85°C
±5
INPUT
Input return loss
ZSYS= 150 Ω, frequency < 300MHz
Differential input resistance
129
Differential input capacitance
(1)
B
C
141
Ω
B
76
dB
A
1.2
Single-ended input resistance
Common-mode rejection ratio
Ω
pF
150
TA= +25°C, Gain = 20 dB
54
173
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value; only for information.
3
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
SBOS436 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: VS+= +5 V (continued)
Boldface limits are tested at +25°C.
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL= 200 Ω differential, G = 20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
PGA870IRHD
PARAMETER
CONDITIONS
MIN
TYP
TA= +25°C
3.5
3.7
TA= –40°C to +85°C
3.4
UNITS
TEST
LEVEL (1)
V
A
V
B
1.5
V
A
1.6
V
B
VPP
B
VPP
B
mAP
A
mV
A
MAX
OUTPUT
Maximum output voltage high
Minimum output voltage low
Differential output voltage swing
Each output with
100 Ω to
midsupply
TA= +25°C
1.3
TA= –40°C to +85°C
TA= +25°C, RL = 200 Ω
4
4.8
TA= –40°C to +85°C
3.6
Differential output current drive
TA= +25°C, RL = 20 Ω
40
50
Output common-mode offset from
midsupply
TA= +25°C, RL = 20 Ω
–60
±10
Differential output impedance
f = 100 MHz
3.5 / 87
Ω/°
B
Differential output impedance model
Series ROUT,EQ, LOUT,EQ
0.3 / 3.8
Ω / nH
B
60
POWER SUPPLY
Specified operating voltage
Quiescent current
4.75
5
5.25
V
C
TA= +25°C
138
143
148
mA
A
TA= –40°C to +85°C
136
150
mA
B
dB
A
V
A
V
A
4
mA
A
4.8
mA
B
dB
C
TA= +25°C, Gain = 20 dB (2)
54
Device power-up voltage threshold
Ensured on above 2.1 V
2.1
Device power-down voltage threshold
Ensured off below 0.9 V
Power-supply rejection ratio (PSRR)
76
POWER DOWN
Power-down quiescent current
0.9
TA= +25°C
2
TA= –40°C to +85°C
Forward isolation in power-down state
f = 100 MHz
PD pin input bias current
PD= VS–
-110
0.5
PD pin input impedance
20 || 0.5
μA
B
kΩ || pF
C
Turn-on time delay
Measured to output on
16
ns
C
Turn-off time delay
Measured to output off
60
ns
C
GAIN SETTING
Gain range
–11.5
Gain control: G0 to G5
Gain step size
Gain error over entire gain range
–11.5 dB ≤ Gain ≤ +20 dB
+20
A
Bits
B
0.50
dB
A
Absolute gain error
–0.35
±0.05
0.35
dB
A
Step to step gain error
–0.10
±0.03
0.10
dB
A
0.0018
0.0022
0.0026
dB/°C
B
ns
B
V
A
Gain temp coefficient
Gain settling time
DIGITAL INPUTS
dB
6
5
B0 to B5 and Latch
Digital threshold low
0.9
Digital threshold high
2.1
V
A
Current into/out of digital pins
±20
nA
C
Data set up time to GAIN STROBE low
2.5
ns
C
0
ns
C
6.4
ns
C
Data hold time after GAIN STROBE
low
Latency time
(2)
PSRR is defined with respect to a differential output.
4
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
www.ti.com
SBOS436 – DECEMBER 2009
PIN CONFIGURATION
VMID1
PD
GND
VS+
GND
GND
GND
28
27
26
25
24
23
22
QFN-28
RHD PACKAGE
(TOP VIEW)
LATCH MODE
1
21
GND
VS+
2
20
VS+
IN+
3
19
OUT+
VMID2
4
18
GND
17
OUT-
16
VS+
15
GND
10
11
12
13
14
B3
VS+
B2
B1
B0
7
9
GAIN STROBE
PowerPADä
B4
6
8
5
(MSB) B5
INVS+
PIN ASSIGNMENTS
PIN NUMBER
1
PIN NAME
LATCH MODE
DESCRIPTION
Controls latched and unlatched acquisition of the gain control word (B0 to B5). See the application section Gain
Control Modes for a detailed description.
2, 6, 11, 16, 20, 25
VS+
+5V power supply
3
IN+
Noninverting input
4
VMID2
Buffer output for the internal midsupply reference. This point is the output of an active buffer which is not intended
to drive an external load. It should be bypassed by a 0.1-μF capacitor.
5
IN–
7
GAIN STROBE
Inverting input
8
B5 (MSB)
Gain control MSB
9
B4
Gain control bit 4
10
B3
Gain control bit 3
12
B2
Gain control bit 2
13
B1
Gain control bit 1
14
B0 (LSB)
Gain control bit 0
17
OUT–
Inverting output
15, 18, 21, 22, 23,
24, 26
GND
Ground
19
OUT+
Noninverting output
27
PD
28
VMID1
Thermal Pad
PowerPAD
Gain latch clock pin
Active low power-down for device analog circuitry. Gain control CMOS circuitry is still active when PD is low.
Chip bypass pin for internal midsupply reference. This point is the midpoint of a resistive voltage divider and is not
intended to function as an input. It should be bypassed with a 0.1-μF capacitor.
Thermal contact for heat dissipation. The thermal pad must be connected to electrical ground.
5
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
SBOS436 – DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
SMALL-SIGNAL AC RESPONSE
Gain Adjusted from –11.5 dB to +5 dB
Gain Adjusted in 0.5-dB Steps
VOUT = 200 mVPP
25
Gain Adjusted in 0.5-dB Steps
VOUT = 200 mVPP
Gain = +5 dB
5
20
0
15
Gain (dB)
Gain (dB)
10
SMALL-SIGNAL AC RESPONSE
Gain Adjusted from +5.5 dB to +20 dB
-5
-10
Gain = +20 dB
10
5
Gain = +5.5 dB
Gain = -11.5 dB
-15
0
10
100
1000
10
1000
Frequency (MHz)
Figure 1.
Figure 2.
LARGE-SIGNAL AC RESPONSE AT FOUR GAINS
DIFFERENTIAL INPUT
LARGE-SIGNAL AC RESPONSE AT FOUR GAINS
SINGLE-ENDED INPUT
30
30
25
25
Gain = 20 dB
20
15
15
Gain = 10 dB
10
5
Gain = 0 dB
0
Gain = -6 dB
-5
Gain = 20 dB
20
Gain (dB)
Gain (dB)
100
Frequency (MHz)
Gain = 10 dB
10
5
Gain = 0 dB
0
Gain = -6 dB
-5
-10
-10
Differential Input
VOUT = 2 VPP
-15
-20
-15
-20
10
100
1000
Single-Ended Input
VOUT = 2 VPP
10
100
1000
Frequency (MHz)
Frequency (MHz)
Figure 3.
Figure 4.
DIFFERENTIAL FREQUENCY RESPONSE vs CAPACITIVE LOAD
25
CL = 94 pF
20
ROS vs CAPACITIVE LOAD
100
CL = 44 pF
CL =
10 pF
15
ROS (W)
Gain (dB)
CL = 820 pF
CL = 470 pF
10
CL =
16 pF
ROS
CL
PGA870
5
ROS
10
ROS
CL
CL =
20 pF
VOUT
PGA870
CL
ROS
VOUT
CL
0
1
10
100
1000
1
Frequency (MHz)
10
100
1000
Capacitive Load (pF)
Figure 5.
Figure 6.
6
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
www.ti.com
SBOS436 – DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
STEP-TO-STEP GAIN ERROR vs GAIN SETTING
OVER TEMPERATURE
LARGE-SIGNAL GAIN vs GAIN SETTING
25
0.15
20
0.10
Gain Error (dB)
15
Gain (dB)
10
5
0
-40°C
0.05
+25°C
0
-0.05
-0.10
-5
50 MHz
100 MHz
200 MHz
-10
+85°C
-0.15
-15
-0.20
-12-10 -8 -6 -4 -2 0
2
4
6
8 10 12 14 16 18 20
-12-10 -8 -6 -4 -2 0
Gain Setting
Figure 7.
8 10 12 14 16 18 20
GAIN STEP RESPONSE: NO LATCH
1.5
Gain Control
3.5
0.02
Gain Code = 111111
1.0
Gain Control (V)
3.0
0
-0.02
-0.04
2.5
0.5
2.0
1.5
0
1.0
-0.5
0.5
0
50 MHz
100 MHz
200 MHz
-1.0
Gain Code = 000000
Amplifier
Output
-0.5
-1.0
-0.08
-12-10 -8 -6 -4 -2 0
2
4
6
-1.5
0
8 10 12 14 16 18 20
100
200
300
400
500
Time (ns)
Gain Setting
Figure 10.
GAIN STEP RESPONSE: LEVEL-TRIGGERED GAIN LATCH
GAIN STEP RESPONSE: EDGE-TRIGGERED LATCH
2.0
Gain Code =
111111
Gain Strobe
1.5
1.0
0.5
0.5
0
-0.5
-1.0
2.5
2.0
Gain Code = 111111
Gain
Strobe
1.5
1.0
Gain Code =
000000
0.5
1.0
0
0.5
0
-0.5
-1.0
Time (50 ns/div)
Time (50 ns/div)
Figure 11.
Figure 12.
Amplifier Output (V)
Gain Code =
000000
Amplifier Output (V)
1.0
0
Gain Control, Gain Strobe (V)
Figure 9.
2.5
Amplifier Output (V)
Gain Error (dB)
6
4.0
0.04
Gain Control, Gain Strobe (V)
4
Figure 8.
STEP-TO-STEP GAIN ERROR vs GAIN SETTING
OVER FREQUENCY
-0.06
2
Gain Setting
7
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
SBOS436 – DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
SECOND-ORDER INTERMODULATION DISTORTION
FOR FOUR OUTPUT LOADS (VOUT = 2 VPP)
-70
VOUT = 2 VPP
DF = 2 MHz
-75
-80
IMD3 (dBc)
IMD2 (dBc)
THIRD-ORDER INTERMODULATION DISTORTION
FOR TWO GAINS AND FOUR OUTPUT LOADS (VOUT = 2 VPP)
-85
-90
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1 kW
-95
-100
Gain = +10 dB
50
100
150
200
250
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
300
VOUT = 2 VPP
DF = 2 MHz
Dashed lines: Gain = -6 dB
Solid lines: Gain = +10 dB
50
100
150
Frequency (MHz)
200
250
300
Frequency (MHz)
Figure 13.
Figure 14.
SECOND-ORDER INTERMODULATION DISTORTION
FOR FOUR OUTPUT LOADS (VOUT = 2 VPP)
THIRD-ORDER INTERMODULATION DISTORTION
FOR TWO GAINS AND FOUR OUTPUT LOADS (VOUT = 2 VPP)
-70
VOUT = 2 VPP
DF = 2 MHz
-75
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1 kW
-80
IMD3 (dBc)
IMD2 (dBc)
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1 kW
-85
-90
-95
-100
Gain = +20 dB
50
100
150
200
250
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
300
VOUT = 2 VPP
DF = 2 MHz
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1 kW
Dashed lines: Gain = 0 dB
Solid lines: Gain = +20 dB
50
100
150
Frequency (MHz)
200
250
300
Frequency (MHz)
Figure 15.
Figure 16.
OUTPUT THIRD-ORDER INTERCEPT vs FREQUENCY
(VOUT = 2 VPP)
50
VOUT = 2 VPP
RL = 200 W
48
OIP3 (dBm)
46
44
42
40
Gain = +20 dB
Gain = +10 dB
Gain = 0 dB
Gain = -6 dB
38
36
50
100
150
200
250
300
Frequency (MHz)
Figure 17.
8
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
www.ti.com
SBOS436 – DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
SECOND-ORDER INTERMODULATION DISTORTION
FOR FOUR OUTPUT LOADS (VOUT = 3 VPP)
-70
THIRD-ORDER INTERMODULATION DISTORTION
FOR TWO GAINS AND FOUR OUTPUT LOADS (VOUT = 3 VPP)
Gain = +10 dB
-80
IMD3 (dBc)
IMD2 (dBc)
-75
-85
-90
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1 kW
-95
VOUT = 3 VPP
DF = 2 MHz
-100
50
100
150
200
250
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
300
VOUT = 3 VPP
DF = 2 MHz
Dashed lines: Gain = -6 dB
Solid lines: Gain = +10 dB
50
100
150
Frequency (MHz)
200
250
300
Frequency (MHz)
Figure 18.
Figure 19.
SECOND-ORDER INTERMODULATION DISTORTION
FOR FOUR OUTPUT LOADS (VOUT = 3 VPP)
THIRD-ORDER INTERMODULATION DISTORTION
FOR TWO GAINS AND FOUR OUTPUT LOADS (VOUT = 3 VPP)
-70
VOUT = 3 VPP
DF = 2 MHz
-75
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1 kW
-80
IMD3 (dBc)
IMD2 (dBc)
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1 kW
-85
-90
-95
-100
Gain = +20 dB
50
100
150
200
250
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
300
VOUT = 3 VPP
DF = 2 MHz
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1 kW
Dashed lines: Gain = 0 dB
Solid lines: Gain = +20 dB
50
100
150
Frequency (MHz)
200
250
300
Frequency (MHz)
Figure 20.
Figure 21.
OUTPUT THIRD-ORDER INTERCEPT vs FREQUENCY
(VOUT = 3 VPP)
52
VOUT = 3 VPP
RL = 200 W
50
OIP3 (dBm)
48
46
44
42
40
Gain = +20 dB
Gain = +10 dB
38
50
100
Gain = 0 dB
Gain = -6 dB
150
200
250
300
Frequency (MHz)
Figure 22.
9
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
SBOS436 – DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
-55
-70
-60
-75
-65
-80
-70
-85
-75
-90
-80
Dashed lines: 2nd Harmonic
Solid lines: 3rd Harmonic
-95
-100
Gain = -6 dB
Gain = 0 dB
-105
Gain = +10 dB
Gain = +20 dB
-110
100
150
200
250
-45
VOUT = 2 VPP
RL = 200 W
-60
-65
-50
-55
-70
-60
-75
-65
-80
-70
-85
-75
-90
Dashed lines: 2nd Harmonic
Solid lines: 3rd Harmonic
-95
-100
Gain = -6 dB
Gain = 0 dB
-105
Gain = +10 dB
Gain = +20 dB
-110
0
50
100
150
200
250
Frequency (MHz)
Frequency (MHz)
Figure 23.
Figure 24.
HARMONIC DISTORTION vs FREQUENCY
(VOUT = 2 VPP)
HARMONIC DISTORTION vs FREQUENCY
(VOUT = 2 VPP)
-45
-50
-55
-70
-60
-75
-65
-80
-70
-85
-75
-90
-80
-95
Dashed lines: 2nd Harmonic
Solid lines: 3rd Harmonic
Gain = -6 dB
Gain = +10 dB
Gain = +20 dB
Gain = 0 dB
-100
-105
-110
0
-55
50
100
150
200
250
-85
-90
-95
-100
300
-55
-65
-85
-90
-95
-100
300
-45
VOUT = 2 VPP
RL = 1 kW
-60
-80
-50
-55
-70
-60
-75
-65
-80
-70
-85
-75
-90
-80
-95
Dashed lines: 2nd Harmonic
Solid lines: 3rd Harmonic
Gain = -6 dB
Gain = +10 dB
Gain = +20 dB
Gain = 0 dB
-100
-105
-110
0
50
100
150
200
Frequency (MHz)
Frequency (MHz)
Figure 25.
Figure 26.
10
250
-85
-90
-95
Third-Order Harmonic Distortion (dBc)
-65
-95
-100
300
VOUT = 2 VPP
RL = 500 W
-60
-90
Third-Order Harmonic Distortion (dBc)
-55
50
-85
Second-Order Harmonic Distortion (dBc)
-50
Second-Order Harmonic Distortion (dBc)
-65
0
Second-Order Harmonic Distortion (dBc)
-45
VOUT = 2 VPP
RL = 100 W
-60
Third-Order Harmonic Distortion (dBc)
-55
HARMONIC DISTORTION vs FREQUENCY
(VOUT = 2 VPP)
Third-Order Harmonic Distortion (dBc)
Second-Order Harmonic Distortion (dBc)
HARMONIC DISTORTION vs FREQUENCY
(VOUT = 2 VPP)
-100
300
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
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SBOS436 – DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
-50
-70
-55
-75
-60
-80
-65
-85
-70
-90
-75
Dashed lines: 2nd Harmonic
Solid lines: 3rd Harmonic
-95
-100
Gain = -6 dB
Gain = 0 dB
-105
Gain = +10 dB
Gain = +20 dB
-110
100
150
200
250
-40
VOUT = 3 VPP
RL = 200 W
-60
-65
-45
-50
-70
-55
-75
-60
-80
-65
-85
-70
-90
Dashed lines: 2nd Harmonic
Solid lines: 3rd Harmonic
-95
-100
Gain = -6 dB
Gain = 0 dB
-105
Gain = +10 dB
Gain = +20 dB
-110
0
50
100
150
200
250
Frequency (MHz)
Frequency (MHz)
Figure 27.
Figure 28.
HARMONIC DISTORTION vs FREQUENCY
(VOUT = 3 VPP)
HARMONIC DISTORTION vs FREQUENCY
(VOUT = 3 VPP)
-40
-45
-50
-70
-55
-75
-60
-80
-65
-85
-70
-90
-75
Dashed lines: 2nd Harmonic
Solid lines: 3rd Harmonic
-95
-100
Gain = -6 dB
Gain = 0 dB
-105
Gain = +10 dB
Gain = +20 dB
-110
0
-55
50
100
150
200
250
-80
-85
-90
-95
300
-55
-65
-80
-85
-90
-95
300
-40
VOUT = 3 VPP
RL = 1 kW
-60
-75
-45
-50
-70
-55
-75
-60
-80
-65
-85
-70
-90
Dashed lines: 2nd Harmonic
Solid lines: 3rd Harmonic
-95
-100
Gain = -6 dB
Gain = 0 dB
-105
Gain = +10 dB
Gain = +20 dB
-110
0
50
100
150
200
Frequency (MHz)
Frequency (MHz)
Figure 29.
Figure 30.
250
-75
-80
-85
-90
Third-Order Harmonic Distortion (dBc)
-65
-90
-95
300
VOUT = 3 VPP
RL = 500 W
-60
-85
Third-Order Harmonic Distortion (dBc)
-55
50
-80
Second-Order Harmonic Distortion (dBc)
-45
Second-Order Harmonic Distortion (dBc)
-65
0
Second-Order Harmonic Distortion (dBc)
-40
VOUT = 3 VPP
RL = 100 W
-60
Third-Order Harmonic Distortion (dBc)
-55
HARMONIC DISTORTION vs FREQUENCY
(VOUT = 3 VPP)
Third-Order Harmonic Distortion (dBc)
Second-Order Harmonic Distortion (dBc)
HARMONIC DISTORTION vs FREQUENCY
(VOUT = 3 VPP)
-95
300
11
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
SBOS436 – DECEMBER 2009
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TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
NOISE FIGURE vs GAIN
DISABLE STEP RESPONSE
45
2.25
f = 100 MHz
RSYS = 150 W
Noise Figure (dB)
35
30
25
20
0.9
1.50
0.6
1.25
0.3
1.00
0
0.75
-0.3
0.50
-0.6
0.25
-0.9
15
0
10
-12-10 -8 -6 -4 -2 0
2 4
6
-1.5
100
8 10 12 14 16 18 20 22
200
400
500
Time (ns)
Figure 32.
LARGE- AND SMALL-SIGNAL
DIFFERENTIAL PULSE RESPONSE
FORWARD ISOLATION vs FREQUENCY
IN DISABLED MODE
0.15
1.0
0.10
0.5
0.05
0
0
-0.05
Left Scale
-1.0
-0.10
Right Scale
-1.5
-60
Forward Isolation (dB)
Gain = 20 dB, RL = 200 W
Small-Signal Differential Output (V)
Large-Signal Differential Output (V)
300
Figure 31.
1.5
-0.15
0
-1.2
Amplifier Output
-0.25
Gain (dB)
-0.5
1.2
1.75
5
10
15
20
Amplifier Output (V)
Disable Signal Amplitude (V)
40
1.5
Disable Signal
2.00
-80
-100
-120
-140
25
0
Time (2.5 ns/div)
100
200
300
400
500
Frequency (MHz)
Figure 33.
Figure 34.
DIFFERENTIAL INPUT IMPEDANCE
DIFFERENTIAL INPUT RETURN LOSS
vs FREQUENCY
4
0
0
-10
ZSYS = 150 W
150
-4
140
Phase
130
-8
120
-12
110
-16
100
100 k
-20
1M
10 M
100 M
1G
Input Return Loss (dB)
Magnitude
Input Impedance Phase (°)
Input Impedance Magnitude (W)
160
-20
-30
-40
20 dB
10 dB
0 dB
-6 dB
-50
-60
100 M
Frequency (Hz)
1G
Frequency (Hz)
Figure 35.
Figure 36.
12
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
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SBOS436 – DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS+= +5 V, differential input signal, differential VOUT = 2 VPP, RL = 200 Ω differential, G = +20 dB, and input and
output common-mode at internal midsupply reference, unless otherwise noted.
SINGLE-ENDED INPUT RETURN LOSS
vs FREQUENCY
DIFFERENTIAL OUTPUT IMPEDANCE
100
0
Input Return Loss (dB)
-5
-10
-15
-20
-25
20 dB
10 dB
0 dB
-6 dB
-30
-35
10 M
100 M
1G
100
80
70
10
60
50
40
1
30
Magnitude
20
10
0.1
10 k
100 k
1M
0
100 M 300 M
10 M
Frequency (Hz)
Frequency (Hz)
Figure 37.
Figure 38.
DIFFERENTIAL OUTPUT SWING
vs RLOAD
PSRR AND CMRR
vs FREQUENCY
90
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
5.5
Differential Output Swing (V)
90
Phase
Output Impedance Phase (°)
Output Impedance Magnitude (W)
ZSYS = 150 W
5.0
4.5
4.0
80
70
PSRR
60
CMRR
50
40
30
20
10
0
3.5
100
1k
10 k
1k
Differential Load Resistance, RLOAD (W)
Figure 39.
10 k
100 k
1M
10 M
100 M
1G
Frequency (Hz)
Figure 40.
13
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SBOS436 – DECEMBER 2009
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APPLICATION INFORMATION
Device Operation
The PGA870 is a wideband, fully differential, programmable-gain amplifier. Looking at the block diagram in
Figure 41, the PGA870 can be separated into the following functional blocks:
•
•
•
•
•
Input Attenuator
Buffered MUX
Output Amplifier
8-bit digital interface
Power function
Attenuator
1
IN-
VS
Gain = +20 dB
2
OUTOutput
Amp
Buffered
MUX
VMID2
OUT+
7
8
IN+
BIAS
Control
Gain Control
PGA870
B0 B1
Gain Latch
Strobe Mode (LSB)
B2
B3
B4
B5
(MSB)
Disable
Figure 41. PGA870 Block Diagram
Input Attenuator
The input stage of the PGA870 consists of a logarithmic R2R ladder and presents a 150-Ω load to the previous
stage. To minimize input return loss and noise figure, it is recommended to provide a 150-Ω matching for that
input. This input can be driven either differentially or single-ended.
This resistive input network is internally biased to midsupply by an internal buffer (VMID2 on pin 4). Proper
bypassing is required on this node (0.1 μF). The buffer midsupply is generated by a passive resistor network
(VMID1 on pin 28). A 0.1-μF capacitor is expected on VMID1 for adequate bypassing. Although VMID1 and VMID2 are
externally accessible, neither of these pins is intended to be externally driven. Additionally, VMID2 is not intended
to drive the midsupply reference to another chip, but can source approximately 200 μA if required.
During power-down operation, the input maintains its nominal differential resistance. However, VMD1 and VMID2
fall to 0 V.
The input attenuator is controlled via the three most significant bits (MSBs) of the gain control. Refer to Table 1
for the step size of each of these three MSBs.
Input Amplifier and Buffered MUX
Following the input attenuator is a programmable buffer stage; the gain of the programmable buffer is controlled
by the three least significant bits (LSBs) of the gain-control word. Refer to Table 1 for the step size of each of
these three LSBs.
14
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PGA870
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SBOS436 – DECEMBER 2009
Table 1. Gain Bits and Corresponding Gain Step Sizes (in dB)
(MSB)
B5
B4
B3
B2
B1
(LSB)
B0
16
8
4
2
1
0.5
Output Amplifier
The PGA870 has a differential, voltage-mode output stage with a differential output resistance of approximately
0.3 Ω and an inductive reactance equivalent to 3.8 nH. The common-mode output voltage has a nominal value of
VMID2. This output amplifier has a nominal gain of +20 dB.
The nominal load is 200 Ω, but the PGA870 can drive loads as low as 100 Ω with only minor changes to the
device distortion.
The output pins go to a high-impedance state when the device is the power-down state (that is, when PD is low).
8-bit Digital Interface
The 8-bit digital interface is composed of six bits: three MSBs that control the input attenuation and three LSBs
that control the input amplifier and buffered MUX. For more information on this parallel interface, refer to the Gain
Control and Latch Modes section.
Power function
The PGA870 features a low-power disabled state for the analog circuitry when the power-down (PD) pin is low.
In the disabled state, the digital circuitry remains active, which allows the gain to be set before device power-up.
There is no internal circuitry to provide a nominal bias to this pin. If this pin is to be left open, it must be biased
with an external pull-up resistor.
Note that when the PGA870 is in this low-power mode, the gain can be programmed using the 8-bit digital
interface, the output pins go to a high-impedance state, and the voltage on the midsupply pins biasing the
attenuator (pin 4 and pin 28) goes to 0 V.
Gain Control and Latch Modes
The PGA870 has six bits of gain control (B5 to B0) that give an extended gain range from a maximum gain of 20
dB to a minimum gain of –11.5 dB. The LSB (B0) represents a minimum gain change (step size) of 0.5 dB, and
the LSB (B5) represents a gain change of 16 dB. The equivalent gain step size of each gain control bit is shown
in Table 1. The device voltage gain can be expressed by the following equation:
GaindB= 20 dB − 0.5 dB × (NG− 63)
NG is the equivalent base-10 integer number that corresponds to the binary gain control word. A summary of the
63 possible device gains versus NG and the values of B0 to B5 are shown in Table 2.
The high and low voltage thresholds allow all of the gain control pins to be controlled by CMOS circuitry. There
are no internal pull-up resistors on the gain-control pins. If the pins are to be left open, they must be biased with
external pull-up resistors.
The PGA870 can be configured so the device gain is controlled by only the six gain bits (no latch) when the
GAIN STROBE pin and the GAIN MODE pin are both held high. In this operating mode, the device voltage gain
follows the signals on pins B0 to B5. Transients on the six gain bits can cause changes to the PGA870 gain
while in this mode, as well. To combat this possibility, the PGA870 also supports two gain modes where the gain
bit data are acquired and latched by signals on the GAIN STROBE pin.
The device is configured for a level-triggered latch when the LATCH MODE pin is high; this configuration allows
the six gain bits to be acquired and latched only on a high signal on the GAIN STROBE. When the GAIN
STROBE signal goes low, the gain-control data are latched and the PGA870 gain is independent of the six gain
bits until the GAIN STROBE goes high again.
If the PGA870 LATCH MODE pin is low, the device is configured for an edge-triggered latch that acquires and
latches the six gain-control bits only on the falling edge of the GAIN STROBE signal.
15
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SBOS436 – DECEMBER 2009
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Table 2. PGA870 Gain and Corresponding Gain Word Values
Gain
State
NG
B1
(LSB)
B0
Gain
State
NG
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
17
1
1
56
16.5
1
55
16
54
Gain
(dB)
(MSB)
B5
B4
B3
B2
Gain
(dB)
(MSB)
B5
B4
B3
B2
B1
(LSB)
B0
63
20
1
1
1
62
19.5
1
1
1
31
4
0
1
1
1
1
1
30
3.5
0
1
1
1
1
61
19
1
1
0
1
29
3
0
1
1
1
0
60
18.5
1
1
0
0
28
2.5
0
1
1
1
0
0
59
18
58
17.5
0
1
1
27
2
0
1
1
0
1
1
0
1
0
26
1.5
0
1
1
0
1
57
0
1
0
0
1
25
1
0
1
1
0
0
1
1
1
0
0
0
24
0.5
0
1
1
0
0
0
1
1
0
1
1
1
23
0
0
1
0
1
1
1
15.5
1
1
0
1
1
0
22
-0.5
0
1
0
1
1
0
53
15
1
1
0
1
0
1
21
-1
0
1
0
1
0
1
52
14.5
1
1
0
1
0
0
20
-1.5
0
1
0
1
0
0
51
14
1
1
0
0
1
1
19
-2
0
1
0
0
1
1
50
13.5
1
1
0
0
1
0
18
-2.5
0
1
0
0
1
0
49
13
1
1
0
0
0
1
17
-3
0
1
0
0
0
1
48
12.5
1
1
0
0
0
0
16
-3.5
0
1
0
0
0
0
47
12
1
0
1
1
1
1
15
-4
0
0
1
1
1
1
46
11.5
1
0
1
1
1
0
14
-4.5
0
0
1
1
1
0
45
11
1
0
1
1
0
1
13
-5
0
0
1
1
0
1
44
10.5
1
0
1
1
0
0
12
-5.5
0
0
1
1
0
0
43
10
1
0
1
0
1
1
11
-6
0
0
1
0
1
1
42
9.5
1
0
1
0
1
0
10
-6.5
0
0
1
0
1
0
41
9
1
0
1
0
0
1
9
-7
0
0
1
0
0
1
40
8.5
1
0
1
0
0
0
8
-7.5
0
0
1
0
0
0
39
8
1
0
0
1
1
1
7
-8
0
0
0
1
1
1
38
7.5
1
0
0
1
1
0
6
-8.5
0
0
0
1
1
0
37
7
1
0
0
1
0
1
5
-9
0
0
0
1
0
1
36
6.5
1
0
0
1
0
0
4
-9.5
0
0
0
1
0
0
35
6
1
0
0
0
1
1
3
-10
0
0
0
0
1
1
34
5.5
1
0
0
0
1
0
2
-10.5
0
0
0
0
1
0
33
5
1
0
0
0
0
1
1
-11
0
0
0
0
0
1
32
4.5
1
0
0
0
0
0
0
-11.5
0
0
0
0
0
0
Table 3. Gain Control Signals and Latch Modes
Latch Mode
GAIN STROBE
LATCH MODE
CONDITION
Edge-triggered latch
Falling edge
Low
Device gain follows and latches gain control word (B0
to B5) only on GAIN STROBE falling edge.
Level-triggered latch
Low
High
Device gain follows gain control word (B0 to B5) when
GAIN STROBE and LATCH MODE are both high.
Device gain latches when GAIN STROBE goes low.
No latch
High
High
Device gain is level-triggered on the gain-control word
(B0 to B5) when LATCH MODE is high and GAIN
STROBE remains high.
16
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SBOS436 – DECEMBER 2009
Table 3 and Figure 42 show a summary table and timing diagrams of the gain modes, respectively. Figure 43
illustrates a timing diagram that defines the transitions and timing of the set-up and hold times for both
level-triggered and edge-triggered latch modes.
Latched on
Gain Strobe
Falling Edge
Latched on
Gain Strobe
High Level
No Latch
Follows
Gain Control Word
1
Gain Strobe
0
1
Latch Mode
0
Gain Bits 1
B5 to B0
(MSB to LSB)
0
1
Gain
0
Figure 42. Gain Mode Timing
1
Gain Bits
B5 to B0
(MSB to LSB)
0
tSU
tHOLD
1
Gain Strobe
0
1
tLATENCY
Gain
0
1
Latch Mode
0
Figure 43. Set-Up and Hold Times: Level-Triggered and Edge-Triggered Latch Modes
17
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Single-Ended to Differential Operation
Figure 44 represents a single-ended to differential conversion test configuration with a 50-Ω source and a 200-Ω
load. The midsupply pins VMID1 and VMID2 are properly bypassed; because this circuit is ac-coupled, these pins
provide the biasing voltage required by the PGA870 input stage. The LATCH MODE, GAIN STROBE, and PD
pins are connected to the supply voltage through a pull-up resistor. The PD pin set high powers up the PGA870,
while setting the LATCH MODE and GAIN STROBE pins high bypasses the latch mode, allowing instantaneous
gain changes as B5 to B0 change. On the noninverting input, a 75-Ω resistance was added to adapt the 150 Ω to
50 Ω and match the 50-Ω source.
If a differential signal source is to be dc-coupled to the device, it should have a common-mode voltage that is
within 0.2 V of the midsupply reference. If the input common-mode/dc voltage is greater than 0.2 V from
midsupply, then increased distortion and reduced performance can result. The non-driven input pin of the
PGA870 should be ac-coupled to ground through a capacitor. If a single-ended signal source is dc-coupled to an
input pin, and the non-driven input pin is grounded, the PGA870 amplifies the desired signal as well as the
difference between the offset from the PGA870 midsupply reference, VMID1.
+5 V
1k W
From 50-W
Source
0.1 mF
IN+
LM
75 W
(1)
(1)
GS
VMID2
PD
OUT+
0.1 mF
PGA870
200 W
VMID1
0.1 mF
OUTB0 to B5
IN-
0.1 mF
B0 to B5
(1)
LM = LATCH MODE pin (pin 1), GS = GAIN STROBE pin (pin 7).
Figure 44. Basic Connections for Single-Ended to Differential Conversion
18
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PGA870
www.ti.com
SBOS436 – DECEMBER 2009
Differential-to-Differential Operation
Differential operation of PGA870 is shown in Figure 45. In this example, both input pins are connected to a
differential 150-Ω source. The PGA870 is driving a typical 200-Ω load. Both midsupply voltage pins VMID1 and
VMID2 are bypassed with a 0.1-μF capacitor. The LATCH MODE, GAIN STROBE, and PD pins are connected to
the power supply using a 1-kΩ pull-up resistor. The PD pin set high powers up the PGA870, while setting the
Latch Mode and the Gain Strobe pins high bypasses the latch mode, allowing instantaneous gain changes as B5
to B0 change.
+5 V
1k W
From 150-W
Differential Source
0.1 mF
IN+
LM
(1)
(1)
GS
VMID2
PD
OUT+
0.1 mF
VMID1
PGA870
0.1 mF
200 W
OUTB0 to B5
IN-
0.1 mF
B0 to B5
(1)
LM = LATCH MODE pin (pin 1), GS = GAIN STROBE pin (pin 7).
Figure 45. Basic Connections for Fully Differential Operation
PCB Layout Recommendations
Complete information about the PGA870EVM is found in the PGA870EVM User Guide, available for download
through the PGA870 product folder on the TI web site. Printed circuit board (PCB) layout should follow these
general guidelines:
1. Signal routing should be direct and as short as possible into and out of the device input and output pins.
Routing the signal path between layers using vias should be avoided if possible.
2. The device PowerPAD should be connected to a solid ground plane with multiple vias. The PowerPAD must
be connected to electrical ground. Consult the PGA870EVM User Guide for a layout example.
3. Ground or power planes should be removed from directly under the amplifier output pins.
4. A 0.1-μF capacitor should be placed between the VMIDpin and ground near to the pin.
5. An output resistor is recommended in each output lead, placed as near to the output pins as possible.
6. Two 0.1-μF power-supply decoupling capacitors should be placed as near to the power-supply pins as
possible.
7. Two 10-μF power-supply decoupling capacitors should be placed within 1 in (2,54 cm) of the device.
8. The digital control pins use CMOS logic levels for high and low signals, but can tolerate being pulled high to
a +5-V power supply. The digital control pins do not have internal pull-up resistors.
19
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA870
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PGA870IRHDR
ACTIVE
VQFN
RHD
28
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PGA870IRHDT
ACTIVE
VQFN
RHD
28
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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