TI THS4524IDBT

TH
THS4521
THS4522
THS4524
S4
521
TH
TH
S4
S4
524
522
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
VERY LOW POWER, NEGATIVE RAIL INPUT, RAIL-TO-RAIL OUTPUT,
FULLY DIFFERENTIAL AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
1
2
•
•
Fully Differential Architecture
Bandwidth: 145 MHz
Slew Rate: 490 V/µs
HD2: –133 dBc at 10 kHz (1 VRMS, RL = 1 kΩ)
HD3: –140 dBc at 10 kHz (1 VRMS, RL = 1 kΩ)
Input Voltage Noise: 4.6 nV/√Hz (f = 100 kHz)
NRI—Negative Rail Input
RRO—Rail-to-Rail Output
Output Common-Mode Control (with Low
Offset and Drift)
Power Supply:
– Voltage: +2.5 V (±1.25 V) to +5.5 V (±2.75 V)
– Current: 1.14 mA/ch
Power-Down Capability: 20 µA (typ)
THS4521 and ADS1278 Combined Performance
1 kW
1.5 nF
5V
49.9 W
1 kW
AINN1
VIN+
THS4521
2.2 nF
49.9 W
VIN-
ADS1278 (CH 1)
AINP1
1 kW
VOCM
1/2
OPA2350
1.5 nF
DESCRIPTION
The THS4521, THS4522, and THS4524 family of
devices are very low-power, fully differential op amps
with rail-to-rail output and an input common-mode
range that includes the negative rail. These amplifiers
are designed for low-power data acquisition systems
and
high-density
applications
where
power
dissipation is a critical parameter.
The family includes single (THS4521),
(THS4522), and quad (THS4524) versions.
dual
These fully differential op amps feature accurate
output common-mode control that allows for
dc-coupling when driving analog-to-digital converters
(ADCs). This control, coupled with an input
common-mode range below the negative rail as well
as rail-to-rail output, allows for easy interfacing
between single-ended, ground-referenced signal
sources. Additionally, these devices are ideally suited
for driving both successive-approximation register
(SAR) and delta-sigma (ΔΣ) ADCs using only a single
+3V to +5V and ground power supply.
VCOM
x1
0.1 mF
Low-Power SAR and ΔΣ ADC Drivers
Low-Power Differential Driver
Low-Power Differential Signal Conditioning
0.1 mF
The THS4521, THS4522, and THS4524 family of fully
differential op amps is characterized for operation
over the full industrial temperature range from –40°C
to +85°C.
1 kW
1-kHz FFT
0
-20
Magnitude (dBFS)
RELATED
PRODUCTS
G=1
RF = RG = 1 kW
CF = 1.5 nF
VS = 5 V
Load = 2 x 49.9 W + 2.2 nF
-80
DEVICE
BW
(MHz)
IQ (mA)
THD
(dBc)
at 100
kHz
-100
THS4520
570
15.3
–114
2
Out
-120
THS4121
100
16
–79
5.4
In/Out
-140
THS4130
150
16
–107
1.3
No
-40
-60
VN
RAIL(nV/√Hz) TO-RAIL
-160
0
4
8
12
16
20
24 26
Frequency (kHz)
Tone
(Hz)
1k
Signal
(dBFS)
-0.50
SNR (dBc)
THD (dBc)
109.1
-107.9
SINAD
(dBc)
105.5
SFDR
(dBc)
113.7
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PACKAGE
DESIGNATOR
SOIC-8
D
MSOP-8
DGK
THS4522
TSSOP-16
PW
–40°C to +85°C
THS4522
THS4524
TSSOP-38
DBT
–40°C to +85°C
THS4524
PRODUCT
THS4521
(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGELEAD
PACKAGE
MARKING
ORDERING
NUMBER
TH4521
–40°C to +85°C
4521
TRANSPORT MEDIA,
QUANTITY
THS4521ID
Rails, 75
THS4521IDR
Tape and reel, 2500
THS4521IDGKT
Tape and reel, 250
THS4521IDGKR
Tape and reel, 2500
THS4522IPW
Rails, 90
THS4522IPWR
Tape and reel, 2000
THS4524IDBT
Rails, 50
THS4524IDBTR
Tape and reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
THS4521, THS4522. THS4524
UNIT
Supply Voltage, VS– to VS+
PARAMETER
5.5
V
Input Voltage, VI
±VS
V
Differential Input Voltage, VID
Output Current, IO
Continuous Power Dissipation
1
V
100
mA
See Thermal Characteristic Specifications
Maximum Junction Temperature, TJ
+150
°C
Maximum Junction Temperature, TJ (continuous operation, long-term reliability)
+125
°C
Operating Free-air Temperature Range, TA
–40 to +85
°C
Storage Temperature Range, TSTG
–65 to +150
°C
Lead Temperature [1,6 mm (1/16 inch) from case for 10 seconds]
ESD
Rating:
300
°C
Human Body Model (HBM)
1300
V
Charge Device Model (CDM)
1000
V
50
V
Machine Model (MM)
(1)
2
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
THS4521
THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3.3 V
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, input and output referenced to midsupply, unless otherwise noted.
THS4521, THS4522, THS4524
UNIT
TEST
LEVEL (1)
135
MHz
C
VOUT = 100 mVPP, G = 2
49
MHz
C
VOUT = 100 mVPP, G = 5
18.6
MHz
C
VOUT = 100 mVPP, G = 10
9.3
MHz
C
Gain Bandwidth Product
VOUT = 100 mVPP, G = 10
93
MHz
C
Large-Signal Bandwidth
VOUT = 2 VPP, G = 1
95
MHz
C
Bandwidth for 0.1-dB Flatness
VOUT = 2 VPP, G = 1
20
MHz
C
Rising Slew Rate (Differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
420
V/µs
C
Falling Slew Rate (Differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
460
V/µs
C
Overshoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
1.2
%
C
Undershoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
2.1
%
C
Rise Time
VOUT = 2-V Step, G = 1, RL = 200 Ω
4
ns
C
Fall Time
VOUT = 2-V Step, G = 1, RL = 200 Ω
3.5
ns
C
Settling Time to 1%
VOUT = 2-V Step, G = 1, RL = 200 Ω
13
ns
C
f = 10 kHz, VOUT = 1 VRMS
–133
dBc
C
f = 1 MHz, VOUT = 2 VPP
–85
dBc
C
f = 10 kHz, VOUT = 1 VRMS
–140
dBc
C
f = 1 MHz, VOUT = 2 VPP
–90
dBc
C
Second-Order Intermodulation Distortion
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
VOUT = 2-VPP envelope
–83
dBc
C
Third-Order Intermodulation Distortion
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
VOUT = 2-VPP envelope
–90
dBc
C
Input Voltage Noise
f > 10 kHz
4.6
nV/√Hz
C
Input Current Noise
f > 100 kHz
0.6
pA/√Hz
C
Overdrive = ±0.5 V
80
ns
C
VOUT = 100 mV, f ≤ 2 MHz (differential input)
–57
dB
C
f = 1 MHz (differential)
0.3
Ω
C
f = 10 kHz, measured differentially
–125
dB
C
PARAMETER
CONDITIONS
MIN
TYP
MAX
AC PERFORMANCE
Small-Signal Bandwidth
VOUT = 100 mVPP, G = 1
Harmonic Distortion
2nd harmonic
3rd harmonic
Overdrive Recovery Time
Output Balance Error
Closed-Loop Output Impedance
Channel-to-Channel Crosstalk (THS4522,
THS4524)
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
100
Input-Referred Offset Voltage
Input offset voltage drift (2)
Input Bias Current
Input bias current drift (2)
Input Offset Current
Input offset current drift (2)
(1)
(2)
dB
A
TA = +25°C
±0.2
116
±2
mV
A
TA = –40°C to +85°C
±0.5
±3.5
mV
B
TA = –40°C to +85°C
±2
µV/°C
C
TA = +25°C
0.65
0.85
µA
B
TA = –40°C to +85°C
0.75
0.95
µA
B
TA = –40°C to +85°C
±1.75
±2
nA/°C
B
TA = +25°C
±50
±60
pA
B
TA = –40°C to +85°C
±60
±70
pA
B
TA = –40°C to +85°C
±0.16
±0.25
pA/°C
B
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at –40°C
and +85°C, computing the difference, and dividing by 125.
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
Submit Documentation Feedback
3
THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, input and output referenced to midsupply, unless otherwise noted.
THS4521, THS4522, THS4524
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
–0.2
–0.1
V
A
–0.1
0
INPUT
Common-Mode Input Voltage Low
TA = +25°C
TA = –40°C to +85°C
Common-Mode Input Voltage High
V
B
TA = +25°C
1.9
2
V
A
TA = –40°C to +85°C
1.8
1.9
V
B
80
100
dB
A
110 1.5
kΩ pF
C
Common-Mode Rejection Ratio (CMRR)
Input Resistance
OUTPUT
Output Voltage Low
Output Voltage High
TA = +25°C
0.08
0.15
V
A
TA = –40°C to +85°C
0.09
0.2
V
B
A
TA = +25°C
3.0
3.1
V
TA = –40°C to +85°C
2.95
3.05
V
B
±35
mA
C
RL = 50 Ω
Output Current Drive (for linear operation)
POWER SUPPLY
Specified Operating Voltage
2.5
Quiescent Operating Current, per channel
5.5
V
B
TA = +25°C
0.9
1.0
1.2
mA
A
TA = –40°C to +85°C
0.85
1.0
1.25
mA
B
80
100
dB
A
V
A
Power-Supply Rejection Ratio (±PSRR)
POWER DOWN
Enable Voltage Threshold
Assured on above 2.1 V
Disable Voltage Threshold
Assured off below 0.7 V
1.6
0.7
Disable Pin Bias Current
2.1
1.6
V
A
1
µA
C
10
µA
C
Turn-On Time Delay
Time to VOUT = 90% of final value, VIN= 2 V,
RL = 200 Ω
108
ns
B
Turn-Off Time Delay
Time to VOUT = 10% of original value, VIN= 2
V, RL = 200 Ω
88
ns
B
Small-Signal Bandwidth
23
MHz
C
Slew Rate
55
V/µs
C
Power Down Quiescent Current
VOCM VOLTAGE CONTROL
Gain
0.98
Measured at VOUT with VOCM input driven,
VOCM = 1.65 V ±0.5 V
Common-Mode Offset Voltage from VOCM Input
Input Bias Current
VOCM = 1.65 V ±0.5 V
VOCM Voltage Range
1
Input Impedance
0.99
1.02
V/V
A
±2.5
±4
mV
B
±5
±8
µA
B
0.8 to 2.5
2.3
V
A
kΩ pF
C
mV
A
–40 to +85
°C
C
72 1.5
Default Output Common-Mode Voltage Offset from
(VS+– VS–)/2
Measured at VOUT with VOCM input open
±1.5
±5
THERMAL CHARACTERISTICS
Specified Operating Range
All Packages
Thermal Resistance, θJA
THS4521
Junction-to-ambient
D
SO-8
194
°C/W
C
DGK
MSOP-8
269
°C/W
C
THS4522
PW
TSSOP-16
116
°C/W
C
THS4524
DBT
TSSOP-38
81
°C/W
C
4
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
THS4521
THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
ELECTRICAL CHARACTERISTICS: VS+ – VS– = 5 V
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, input and output referenced to midsupply, unless otherwise noted.
THS4521, THS4522, THS4524
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
Small-Signal Bandwidth
VOUT = 100 mVPP, G = 1
145
MHz
C
VOUT = 100 mVPP, G = 2
50
MHz
C
VOUT = 100 mVPP, G = 5
20
MHz
C
VOUT = 100 mVPP, G = 10
9.5
MHz
C
Gain Bandwidth Product
VOUT = 100 mVPP, G = 10
95
MHz
C
Large-Signal Bandwidth
VOUT = 2 VPP, G = 1
145
MHz
C
Bandwidth for 0.1-dB Flatness
VOUT = 2 VPP, G = 1
30
MHz
C
Rising Slew Rate (Differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
490
V/µs
C
Falling Slew Rate (Differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
600
V/µs
C
Overshoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
1
%
C
Undershoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
2.6
%
C
Rise Time
VOUT = 2-V Step, G = 1, RL = 200 Ω
3.4
ns
C
Fall Time
VOUT = 2-V Step, G = 1, RL = 200 Ω
3
ns
C
Settling Time to 1%
VOUT = 2-V Step, G = 1, RL = 200 Ω
10
ns
C
f = 10 kHz, VOUT = 1 VRMS
–133
dBc
C
f = 1 MHz, VOUT = 2 VPP
–85
dBc
C
f = 10 kHz, VOUT = 1 VRMS
–140
dBc
C
f = 1 MHz, VOUT = 2 VPP
–91
dBc
C
Second-Order Intermodulation Distortion
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
VOUT = 2-VPP envelope
–86
dBc
C
Third-Order Intermodulation Distortion
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
VOUT = 2-VPP envelope
–93
dBc
C
Input Voltage Noise
f > 10 kHz
4.6
nV/√Hz
C
Input Current Noise
f > 100 kHz
0.6
pA/√Hz
C
Overdrive = ±0.5 V
75
ns
C
VOUT = 100 mV, f < 2 MHz, VIN differential
–57
dB
C
f = 1 MHz (differential)
0.3
Ω
C
f = 10 kHz, measured differentially
–125
dB
C
Harmonic Distortion
2nd harmonic
3rd harmonic
Overdrive Recovery Time
Output Balance Error
Closed-Loop Output Impedance
Channel-to-Channel Crosstalk (THS4522.
THS4524)
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
100
Input-Referred Offset Voltage
Input offset voltage drift (2)
Input Bias Current
Input bias current drift (2)
Input Offset Current
Input offset current drift (2)
(1)
(2)
dB
A
TA = +25°C
±0.24
119
±2
mV
A
TA = –40°C to +85°C
±0.5
±3.5
mV
B
TA = –40°C to +85°C
±2
µV/°C
B
TA = +25°C
0.7
0.9
µA
B
TA = –40°C to +85°C
0.9
1.1
µA
B
TA = –40°C to +85°C
±1.8
±2.2
nA/°C
B
TA = +25°C
±50
±60
pA
B
TA = –40°C to +85°C
±60
±75
pA
B
TA = –40°C to +85°C
±0.16
±0.25
pA/°C
B
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at –40°C
and +85°C, computing the difference, and dividing by 125.
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
Submit Documentation Feedback
5
THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, input and output referenced to midsupply, unless otherwise noted.
THS4521, THS4522, THS4524
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
–0.2
–0.1
V
A
–0.1
0
INPUT
Common-Mode Input Voltage Low
TA = +25°C
TA = –40°C to +85°C
Common-Mode Input Voltage High
V
B
TA = +25°C
3.6
3.7
V
A
TA = –40°C to +85°C
3.5
3.6
V
B
80
102
dB
A
100 0.7
kΩ pF
C
Common-Mode Rejection Ratio (CMRR)
Input Impedance
OUTPUT
Output Voltage Low
Output Voltage High
TA = +25°C
0.10
0.15
V
A
TA = –40°C to +85°C
0.115
0.2
V
B
A
TA = +25°C
4.7
4.75
V
TA = –40°C to +85°C
4.65
4.7
V
B
±55
mA
C
RL = 50 Ω
Output Current Drive (for linear operation)
POWER SUPPLY
Specified Operating Voltage
2.5
Quiescent Operating Current, per channel
5.5
V
B
TA = +25°C
0.95
1.14
1.25
mA
A
TA = –40°C to +85°C
0.9
1.15
1.3
mA
B
80
100
dB
A
V
A
Power-Supply Rejection Ratio (±PSRR)
POWER DOWN
Enable Voltage Threshold
Ensured on above 2.1 V
Disable Voltage Threshold
Ensured off below 0.7 V
1.6
0.7
Disable Pin Bias Current
2.1
1.6
V
A
1
µA
C
20
µA
C
Turn-On Time Delay
Time to VOUT = 90% of final value, VIN= 2 V,
RL = 200 Ω
70
ns
B
Turn-Off Time Delay
Time to VOUT = 10% of original value, VIN= 2
V, RL = 200 Ω
60
ns
B
Small-Signal Bandwidth
23
MHz
C
Slew Rate
55
V/µs
C
Power Down Quiescent Current
VOCM VOLTAGE CONTROL
Gain
0.98
Measured at VOUT with VOCM input driven,
VOCM = 2.5V ±1 V
Common-Mode Offset Voltage from VOCM Input
Input Bias Current
VOCM = 2.5V ±1 V
VOCM Voltage Range
1
Input Impedance
0.99
1.02
V/V
A
±5
±9
mV
B
±20
±25
µA
B
0.8 to 4.2
4
V
A
kΩ pF
C
±5
mV
A
+85
°C
C
46 1.5
Default Output Common-Mode Voltage Offset from
(VS+– VS–)/2
Measured at VOUT with VOCM input open
±1
THERMAL CHARACTERISTICS
Specified Operating Range
All Packages
–40
Thermal Resistance, θJA
THS4521
Junction-to-ambient
D
SO-8
194
°C/W
C
DGK
MSOP-8
269
°C/W
C
THS4522
PW
TSSOP-16
116
°C/W
C
THS4524
DBT
TSSOP-38
81
°C/W
C
6
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
THS4521
THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
DEVICE INFORMATION
THS4521
SOIC-8, MSOP-8 (D, DGK PACKAGES)
(TOP VIEW)
THS4522
TSSOP-16 (PW PACKAGE)
(TOP VIEW)
VIN- 1
8
VIN+
PD1
1
16
VS-
VOCM 2
7
PD
VIN1+
2
15
VOUT1-
VS+ 3
6
VS-
VIN1-
3
14
VOUT1+
VOUT+ 4
5
VOUT-
VOCM1
4
13
VS1+
PD2
5
12
VS-
VIN2+
6
11
VOUT2-
VIN2-
7
10
VOUT2+
VOCM2
8
9
VS2+
TERMINAL FUNCTIONS: THS4521
SOIC-8, MSOP-8
PIN NO.
NAME
1
VIN–
DESCRIPTION
2
VOCM
3
VS+
4
VOUT+
Noninverting amplifier output
5
VOUT–
Inverting amplifier output
6
VS–
Amplifier negative power-supply input. Note that VS– is tied together on multi-channel devices.
7
PD
Power down. PD = logic low puts device into low-power mode. PD = logic high or open for normal
operation.
8
VIN+
Noninverting amplifier input
Inverting amplifier input
Common-mode voltage input
Amplifier positive power-supply input
TERMINAL FUNCTIONS: THS4522
TSSOP-16
PIN NO.
NAME
DESCRIPTION
1
PD 1
Power down 1. PD = logic low puts device into low-power mode. PD = logic high or open for normal
operation.
2
VIN1+
Noninverting amplifier 1 input
3
VIN1–
Inverting amplifier 1 input
4
VOCM1
Common-mode voltage input 1
5
PD 2
Power down 2. PD = logic low puts device into low-power mode. PD = logic high or open for normal
operation.
6
VIN2+
Noninverting amplifier 2 input
7
VIN2–
Inverting amplifier 2 input
8
VOCM2
Common-mode voltage input 2
9
VS+2
10
VOUT2+
Noninverting amplifier 2 output
11
VOUT2–
Inverting amplifier 2 output
12
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
13
VS+1
Amplifier 1 positive power-supply input
14
VOUT1+
Noninverting amplifier 1 output
15
VOUT1–
Inverting amplifier 1 output
16
VS–
Amplifier 2 positive power-supply input
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
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THS4522
THS4524
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THS4524
TSSOP-38 (DBT PACKAGE)
(TOP VIEW)
8
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PD1
1
38
VS-
VIN1+
2
37
VOUT1-
VIN1-
3
36
VOUT1+
VOCM1
4
35
VS1+
VS-
5
34
VS-
PD2
6
33
VS-
VIN2+
7
32
VOUT2-
VIN2-
8
31
VOUT2+
VOCM2
9
30
VS2+
VS-
10
29
VS-
PD3
11
28
VS-
VIN3+
12
27
VOUT3-
VIN3-
13
26
VOUT3+
VOCM3
14
25
VS3+
VS-
15
24
VS-
PD4
16
23
VS-
VIN4+
17
22
VOUT4-
VIN4-
18
21
VOUT4+
VOCM4
19
20
VS4+
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
THS4521
THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
TERMINAL FUNCTIONS: THS4524
TSSOP-38
PIN NO.
NAME
DESCRIPTION
1
PD 1
Power down 1. PD = logic low puts channel into low-power mode. PD = logic high or open for
normal operation.
2
VIN1+
Noninverting amplifier 1 input
3
VIN1–
Inverting amplifier 1 input
4
VOCM1
Common-mode voltage input 1
5
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
6
PD 2
Power down 2. PD = logic low puts channel into low-power mode. PD = logic high or open for
normal operation.
7
VIN2+
Noninverting amplifier 2 input
8
VIN2–
Inverting amplifier 2 input
Common-mode voltage input 2
9
VOCM2
10
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
11
PD 3
Power down 3. PD = logic low puts channel into low-power mode. PD = logic high or open for
normal operation.
12
VIN3+
Noninverting amplifier 3 input
13
VIN3–
Inverting amplifier 3 input
14
VOCM3
Common-mode voltage input 3
15
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
16
PD 4
Power down 4. PD = logic low puts channel into low-power mode. PD = logic high or open for
normal operation.
17
VIN4+
Noninverting amplifier 4 input
18
VIN4–
Inverting amplifier 4 input
19
VOCM4
Common-mode voltage input 4
20
VS4+
21
VOUT4+
Amplifier 4 positive power-supply input
Noninverting amplifier 4 output
22
VOUT4–
Inverting amplifier 4 output
23
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
24
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
25
VS3+
Amplifier 3 positive power-supply input
26
VOUT3+
Noninverting amplifier3 output
27
VOUT3–
Inverting amplifier3 output
28
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
29
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
30
VS2+
Amplifier 2 positive power-supply input
31
VOUT2+
Noninverting amplifier 2 output
32
VOUT2–
Inverting amplifier 2 output
33
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
34
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
35
VS1+
Amplifier 1 positive power-supply input
36
VOUT1+
Noninverting amplifier 1 output
37
VOUT1–
Inverting amplifier 1 output
38
VS–
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
Copyright © 2008–2009, Texas Instruments Incorporated
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THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs: VS+ – VS– = 3.3 V
TITLE
FIGURE
Small-Signal Frequency Response
Figure 1
Large-Signal Frequency Response
Figure 2
Large- and Small-Signal Pulse Response
Figure 3
Slew Rate vs VOUT Step
Figure 4
Overdrive Recovery
Figure 5
10-kHz Output Spectrum on AP Analyzer
Figure 6
Harmonic Distortion vs Frequency
Figure 7
Harmonic Distortion vs Output Voltage at 1 MHz
Figure 8
Harmonic Distortion vs Gain at 1 MHz
Figure 9
Harmonic Distortion vs Load at 1 MHz
Figure 10
Harmonic Distortion vs VOCM at 1 MHz
Figure 11
Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency
Figure 12
Single-Ended Output Voltage Swing vs Load Resistance
Figure 13
Main Amplifier Differential Output Impedance vs Frequency
Figure 14
Frequency Response vs CLOAD (RLOAD = 1 kΩ)
Figure 15
RO vs CLOAD (RLOAD = 1 kΩ)
Figure 16
Rejection Ratio vs Frequency
Figure 17
THS4522, THS4524 Crosstalk (Measured Differentially)
Figure 18
Turn-on Time
Figure 19
Turn-off Time
Figure 20
Input-Referred Voltage Noise and Current Noise Spectral Density
Figure 21
Main Amplifier Differential Open-Loop Gain and Phase
Figure 22
Output Balance Error vs Frequency
Figure 23
VOCM Small-Signal Frequency Response
Figure 24
VOCM Large-Signal Frequency Response
Figure 25
VOCM Input Impedance vs Frequency
Figure 26
10
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THS4522
THS4524
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Table of Graphs: VS+ – VS– = 5 V
TITLE
FIGURE
Small-Signal Frequency Response
Figure 27
Large-Signal Frequency Response
Figure 28
Large- and Small-Signal Pulse Response
Figure 29
Slew Rate vs VOUT Step
Figure 30
Overdrive Recovery
Figure 31
10-kHz Output Spectrum on AP Analyzer
Figure 32
Harmonic Distortion vs Frequency
Figure 33
Harmonic Distortion vs Output Voltage at 1 MHz
Figure 34
Harmonic Distortion vs Gain at 1 MHz
Figure 35
Harmonic Distortion vs Load at 1 MHz
Figure 36
Harmonic Distortion vs VOCM at 1 MHz
Figure 37
Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency
Figure 38
Single-Ended Output Voltage Swing vs Load Resistance
Figure 39
Main Amplifier Differential Output Impedance vs Frequency
Figure 40
Frequency Response vs CLOAD (RLOAD = 1 kΩ)
Figure 41
RO vs CLOAD (RLOAD = 1 kΩ)
Figure 42
Rejection Ratio vs Frequency
Figure 43
THS4522, THS4524 Crosstalk (Measured Differentially)
Figure 44
Turn-on Time
Figure 45
Turn-off Time
Figure 46
Input-Referred Voltage Noise and Current Noise Spectral Density
Figure 47
Main Amplifier Differential Open-Loop Gain and Phase
Figure 48
Output Balance Error vs Frequency
Figure 49
VOCM Small-Signal Frequency Response
Figure 50
VOCM Large-Signal Frequency Response
Figure 51
VOCM Input Impedance vs Frequency
Figure 52
Copyright © 2008–2009, Texas Instruments Incorporated
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THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: VS+ – VS– = 3.3 V
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, and input and output referenced to midsupply, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
6
6
3
G = 1 V/V
0
-3
Normalized Gain (dB)
Normalized Gain (dB)
3
G = 2 V/V
-6
G = 5 V/V
-9
-12
G = 10 V/V
-15
VS+ = 3.3 V
RL = 1 kW
VO = 100 mVPP
-18
-21
-24
100 k
G = 1 V/V
0
G = 2 V/V
-3
-6
G = 5 V/V
-9
-12
G = 10 V/V
-15
VS+ = 3.3 V
RL = 1 kW
VO = 2.0 VPP
-18
-21
1M
10 M
100 M
-24
100 k
1G
Figure 1.
Figure 2.
SLEW RATE vs VOUT
Rising
500
0
Slew Rate (V/ms)
Differential VOUT (V)
0.5
0.5-V Step
-0.5
-1.0
40
60
100
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 200 W
1
OVERDRIVE RECOVERY
10-kHz OUTPUT SPECTRUM ON
AP ANALYZER
2.0
0.5
0
0
-1
-0.5
VS+ = 3.3 V
G = 2 V/V
RF = 1 kW
RL = 200 W
-1.0
-1.5
-2.0
300 400 500 600
800 900
1k
Input Voltage (V)
1
Magnitude (dBv)
1.5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
VOUT = 5 VPP
0
5k
Generator
THS4521
10 k
15 k
20 k
25 k
30 k
35 k
Frequency (Hz)
Figure 5.
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5
4
Figure 4.
Time (ns)
12
3
2
Figure 3.
1.0
100 200
0
Differential VOUT (V)
2
0
200
Time (ns)
3
Differential VOUT (V)
80
VOUT Diff
Input
-4
300
0
20
4
-3
Falling
100
-1.5
-2
400
2-V Step
0
1G
600
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 200 W
1.0
100 M
Frequency (Hz)
LARGE- AND SMALL-SIGNAL PULSE RESPONSE
1.5
10 M
1M
Frequency (Hz)
Figure 6.
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
THS4521
THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
TYPICAL CHARACTERISTICS: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, and input and output referenced to midsupply, unless otherwise noted.
HARMONIC DISTORTION
vs VOUT AT 1 MHZ
HARMONIC DISTORTION vs FREQUENCY
Harmonic Distortion (dBc)
-50
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
VOUT = 2.0 VPP
-20
-30
-40
-50
Third
Harmonic
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
f = 1 MHz
-55
Harmonic Distortion (dBc)
-10
Second
Harmonic
-60
-70
-80
-90
-100
-60
-65
-70
-75
Second
Harmonic
-80
-85
-90
Third
Harmonic
-95
-110
-100
10
1
100
1
3
2
Frequency (MHz)
Figure 7.
Figure 8.
HARMONIC DISTORTION
vs GAIN AT 1 MHZ
HARMONIC DISTORTION
vs LOAD AT 1 MHZ
-70
-75
Second
Harmonic
-80
-85
VS+ = 3.3 V
RF = 1 kW
RL = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
Third
Harmonic
-90
-95
-100
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-70
-75
Second
Harmonic
-80
-85
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-90
-95
Third
Harmonic
-100
1
3
2
5
4
6
7
8
9
10
0
100 200
Gain (V/V)
-50
-60
-70
HARMONIC DISTORTION
vs VOCM AT 1 MHZ
TWO-TONE INTERMODULATION DISTORTION
vs FREQUENCY
-10
-90
Third
Harmonic
-100
0
0.5
900
Figure 10.
Second
Harmonic
-80
800
Figure 9.
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-40
300 400 500 600
1.0
1.5
1k
Load (W)
2.0
2.5
3.0
Intermodulation Distortion (dBc)
-30
Harmonic Distortion (dBc)
6
5
4
VOUT (VPP)
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
VOUT = 2.0 VPP
envelope
-20
-30
-40
-50
Second
Intermodulation
-60
-70
Third
Intermodulation
-80
-90
-100
-110
1
10
VOCM (V)
Frequency (MHz)
Figure 11.
Figure 12.
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100
13
THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, and input and output referenced to midsupply, unless otherwise noted.
SINGLE-ENDED OUTPUT VOLTAGE SWING
vs LOAD RESISTANCE
3.5
100
Differential Output Impedance (W)
Linear Voltage Range
VOCM = 1.65 V
3.0
Single-Ended VOUT (V)
MAIN AMPLIFIER DIFFERENTIAL OUTPUT IMPEDANCE
vs FREQUENCY
2.5
VOUT max
2.0
1.5
VOUT min
1.0
0.5
100
1k
1
0.1
0.01
100 k
0
10
10
10 k
Figure 13.
Figure 14.
FREQUENCY RESPONSE vs CLOAD
RLOAD = 1 kΩ
RO vs CLOAD
RLOAD = 1 kΩ
1k
5
CL = 4.7 pF
RO = 150 W
CL = 1000 pF
RO = 7.15 W
-5
-10
100
RO (W)
Normalized Gain (dB)
0
CL = 100 pF
RO = 35.7 W
10
-15
CL = 10 pF
RO = 124 W
-20
1
-25
100 k
1M
100 M
10 M
10
1G
Figure 15.
Figure 16.
REJECTION RATIO vs FREQUENCY
THS4522, THS4524
CROSSTALK (MEASURED DIFFERENTIALLY)
Channel-to-Channel Crosstalk (dB)
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
90
80
CMRR
70
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
-PSRR
+PSRR
-105
-110
-115
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
Active Channel VOUT = 1 VRMS
-120
-125
-130
-135
-140
100 k
10 M
1M
100 M
10
100
Frequency (Hz)
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1k
10 k
100 k
1M
Frequency (Hz)
Figure 17.
14
1000
CLOAD (pF)
-100
10 k
100
Frequency (Hz)
110
50
100 M
Frequency (Hz)
Load Resistance (W)
60
10 M
1M
Figure 18.
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
THS4521
THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
TYPICAL CHARACTERISTICS: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, and input and output referenced to midsupply, unless otherwise noted.
TURN-ON TIME
3.5
3.0
1.5
2.0
1.0
1.5
VOUT Diff
PD
1.0
2.5
40
60
80
100 120
1.2
1.0
1.5
0.8
0.6
VOUT Diff
PD
0.5
140 160
0.2
0
0
180 200
20
40
60
80
100 120
140 160 180 200
Time (ns)
Time (ns)
Figure 19.
Figure 20.
INPUT-REFERRED VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY
MAIN AMPLIFIER
DIFFERENTIAL OPEN-LOOP GAIN AND PHASE
100
0
120
Gain
Voltage
Noise
10
Current
Noise
1
OPen-Loop Gain (dB)
100
80
-45
60
40
-90
20
Phase
0
0
10
100
1k
10 k
100 k
1M
-135
-20
10
1
100
1k
Frequency (Hz)
10 k
100 k
1M
10 M 100 M
Frequency (Hz)
Figure 21.
Figure 22.
OUTPUT BALANCE ERROR
vs FREQUENCY
-20
Open-Loop Phase (Degrees)
Input-Referred Voltage Noise (nV/ÖHz)
Input-Referred Current Noise (pA/ÖHz)
0.4
0
0
20
1.4
1.0
0.5
0
1.6
2.0
0.5
0
1.8
Differential VOUT (V)
2.5
2.0
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 200 W
2.0
Differential VOUT (V)
3.0
PD Pulse (V)
TURN-OFF TIME
3.5
2.5
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 200 W
PD Pulse (V)
4.0
VOCM SMALL-SIGNAL FREQUENCY RESPONSE
0
G = 0 dB
-30
-5
-35
Gain (dB)
Output Balance Error (dB)
-25
-40
-45
-50
-15
G = 0 dB
VIN = -20 dBm
-55
-60
100 k
-10
10 M
1M
100 M
-20
100 k
1M
10 M
Frequency (Hz)
Frequency (Hz)
Figure 23.
Figure 24.
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
100 M
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1G
15
THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, and input and output referenced to midsupply, unless otherwise noted.
VOCM INPUT IMPEDANCE
vs FREQUENCY
VOCM LARGE-SIGNAL PULSE RESPONSE
100 k
2.3
2.1
1.9
1.7
1.5
1.3
1.1
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
0.9
0.7
0.5
0
16
VOCM Input Impedance (W)
VOUT Common-Mode Voltage (V)
2.5
100
200
300
400
10 k
1k
100
100 k
10 M
1M
Time (ns)
Frequency (Hz)
Figure 25.
Figure 26.
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100 M
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THS4522
THS4524
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TYPICAL CHARACTERISTICS: 5 V
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
6
6
3
3
G = 1 V/V
-3
Normalized Gain (dB)
Normalized Gain (dB)
0
G = 2 V/V
-6
G = 5 V/V
-9
-12
G = 10 V/V
-15
VS+ = 5.0 V
RL = 1 kW
VO = 100 mVPP
-18
-21
-24
100 k
G = 1 V/V
0
-3
G = 2 V/V
-6
G = 5 V/V
-9
-12
G = 10 V/V
-15
VS+ = 5.0 V
RL = 1 kW
VO = 2.0 VPP
-18
-21
1M
10 M
100 M
-24
100 k
1G
Figure 27.
Figure 28.
SLEW RATE vs VOUT
700
0
0.5-V Step
-0.5
40
60
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 200 W
100
1
2
3
4
5
Differential VOUT (V)
Figure 29.
Figure 30.
OVERDRIVE RECOVERY
10-kHz OUTPUT SPECTRUM ON
AP ANALYZER AT VOUT = 8 VPP
3
VOUT Diff
Input
2
1
0
0
-1
VS+ = 5 V
G = 2 V/V
RF = 1 kW
RL = 200 W
-2
-3
300 400 500 600 700 800 900
1k
Input Voltage (V)
2
100 200
0
Time (ns)
4
Differential VOUT (V)
80
Magnitude (dBv)
20
6
0
300
0
0
-6
Rising
400
100
-1.5
-4
500
200
2-V Step
-1.0
-2
Falling
600
Slew Rate (V/ms)
Differential VOUT (V)
0.5
1G
800
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 200 W
1.0
100 M
Frequency (Hz)
LARGE- AND SMALL-SIGNAL PULSE RESPONSE
1.5
10 M
1M
Frequency (Hz)
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
VS+ = 5.0 V
G = 1 V/V
RF = 1 kW
VOUT = 8 VPP
0
5k
6
7
Generator
THS4521
10 k
Time (ns)
15 k
20 k
25 k
30 k
35 k
Frequency (Hz)
Figure 31.
Figure 32.
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THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: 5 V (continued)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
HARMONIC DISTORTION
vs VOUT AT 1 MHZ
HARMONIC DISTORTION vs FREQUENCY
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
VOUT = 2.0 VPP
Harmonic Distortion (dBc)
-20
-30
-40
-50
-70
Third
Harmonic
Harmonic Distortion (dBc)
-10
Second
Harmonic
-60
-70
-80
-90
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
f = 1 MHz
-75
-80
Second
Harmonic
-85
Third
Harmonic
-90
-95
-100
-100
-110
10
1
100
1
2
3
Frequency (MHz)
HARMONIC DISTORTION
vs GAIN AT 1 MHZ
HARMONIC DISTORTION
vs LOAD AT 1 MHZ
8
-70
-75
Second
Harmonic
-80
-85
VS+ = 5 V
RF = 1 kW
RL = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-90
Third
Harmonic
-95
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
7
6
Figure 34.
-100
-75
Second
Harmonic
-80
-85
VS+ = 5 V
G = 1 V/V
RF = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-90
-95
Third
Harmonic
-100
1
2
3
5
4
6
7
8
9
10
0
100 200
-30
-60
-70
HARMONIC DISTORTION
vs VOCM AT 1 MHZ
TWO-TONE INTERMODULATION DISTORTION
vs FREQUENCY
-10
Third
Harmonic
-80
900
Figure 36.
Intermodulation Distortion (dBc)
-50
800
Figure 35.
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-40
300 400 500 600
1k
Load (W)
Gain (V/V)
Harmonic Distortion (dBc)
5
Figure 33.
-70
Second
Harmonic
-90
-100
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
VOUT = 2.0 VPP
envelope
-20
-30
-40
-50
-60
Second
Intermodulation
-70
-80
-90
Third
Intermodulation
-100
-110
0
18
4
VOUT (VPP)
1.0
2.0
3.0
4.0
5.0
10
1
VOCM (V)
Frequency (MHz)
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTICS: 5 V (continued)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
SINGLE-ENDED OUTPUT VOLTAGE SWING
vs DIFFERENTIAL LOAD RESISTANCE
5.0
100
Differential Output Impedance (W)
Linear Voltage Range
VOCM = 2.5 V
4.5
Single-Ended VOUT (V)
MAIN AMPLIFIER DIFFERENTIAL OUTPUT IMPEDANCE
vs FREQUENCY
4.0
3.5
VOUT max
3.0
2.5
2.0
VOUT min
1.5
1.0
0.5
100
1k
1
0.1
0.01
100 k
0
10
10
10 k
Figure 39.
Figure 40.
FREQUENCY RESPONSE vs CLOAD
RLOAD = 1 kΩ
RO vs CLOAD
RLOAD = 1 kΩ
1k
5
CL = 4.7 pF
RO = 150 W
0
CL = 1000 pF
RO = 7.15 W
100
RO (W)
-5
-10
CL = 100 pF
RO = 35.7 W
-15
10
CL = 10 pF
RO = 124 W
-20
-25
100 k
1
1M
100 M
10 M
10
1G
100
1000
Frequency (Hz)
CLOAD (pF)
Figure 41.
Figure 42.
REJECTION RATIO vs FREQUENCY
THS4522, THS4524
CROSSTALK (MEASURED DIFFERENTIALLY)
110
VS+ = 5.0 V
G = 1 V/V
RF = 1 kW
100
90
80
CMRR
70
-PSRR
60
+PSRR
50
-100
Channel-to-Channel Crosstalk (dB)
Normalized Gain (dB)
100 M
Frequency (Hz)
Load Resistance (W)
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
10 M
1M
-105
-110
-115
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
Active Channel VOUT = 1 VRMS
-120
-125
-130
-135
-140
10 k
100 k
10 M
1M
100 M
10
100
Frequency (Hz)
Figure 43.
1k
10 k
100 k
1M
Frequency (Hz)
Figure 44.
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THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: 5 V (continued)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
TURN-ON TIME
3.5
3.0
1.5
2.0
1.0
1.5
1.0
2.5
0
0
20
40
60
80
100 120
140 160
1.0
1.5
0.8
0.6
1.0
0.4
VOUT Diff
PD
0.2
0
0
0
0
180 200
20
40
60
80
100 120
140 160 180 200
Time (ns)
Time (ns)
Figure 45.
Figure 46.
INPUT-REFERRED VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY
MAIN AMPLIFIER
DIFFERENTIAL OPEN-LOOP GAIN AND PHASE
100
0
120
Gain
Voltage
Noise
10
Current
Noise
1
OPen-Loop Gain (dB)
100
80
-45
60
40
-90
20
Phase
0
0
10
100
1k
10 k
100 k
1M
-135
-20
10
1
100
1k
Frequency (Hz)
10 k
100 k
1M
10 M 100 M
Frequency (Hz)
Figure 47.
Figure 48.
OUTPUT BALANCE ERROR
vs FREQUENCY
-20
Open-Loop Phase (Degrees)
Input-Referred Voltage Noise (nV/ÖHz)
Input-Referred Current Noise (pA/ÖHz)
1.4
1.2
0.5
VOUT Diff
PD
1.6
2.0
0.5
0.5
1.8
Differential VOUT (V)
2.5
2.0
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 200 W
2.0
Differential VOUT (V)
3.0
PD Pulse (V)
TURN-OFF TIME
3.5
2.5
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 200 W
PD Pulse (V)
4.0
VOCM SMALL-SIGNAL FREQUENCY RESPONSE
0
G = 0 dB
-30
-5
-35
Gain (dB)
Output Balance Error (dB)
-25
-40
-45
-50
-15
G = 0 dB
VIN = -20 dBm
-55
-60
100 k
20
-10
10 M
1M
100 M
-20
100 k
1M
10 M
Frequency (Hz)
Frequency (Hz)
Figure 49.
Figure 50.
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1G
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TYPICAL CHARACTERISTICS: 5 V (continued)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
VOCM INPUT IMPEDANCE
vs FREQUENCY
VOCM LARGE-SIGNAL PULSE RESPONSE
100 k
3.3
VOCM Input Impedance (W)
VOUT Common-Mode Voltage (V)
3.5
3.1
2.9
2.7
2.5
2.3
2.1
VS+ = 5.0 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
1.9
1.7
1.5
0
100
200
300
400
10 k
1k
100
100 k
10 M
1M
Time (ns)
Frequency (Hz)
Figure 51.
Figure 52.
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THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
TEST CIRCUITS
Overview
The THS4521, THS4522, and THS4524 family is
tested with the test circuits shown in this section; all
circuits are built using the available THS4521
evaluation
module
(EVM).
For
simplicity,
power-supply decoupling is not shown; see the layout
in the Applications section for recommendations.
Depending on the test conditions, component values
change in accordance with Table 1 and Table 2, or
as otherwise noted. In some cases the signal
generators used are ac-coupled and in others they
dc-coupled 50-Ω sources. To balance the amplifier
when ac-coupled, a 0.22-µF capacitor and 49.9-Ω
resistor to ground are inserted across RIT on the
alternate input; when dc-coupled, only the 49.9-Ω
resistor to ground is added across RIT. A split power
supply is used to ease the interface to common test
equipment, but the amplifier can be operated in a
single-supply configuration as described in the
Applications section with no impact on performance.
Also, for most of the tests, except as noted, the
devices are tested with single-ended inputs and a
transformer on the output to convert the differential
output to single-ended because common lab test
equipment has single-ended inputs and outputs.
Similar or better performance can be expected with
differential inputs and outputs.
As a result of the voltage divider on the output formed
by the load component values, the amplifier output is
attenuated. The Atten column in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output (as shown in
Figure 54), the signal sees slightly more loss because
of transformer and line loss; these numbers are
approximate.
Table 2. Load Component Values For 1:1
Differential to Single-Ended Output Transformer(1)
RL
RO
ROT
100 Ω
24.9 Ω
Open
6 dB
200 Ω
86.6 Ω
69.8 Ω
16.8 dB
499 Ω
237 Ω
56.2 Ω
25.5 dB
1 kΩ
487 Ω
52.3 Ω
31.8 dB
1. Total load includes 50-Ω termination by the test
equipment. Components are chosen to achieve
load and 50-Ω line termination through a 1:1
transformer.
Frequency Response
The circuit shown in Figure 53 is used to measure the
frequency response of the circuit.
An HP network analyzer is used as the signal source
and the measurement device. The output impedance
of the HP network analyzer is is dc-coupled and is
50 Ω. RIT and RG are chosen to impedance-match to
50 Ω and maintain the proper gain. To balance the
amplifier, a 49.9-Ω resistor to ground is inserted
across RIT on the alternate input.
The output is probed using a Tektronix
high-impedance differential probe across the 953-Ω
resistor and referred to the amplifier output by adding
back the 0.42-dB because of the voltage divider on
the output.
From
50-W
Source
VIN+
RG
Calibrated
Differential
Probe
Across
RIT
1 kW
VS+
RIT
24.9 W
PD
Open
THS452x
0.22 mF
Table 1. Gain Component Values for
Single-Ended Input(1)
Gain
RF
RG
RIT
1 V/V
1 kΩ
1 kΩ
52.3 Ω
2 V/V
1 kΩ
487 Ω
53.6 Ω
5 V/V
1 kΩ
187 Ω
59.0 Ω
10 V/V
1 kΩ
86.6 Ω
69.8 Ω
Atten
VOCM
Installed to
Balance
Amplifier
VS-
RIT
49.9 W
RG
24.9 W
953 W
Measure with
Differential
Probe
Across ROT
Open
0.22 mF
1 kW
Figure 53. Frequency Response Test Circuit
1. Gain setting includes 50-Ω source impedance.
Components are chosen to achieve gain and
50-Ω input termination.
22
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Distortion
The circuit shown in Figure 54 is used to measure
harmonic and intermodulation distortion of the
amplifier.
An HP signal generator is used as the signal source
and the output is measured with a Rhode and
Schwarz spectrum analyzer. The output impedance
of the HP signal generator is ac-coupled and is 50 Ω.
RIT and RG are chosen to impedance match to 50 Ω
and maintain the proper gain. To balance the
amplifier, a 0.22-µF capacitor and 49.9-Ω resistor to
ground are inserted across RIT on the alternate input.
A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
The level of the fundamental is measured and then a
high-pass filter is inserted at the output to reduce the
fundamental so it does not generate distortion in the
input of the spectrum analyzer.
Slew Rate, Transient Response, Settling
Time, Output Impedance, Overdrive, Output
Voltage, and Turn-On/Turn-Off Time
The circuit shown in Figure 55 is used to measure
slew rate, transient response, settling time, output
impedance, overdrive recovery, output voltage swing,
and ampliifer turn-on/turn-off time. Turn-on and
turn-off time are measured with the same circuit
modified for 50-Ω input impedance on the PD input
by replacing the 0.22-µF capacitor with a 49.9-Ω
resistor. For output impedance, the signal is injected
at VOUT with VIN open; the drop across the 2x 49.9-Ω
resistors is then used to calculate the impedance
seen looking into the amplifier output.
From
50-W
Source
VIN+
RG
RIT
49.9 W
PD
Open
The transformer used in the output to convert the
signal from differential to single-ended is an
ADT1–1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
approximately 1 MHz.
From
50-W
Source
VIN+
RG
RF
VS+
RIT
VOUT
RO
PD
Open
THS452x
0.22 mF
VOCM
Installed to
Balance
Amplifier
VS0.22 mF
RIT
RG
RO
1:1
ROT
To 50-W
Test
Equipment
1 kW
VS+
THS452x
0.22 mF
VOCM
Installed to
Balance
Amplifier
VS-
49.9 W
RIT
RG
49.9 W
VOUT-
VOUT+
To Oscilloscope
with 50-W Input
Open
0.22 mF
1 kW
Figure 55. Slew Rate, Transient Response,
Settling Time, Output Impedance, Overdrive
Recovery, VOUT Swing, and Turn-On/Turn-Off Test
Circuit
Open
0.22 mF
RF
49.9 W
Figure 54. Distortion Test Circuit
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space
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Common-Mode and Power-Supply Rejection
VOCM Input
The circuit shown in Figure 56 is used to measure the
CMRR. The signal from the network analyzer is
applied common-mode to the input. Figure 57 is used
to measure the PSRR of VS+ and VS–. The power
supply under test is applied to the network analyzer
dc offset input. For both CMRR and PSRR, the output
is probed using a Tektronix high-impedance
differential probe across the 953-Ω resistor and
referred to the amplifier output by adding back the
0.42-dB as a result of the voltage divider on the
output. For these tests, the resistors are matched for
best results.
The circuit illustrated in Figure 58 is used to measure
the frequency response and input impedance of the
VOCM input. Frequency response is measured using a
Tektronix high-impedance differential probe, with
RCM = 0 Ω at the common point of VOUT+ and VOUT–,
formed at the summing junction of the two matched
499-Ω resistors, with respect to ground. The input
impedance is measured using a Tektronix
high-impedance differential probe at the VOCM input
with RCM = 10 kΩ and the drop across the 10-kΩ
resistor is used to calculate the impedance seen
looking into the amplifier VOCM input.
From
Network
Analyzer
VIN+
1 kW
1 kW
VS+
24.9 W
PD
Open
Calibrated
Differential
Probe
THS452x
24.9 W
0.22 mF
52.3 W
VOCM
953 W
Measure with
Differential
Probe
Open
0.22 mF
VS-
The circuit shown in Figure 59 measures the transient
response and slew rate of the VOCM input. A 1-V step
input is applied to the VOCM input and the output is
measured using a 50-Ω oscilloscope input referenced
back to the amplifier output.
1 kW
1 kW
Open
VS+
49.9 W
1 kW
1 kW
499 W
Figure 56. CMRR Test Circuit
PD
Open
THS452x
0.22 mF
499 W
RCM
VOCM
VS
Power
Supply
Open
1 kW
1 kW
49.9 W
Network
Analyzer
1 kW
1 kW
Open
Calibrated Differential
Probe
Across
VS+ and GND
Calibrated
Measurement Differential
Probe
Point for ZIN
Across
49.9 W
Resistor
From
Network
Analyzer
49.9 W
Figure 58. VOCM Input Test Circuit
VS+
52.3 W
1 kW
24.9 W
Open
Measurement
Point for Bandwidth
PD
THS452x
0.22 mF
24.9 W
VOCM
VS-
1 kW
Open
VS+
Measure with
Differential
953 W
Probe
Across ROT
52.3 W
499 W
Open
Open
0.22 mF
PD
THS452x
0.22 mF
To Oscilloscope
50-W Input
499 W
49.9 W
VOCM
Open
1 kW
52.3 W
VS-
1 kW
Step
Input
Open
1 kW
1 kW
52.3 W
Figure 57. PSRR Test Circuit
49.9 W
Figure 59. VOCM Transient Response and Slew
Rate Test Circuit
space
24
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APPLICATION INFORMATION
The following circuits show application information for
the THS4521, THS4522, and THS4524 family. For
simplicity, power-supply decoupling capacitors are
not shown in these diagrams; see the EVM and
Layout Recommendations section for suggested
guidelines. For more details on the use and operation
of fully differential op amps, refer to the Application
Report Fully-Differential Amplifiers (SLOA054),
available for download from the TI web site at
www.ti.com.
Single-Ended
Input
VS+
VS+
THS452x
VOUT+
VS-
RF
Figure 61. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
The input common-mode voltage of a fully-differential
op amp is the voltage at the + and – input pins of the
device.
RF
Differential
Input
Differential
Output
VOUT-
RG
Differential Input to Differential Output
Amplifier
The THS4521, THS4522, and THS4524 family are
fully-differential operational amplifiers that can be
used to amplify differential input signals to differential
output signals. Figure 60 shows a basic block
diagram of the circuit (VOCM and PD inputs not
shown). The gain of the circuit is set by RF divided by
RG.
RF
RG
Differential
Output
RG
VOUT-
VIN+
THS452x
VIN-
VOUT+
RG
It is important to not violate the input common-mode
voltage range (VICR) of the op amp. Assuming the op
amp is in linear operation, the voltage across the
input pins is only a few millivolts at most. Therefore,
finding the voltage at one input pin determines the
input common-mode voltage of the op amp.
Treating the negative input as a summing node, the
voltage is given by Equation 1:
VSRF
VOUT+ ´
Figure 60. Differential Input to Differential Output
Amplifier
Single-Ended Input to Differential Output
Amplifier
RF
RG
+ VIN- ´
R G + RF
R G + RF
(1)
To determine the VICR of the op amp, the voltage at
the negative input is evaluated at the extremes of
VOUT+. As the gain of the op amp increases, the input
common-mode voltage becomes closer and closer to
the input common-mode voltage of the source.
The THS4521, THS4522, and THS4524 family can
also amplify and convert single-ended input signals to
differential output signals. Figure 61 illustrates a basic
block diagram of the circuit (VOCM and PD inputs not
shown). The gain of the circuit is again set by RF
divided by RG.
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Setting the Output Common-Mode Voltage
Single-Supply Operation
The output common-model voltage is set by the
voltage at the VOCM pin. The internal common-mode
control circuit maintains the output common-mode
voltage within 5-mV offset (typ) from the set voltage.
If left unconnected, the common-mode set point is set
to midsupply by internal circuitry, which may be
overdriven from an external source. Figure 62
represents the VOCM input. The internal VOCM circuit
has typically 23 MHz of –3 dB bandwidth, which is
required for best performance, but it is intended to be
a dc bias input pin. A 0.22-µF bypass capacitor is
recommended on this pin to reduce noise. The
external current required to overdrive the internal
resistor divider is given approximately by the formula
in Equation 2:
2VOCM - (VS+ - VS-)
IEXT =
50 kW
(2)
To facilitate testing with common lab equipment, the
THS4521EVM allows for split-supply operation; most
of the characterization data presented in this data
sheet is measured using split-supply power inputs.
The device can easily be used with a single-supply
power input without degrading performance.
Figure 63 shows a dc-coupled single-supply circuit
with single-ended inputs. This circuit can also be
applied to differential input sources.
VIN+
RG
RIT
RO
VOUT-
PD
PD Control
THS452x
0.22 mF
VS+
100 kW
To internal
VOCM circuit
VOCM
VOCM Control
0.22 mF
Optional;
installed to
balance
impedance seen
at VIN+
VOCM is the voltage applied to the VOCM pin
RO
VOUT+
VS-
where:
•
RF
VS+
RIT
RG
RF
IEXT
VOCM
Figure 63. THS4521 DC-Coupled Single-Supply
with Single-Ended Inputs
100 kW
VS-
The input common-mode voltage range of the
THS4521, THS4522, and THS4524 family is
designed to include the negative supply voltage. in
the circuit shown in Figure 63, the signal source is
referenced to ground. VOCM is set by an external
control source or, if left unconnected, the internal
circuit defaults to midsupply. Together with the input
impedance of the amplifier circuit, RIT provides input
termination, which is also referenced to ground.
Figure 62. VOCM Input Circuit
Typical Performance Variation with Supply
Voltage
The THS4521, THS4522, and THS4524 family of
devices provide excellent performance across the
specified power-supply range of 2.5 V to 5.5 V with
only minor variations. The input and output voltage
compliance ranges track with the power supply in
nearly a 1:1 correlation. Other changes can be
observed in slew rate, output current drive, open-loop
gain, bandwidth, and distortion. Table 3 shows the
typical variation to be expected in these key
performance parameters.
Note that RIT and optional matching components are
added to the alternate input to balance the
impedance at signal input.
Table 3. Typical Performance Variation versus Power-Supply Voltage
PARAMETER
VS = 5 V
VS = 3.3 V
VS = 2.5 V
–3-dB Small-signal bandwidth
145 MHz
135 MHz
125 MHz
Slew rate (2-V step)
490 V/µs
420 V/µs
210 V/µs
Second harmonic
–85 dBc
–85 dBc
–84 dBc
Third harmonic
–91 dBc
–90 dBc
–88 dBc
Open-loop gain
119 dB
116 dB
115 dB
Linear output current drive
55 mA
35 mA
24 mA
Harmonic distortion at 1 MHz, 2 VPP, RL = 1 kΩ
xxx
xxx
26
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THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
Low-Power Applications and the Effects of
Resistor Values on Bandwidth
Frequency Response Variation due to
Package Options
For low-power operation, it may be necessary to
increase the gain setting resistors values to limit
current consumption and not load the source. Using
larger value resistors lowers the bandwidth of the
THS4521, THS4522, and THS4524 family as a result
of the interactions between the resistors, the device
parasitic capacitance, and printed circuit board (PCB)
parasitic capacitance. Figure 64 shows the
small-signal frequency response with 1-kΩ, 10-kΩ,
and 100-kΩ resistors for RF, RG, and RL (impedance
is assumed to typically increase for all three resistors
in low-power applications).
Users can see variations in the small-signal (VOUT =
100 mVPP) frequency response between the available
package options for the THS4521, THS4522, and
THS4524 family as a result of parasitic elements
associated with each package and board layout
changes. Figure 65 shows the variance measured in
the lab; this variance is to be expected even when
using a good layout.
SMALL-SIGNAL FREQUENCY RESPONSE
Device and Package Option Comparison
6
THS4522,
THS4524
3
SMALL-SIGNAL FREQUENCY RESPONSE
Gain = 1, RF = RG = RL = 1 kW, 10 kW, 100 kW
Signal Gain (dB)
0
6
1 kW
3
Signal Gain (dB)
0
-3
10 kW
-6
-9
-21
-24
-9
-12
-15
-21
100 kW
-24
-15
-18
-6
-18
-12
VS+ = 5.0 V
Gain = 1 V/V
RF = 1 kW
RL = 1 kW
0.1
VS+ = 5.0 V
VO = 100 mVPP
Gain = 1 V/V
0.1
1
THS4521
SOIC
THS4521
MSOP
-3
1
10
100
1000
Frequency (MHz)
10
100
1000
Figure 65. Small-Signal Frequency Response:
Package Variations
Frequency (MHz)
Figure 64. THS4521 Frequency Response with
Various Gain Setting and Load Resistor Values
space
space
space
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
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THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
Driving Capacitive Loads
This reduction in phase margin results in frequency
response peaking; overshoot, undershoot, and/or
ringing when a step or square-wave signal is applied;
and may lead to instability or oscillation. Inserting RO
isolates the phase shift from the loop gain path and
restores the phase margin, but it also limits
bandwidth. Figure 66 shows the recommended
values of RO versus capacitive loads (CL). Figure 67
shows the frequency response with various values.
1k
Series Output Resistor (W)
The THS4521, THS4522, and THS4524 family is
designed for a nominal capacitive load of 1 pF on
each output to ground. When driving capacitive loads
greater than 1 pF, it is recommended to use small
resistors (RO) in series with the output, placed as
close to the device as possible. Without RO,
capacitance on the output interacts with the output
impedance of the amplifier and causes phase shift in
the loop gain of the amplifier that reduces the phase
margin.
RECOMMENDED RO vs CLOAD
For Flat Frequency Response
100
10
1
VS+ = 5.0 V
Gain = 1 V/V
RF = 1 kW
RL = 1 kW Differential
VOUT = 100 mVPP
10
100
1000
CLOAD (pF)
Figure 66. Recommended Series Output Resistor
versus Capacitive Load for Flat Frequency
Response, with RLOAD = 1 kΩ
FREQUENCY RESPONSE vs CLOAD
5
RO = 150 W
CL = 4.7 pF
each output
Normalized Gain (dB)
0
RO = 7.15 W
CL = 1000 pF each output
-5
RO = 37.5 W
CL = 100 pF each output
-10
-15
-20
-25
VS+ = 5.0 V, Gain = 1 V/V
RO = 124 W
RF = 1 kW differential
CL = 10 pF
RL = 1 kW
each output
VOUT = 100 mVPP
0.1
1
10
100
1000
Frequency (MHz)
Figure 67. Frequency Response for Various RO
and CL Values, with RLOAD = 1 kΩ
28
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THS4521
THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
Audio Performance
1 kW
-50
-60
-70
THD+N (dBv)
The THS4521, THS4522, and THS4524 family
provide excellent audio performance with very low
quiescent power. To show performance in the audio
band, the device was tested with a SYS-2722 audio
analyzer from Audio Precision. THD+N and FFT tests
were performed at 1-VRMS output voltage.
Performance is the same on both 3.3-V and 5-V
supplies. Figure 68 shows the test circuit used;
Figure 69 and Figure 70 show the performance of the
analyzer using internal loopback mode (generator)
together with the THS4521. Note that the harmonic
distortion performance is very close to the same with
and without the device meaning the THS4521
performance is actually much better than can be
directly measured by this meathod. Using these
measurements and simuation, we estimate the
second-order harmonic distortion to be –133 dBc and
the third-order harmonic distortion to be –140 dBc at
10 kHz. Note that the circuit of Figure 68 is also used
to measure crosstalk between channels on the
THS4522 and THS4524 using the crosstalk meter
function of the AP audio analyzer.
TOTAL HARMONIC DISTORTION + NOISE
THS4521 Measured on AP Analyzer
VIN-
Open
THS452x
0.22 mF
VOCM
VS1 kW
24.9 W
To AP
Analyzer
Open
0.22 mF
1 kW
Figure 68. THS4521 AP Analyzer Test Circuit
5
0
10
15
20
Frequency (kHz)
Figure 69. THS4521 1-VRMS 20-Hz to 20-kHz
THD+N
10-kHz OUTPUT SPECTRUM
THS4521 on AP Analyzer
VOUT-
VOUT+
Signal Generator
-120
Magnitude (dBv)
24.9 W
PD
THS4521
-110
1 kW
VIN+
-90
-100
VS+
From
AP
Analyzer
-80
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
VS+ = 5.0 V
G = 1 V/V
RF = 1 kW
VOUT = 1 VRMS
0
5k
10 k
Generator
THS4521
15 k
20 k
25 k
30 k
35 k
Frequency (Hz)
Figure 70. THS4521 1-VRMS 10-kHz FFT Plot
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
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THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
ADC Driver Performance:
THS4521 and ADS1278 Combined
Performance
1-kHz FFT
0
G=1
RF = RG = 1 kW
CF = 1.5 nF
VS = 5 V
Load = 2 x 49.9 W + 2.2 nF
-20
Magnitude (dBFS)
The THS4521 provides excellent performance when
driving high-performance delta-sigma (ΔΣ) and
successive approximation register (SAR) ADCs in
audio and industrial applications using a single 3-V to
5-V power supply. To show achievable performance,
the THS4521 is tested as the drive amplifier for the
ADS1278 24-bit ADC. The ADS1278 offers excellent
ac and dc performance, with four selectable operating
modes from 10 kSPS to 128 kSPS to enable the user
to fine-tune performance and power for specific
application needs. The circuit shown in Figure 71 was
used to test the performance. Data were taken using
the High-Resolution mode (52 kSPS) of the ADS1278
with input frequencies at 1 kHz and 10 kHz and
signal levels 1/2 dB below full-scale (–0.5 dBFS). FFT
plots showing the spectral performance are given in
Figure 72 and Figure 73; tabulated ac analysis results
are shown in Table 4.
-40
-60
-80
-100
-120
-140
-160
0
4
8
G=1
RF = RG = 1 kW
CF = 1.5 nF
VS = 5 V
Load = 2 x 49.9 W + 2.2 nF
-20
AINN1
VIN+
THS4521
VIN-
49.9 W
2.2 nF
ADS1278 (CH 1)
AINP1
1 kW
VOCM
VCOM
1/2
OPA2350
-40
-60
-80
-100
-120
x1
0.1 mF
Magnitude (dBFS)
1.5 nF
49.9 W
24 26
10-kHz FFT
0
1 kW
20
Figure 72. 1-kHz FFT
1 kW
5V
16
12
Frequency (kHz)
0.1 mF
1.5 nF
-140
-160
0
1 kW
4
8
12
16
20
24 26
Frequency (kHz)
Figure 71. THS4521 and ADS1278 (Ch 1) Test
Circuit
Figure 73. 10-kHz FFT
Table 4. AC Analysis
30
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Tone
(Hz)
Signal
(dBFS)
SNR
(dBc)
THD
(dBc)
SINAD
(dBc)
SFDR
(dBc)
1k
–0.50
109.1
–107.9
105.5
113.7
10 k
–0.50
101.8
–109.8
101.1
109.8
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
THS4521
THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
ADC Driver Performance:
THS4521 and ADS8321 Combined
Performance
10-kHz FFT
0
Magnitude (dBFS)
To demonstrate achievable performance, the
THS4521 is tested as the drive amplifier for the
ADS8321 16-bit SAR ADC. The ADS8321 offers
excellent ac and dc performance, with ultra-low power
and small size. The circuit shown in Figure 74 was
used to test the performance. Data were taken using
the ADS8321 at 100 kSPS with input frequencies of 2
kHz and 10 kHz and signal levels that were -0.5
dBFS. FFT plots that illustrate the spectral
performance are given in Figure 75 and Figure 76.
Tabulated ac analysis results are listed in Table 5.
VS = 5.0 V
G = 1 V/V
R F = R G = 1 kW
Load = 2 x 49.9 W + 2 pF
-20
-40
-60
-80
-100
-120
-140
-160
0
10 k
20 k
30 k
40 k
50 k
Frequency (Hz)
1 kW
Figure 76. 10-kHz FFT
5V
68 pF
49.9 W
1 kW
-IN
VIN+
THS4521
VIN-
1 nF
49.9 W
1 kW
VOCM
Table 5. AC Analysis
ADS8321
+IN
68 pF
Open
0.22 mF
1 kW
Tone
(Hz)
Signal
(dBFS)
SNR
(dBc)
THD
(dBc)
SINAD
(dBc)
SFDR
(dBc)
2k
–0.5
86.7
–97.8
86.4
100.7
10 k
–0.6
85.2
–98.1
85.2
102.2
Figure 74. THS4521 and ADS8321 Test Circuit
2-kHz FFT
0
VS = 5.0 V
G = 1 V/V
RF = RG = 1 kW
Load = 2 x 49.9 W + 2 pF
Magnitude (dBFS)
-20
-40
-60
-80
-100
-120
-140
-160
0
10 k
20 k
30 k
40 k
50 k
Frequency (Hz)
Figure 75. 2-kHZ FFT
Copyright © 2008–2009, Texas Instruments Incorporated
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THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
EVM AND LAYOUT RECOMMENDATIONS
Figure 77 shows the THS4521EVM schematic. PCB layers 1 through 4 are shown in Figure 78; Table 6 lists the
bill of materials for the THS4521EVM as supplied from TI. It is recommended to follow the layout of the external
components near to the amplifier, ground plane construction, and power routing as closely as possible. Follow
these general guidelines:
1. Signal routing should be direct and as short as possible into and out of the op amp circuit.
2. The feedback path should be short and direct.
3. Ground or power planes should be removed from directly under the amplifier input and output pins.
4. An output resistor is recommended in each output lead, placed as near to the output pins as possible.
5. Two 0.1-µF power-supply decoupling capacitors should be placed as near to the power-supply pins as
possible.
6. Two 10-µF power-supply decoupling capacitors should be placed within 1 inch of the device and can be
shared among multple analog devices.
7. A 0.22-µF capacitor should be placed between the VOCM input pin and ground near to the pin. This capacitor
limits noise coupled into the pin.
8. The PD pin uses TTL logic levels; a bypass capacitor is not necessary if actively driven, but can be used for
robustness in noisy environments whether driven or not.
9. If input termination resistors R10 and R11 are used, a single point connection to ground on L2 is
recommended.
J4
VS-
VS-
C3
0.1mF
C5
0.1mF
C7
10mF
C603
J5
GND
J8
VS+
C8
10mF
C9
10mF
C0805
VS+
C10
10mF
C11
0.1mF
VS+
C15
Open
C12
0.1mF
C0805
C13
Open
C14
Open
C603
TP2
C16
Open
TP3
VS-
J11
J1
JP1
C1
R6
0.22mF 49.9W
VS-
C4
0.22mF
J6
R14
1kW
R4
0W
R1
R10
52.3W
3 T1 4
R12
1kW
PW
R2
2
5
1
6
R5
0W
J2
C2
1
R7
6
4
R9
R20
52.3W
5
R13
1kW
8
VOUTVS+
CM
R21
5
2
R19
R17
487W
4
3
J9
R26
J10
R24
0W
J7
R15
1kW
R25
0W
R22
3
2
R11
52.3W
6 T2 1
R16
487W
VOUT+
7
R3
R23
R18
VS-
R8
TP1
C6
0.22mF
J3
Figure 77. THS4521EVM: Schematic
32
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THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
Figure 78. THS4521EVM: Layer 1 to Layer 4 Images
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
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THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
Table 6. THS4521EVM Parts List
REFERENCE
DESIGNATOR
QTY
0805
C7, C8, C9, C10
4
(AVX) 08056D106KAT2A
0603
C3, C5, C11, C12
4
(AVX) 0603YC104KAT2A
Capacitor, 0.22 µF, ceramic, X7R, 10 V
0603
C1, C4, C6
3
(AVX) 0603ZC224KAT2A
4
Open
0603
C2, C13, C14, C15, C16
5
5
Open
0603
R1, R2, R3, R7, R8, R9, R18,
R19, R21, R22, R23, R26
12
6
Resistor, 0 Ω
0603
R24, R25
2
(ROHM) MCR03EZPJ000
7
Resistor, 49.9 Ω, 1/10W, 1%
0603
R6
1
(ROHM) MCR03EZPFX49R9
8
Resistor, 52.3 Ω, 1/10W, 1%
0603
R10, R11, R20
3
(ROHM) MCR03EZPFX52R3
9
Resistor, 487 Ω, 1/10W, 1%
0603
R16, R17
2
(ROHM) MCR03EZPFX4870
10
Resistor, 1k Ω, 1/10W, 1%
0603
R12, R13, R14, R15
4
(ROHM) MCR03EZPFX1001
11
Resistor, 0 Ω
0805
R4, R5
2
(ROHM) MCR10EZPJ000
12
Open
T1
1
13
Transformer, RF
14
Jack, Banana receptance, 0.25-in dia.
hole
15
Open
16
Connector, edge, SMA PCB jack
17
Header, 0.1 in CTRS, 0.025-in sq. pins
18
Shunts
19
Test point, Red
20
Test point, Black
21
IC, THS4521
22
23
24
ITEM
DESCRIPTION
SMD SIZE
1
Capacitor, 10.0 µF, ceramic, X5R, 6.3 V
2
Capacitor, 0.1 µF, ceramic, X7R, 16 V
3
34
2 POS.
MANUFACTURER
PART NUMBER
T2
1
(MINI-CIRCUITS) ADT1-1WT
J4, J5, J8
3
(SPC) 813
J1, J3, J6, J7, J10, J11
6
J2, J9
2
(JOHNSON) 142-0701-801
JP1
1
(SULLINS) PBC36SAAN
JP1
1
(SULLINS) SSC02SYAN
TP1
1
(KEYSTONE) 5000
TP2, TP3
2
(KEYSTONE) 5001
U1
1
(TI) THS4521D
Standoff, 4-40 hex, 0.625 in length
4
(KEYSTONE) 1808
Screw, Phillips, 4-40, .250 in
4
SHR-0440-016-SN
Board, printed circuit
1
(TI) EDGE# 6494532
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THS4522
THS4524
www.ti.com.................................................................................................................................................... SBOS458B – DECEMBER 2008 – REVISED MAY 2009
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or
services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or
safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are
designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 3 V to 5.5 V and the output voltage range of 3 V to 5.5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +85°C. The EVM is designed to operate
properly with certain components above +85°C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
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THS4521
THS4522
THS4524
SBOS458B – DECEMBER 2008 – REVISED MAY 2009.................................................................................................................................................... www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March, 2009) to Revision B ................................................................................................. Page
•
Corrected ordering number for THS4522 large tape and reel ............................................................................................... 2
Changes from Original (December, 2008) to Revision A ............................................................................................... Page
•
•
•
•
•
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36
Changed device status of THS4524 from product preview to production data ..................................................................... 1
Changed power-supply voltage range from +3 V (1.5 V) to +2.5 V (1.25 V) ....................................................................... 1
Revised channel-to-channel crosstalk specifications (3.3 V)................................................................................................. 3
Changed specified operating voltage (3.3 V) from 3 V (minimum) to 2.5 V (minimum) ........................................................ 4
Revised channel-to-channel crosstalk specifications (5 V).................................................................................................... 5
Changed specified operating voltage (5 V) from 3 V (minimum) to 2.5 V (minimum) ........................................................... 6
Updated Figure 18 (THS4522, THS4524 Crosstalk) ........................................................................................................... 14
Updated Figure 44 (THS4522, THS4524 Crosstalk) ........................................................................................................... 19
Added Typical Performance Variation with Supply Voltage section .................................................................................... 26
Changed title of Single-Supply Operation section ............................................................................................................... 26
Added sentence regarding use of Figure 68 to measure crosstalk between channels of THS4522 and THS4524 to
Audio Performance section.................................................................................................................................................. 29
Corrected device name error in EVM schematic ................................................................................................................. 32
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Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4521 THS4522 THS4524
PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS4521ID
ACTIVE
SOIC
D
8
THS4521IDGKR
ACTIVE
MSOP
DGK
THS4521IDGKT
ACTIVE
MSOP
THS4521IDR
ACTIVE
THS4522IPW
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
TSSOP
PW
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4522IPWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4524IDBT
ACTIVE
TSSOP
DBT
38
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4524IDBTR
ACTIVE
TSSOP
DBT
38
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
90
50
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-May-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
THS4521IDGKR
MSOP
DGK
8
THS4521IDGKT
MSOP
DGK
THS4521IDR
SOIC
D
THS4522IPWR
TSSOP
THS4524IDBTR
TSSOP
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
PW
16
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
DBT
38
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-May-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS4521IDGKR
MSOP
DGK
8
2500
346.0
346.0
29.0
THS4521IDGKT
MSOP
DGK
8
250
190.5
212.7
31.8
THS4521IDR
SOIC
D
8
2500
346.0
346.0
29.0
THS4522IPWR
TSSOP
PW
16
2000
346.0
346.0
29.0
THS4524IDBTR
TSSOP
DBT
38
2000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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