SN54AHC16245, SN74AHC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS328C – MARCH 1996 – REVISED JULY 1998 D D D D D SN54AHC16245 . . . WD PACKAGE SN74AHC16245 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family Operating Range 2-V to 5.5-V VCC EPIC (Enhanced-Performance Implanted CMOS) Process Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR description The ’AHC16245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for synchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54AHC16245 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AHC16245 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PRODUCT PREVIEW D SN54AHC16245, SN74AHC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS328C – MARCH 1996 – REVISED JULY 1998 logic symbol† 48 1OE 1DIR G3 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR G6 24 6 EN4 [BA] 6 EN5 [AB] 1A1 47 2 1 1B1 2 1A2 1A3 1A4 1A5 PRODUCT PREVIEW 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 5 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 36 13 1B1 To Seven Other Channels 2 POST OFFICE BOX 655303 2OE To Seven Other Channels • DALLAS, TEXAS 75265 2B1 SN54AHC16245, SN74AHC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS328C – MARCH 1996 – REVISED JULY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. SN54AHC16245 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 3 V VCC = 5.5 V VCC = 2 V VIL VI VO IOH Low-level input voltage Output voltage VCC = 2 V VCC = 3.3 ± 0.3 V ∆t/∆v Low-level output current Input transition rise or fall rate 2 5.5 1.5 SN74AHC16245 MIN MAX 2 5.5 UNIT V 1.5 2.1 2.1 3.85 3.85 0.5 V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC –50 0 VCC –50 mA –4 –4 –8 –8 50 50 VCC = 3.3 ± 0.3 V VCC = 5 ± 0.5 V 4 4 8 8 VCC = 3.3 ± 0.3 V VCC = 5 ± 0.5 V 100 100 20 20 VCC = 5 ± 0.5 V VCC = 2 V IOL MAX VCC = 3 V VCC = 5.5 V Input voltage High-level output current MIN PRODUCT PREVIEW recommended operating conditions (see Note 3) V mA mA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHC16245, SN74AHC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS328C – MARCH 1996 – REVISED JULY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TA = 25°C TYP MAX 2V 1.9 2 1.9 1.9 VCC IOH = –50 mA VOH IOH = –4 mA IOH = –8 mA IOL = 50 mA VOL IOL = 4 mA IOL = 8 mA PRODUCT PREVIEW MIN MAX SN74AHC16245 MIN 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 3V 2.58 2.48 2.48 4.5 V 3.94 3.8 MAX UNIT V 3.8 2V 0.1 0.1 0.1 0.1 3V 0.1 0.1 4.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 ±0.1 ±1 ±1 ±0.1 ±1 ±1 A or B inputs II SN54AHC16245 V mA VI = VCC or GND 55V 5.5 IOZ† VO = VCC or GND, VI (OE) = VIL or VIH 5.5 V ±0.25 ±2.5 ±2.5 mA ICC Ci 5.5 V 4 40 40 mA OE or DIR VI = VCC or GND, VI = VCC or GND 10 pF Cio A or B inputs OE or DIR IO = 0 VI = VCC or GND † The parameter IOZ includes the input leakage current. 5V 2.5 5V 4 10 pF switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH* tPHL* A or B B or A CL = 15 pF tPZH* tPZL* OE A or B CL = 15 pF tPHZ* tPLZ* OE A or B CL = 15 pF tPLH tPHL A or B B or A CL = 50 pF tPZH tPZL OE A or B CL = 50 pF tPHZ tPLZ OE A or B CL = 50 pF tsk(o)‡ TA = 25°C MIN TYP MAX MIN MAX MIN MAX 8.4 1 10 1 10 5.8 8.4 1 10 1 10 8.5 13.2 1 15.5 1 15.5 8.5 13.2 1 15.5 1 15.5 8.9 12.5 1 15.5 1 15.5 8.9 12.5 1 15.5 1 15.5 8.3 11.9 1 13.5 1 13.5 8.3 11.9 1 13.5 1 13.5 11 16.7 1 19 1 19 11 16.7 1 19 1 19 11.5 15.8 1 18 1 18 11.5 15.8 1 18 1 18 1.5** CL = 50 pF POST OFFICE BOX 655303 SN74AHC16245 5.8 * On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply. ‡ Skew between any two outputs of the same package switching in the same direction 4 SN54AHC16245 • DALLAS, TEXAS 75265 1.5 UNIT ns ns ns ns ns ns ns SN54AHC16245, SN74AHC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS328C – MARCH 1996 – REVISED JULY 1998 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH* tPHL* A or B B or A CL = 15 pF tPZH* tPZL* OE A or B CL = 15 pF tPHZ* tPLZ* OE A or B CL = 15 pF tPLH tPHL A or B B or A CL = 50 pF tPZH tPZL OE A or B CL = 50 pF tPHZ tPLZ OE A or B CL = 50 pF tsk(o)† MIN TA = 25°C TYP MAX SN54AHC16245 SN74AHC16245 MIN MAX MIN MAX 4 5.5 1 6.5 1 6.5 4 5.5 1 6.5 1 6.5 5.8 8.5 1 10 1 10 5.8 8.5 1 10 1 10 5.6 7.8 1 9.2 1 9.2 5.6 7.8 1 9.2 1 9.2 5.5 7.5 1 8.5 1 8.5 5.5 7.5 1 8.5 1 8.5 7.3 10.6 1 12 1 12 7.3 10.6 1 12 1 12 7 9.7 1 11 1 11 7 9.7 1 11 1 11 1** CL = 50 pF 1 UNIT ns ns ns ns ns ns ns PRODUCT PREVIEW PARAMETER * On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply. † Skew between any two outputs of the same package switching in the same direction noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHC16245 PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.9 V Quiet output, minimum dynamic VOL –0.9 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.3 V High-level dynamic input voltage 3.5 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V 1.5 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 14 pF 5 SN54AHC16245, SN74AHC16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS328C – MARCH 1996 – REVISED JULY 1998 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC PRODUCT PREVIEW 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL VCC Output Control 50% VCC 0V tPZL Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC VOH 50% VCC VOL 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS tPLZ 50% VCC tPZH ≈ VCC VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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