ETC ATJ2073

ATJ2073
Data Sheet
Contents
1
2
3
4
Short Descriptions .....................................................................................................................4
Features......................................................................................................................................4
Architecture Overview ..............................................................................................................5
Pin Descriptions.........................................................................................................................6
4.1 Pinout........................................................................................................................................................... 6
4.2 Pin sort by number....................................................................................................................................... 7
4.3 Pin sort by Function................................................................................................................................... 13
5
Functional Description ............................................................................................................22
5.1 DSP Core ................................................................................................................................................... 22
5.2 MCU Core ................................................................................................................................................. 22
5.3 System Memory Mapping ......................................................................................................................... 22
5.4 USB1.1 Interface ....................................................................................................................................... 23
5.5 MPEG Decoder.......................................................................................................................................... 23
5.6 Microphone Interface................................................................................................................................. 24
5.7 SPDIF Interface ......................................................................................................................................... 25
5.8 Power Management Unit (PMU)............................................................................................................... 26
6
Control Interfaces ....................................................................................................................27
6.1 How System Power Up.............................................................................................................................. 27
6.2 Key Matrix Scan ........................................................................................................................................ 28
6.3 4*13 LCD Driver....................................................................................................................................... 29
6.4 8080/6800 LCM Interface ......................................................................................................................... 30
7
8
Pin Configurations...................................................................................................................32
Electrical Characteristics .........................................................................................................34
8.1 Absolute Maximum Ratings ...................................................................................................................... 34
8.2 Capacitance (TA = 25 , VCC = 0 V) ...................................................................................................... 34
8.3 DC Characteristics (TA = 25 , VDD = 2.35 V, VCC = 3.15 V) ............................................................. 34
8.4 AC Characteristics (TA = 25 , VDD = 2 to 2.7 V, VCC = 2.7 to 3.6 V)................................................ 35
9
Typical Performance Characteristics .......................................................................................41
9.1 A/D Converter Characteristics................................................................................................................... 41
9.2 D/A Converter ........................................................................................................................................... 41
9.3 Internal Power Amplifier (2 channels) ...................................................................................................... 42
9.4 MCU/DSP Dissipation (Ivdd VS. Frequency)........................................................................................... 43
10
Outline Dimension...................................................................................................................44
Page 3 of 45
Actions Semiconductor Co.,LTD
ATJ2073
1
Data Sheet
Short Descriptions
The ATJ2073 is a single-chip highly-integrated digital music system solution for devices such as dedicated
audio players, PDAs, and cell phones. It includes an audio decoder with a high performance DSP with
embedded RAM, ADPCM/AG record capabilities and USB interface for downloading music and uploading
voice recordings. ATJ2073 also provides an interface to S/PDIF audio data input, flash memory, LED/LCD,
button and switch inputs, headphone, and microphone, and FM radio control. The ATJ2073’s programmable
architecture supports the MP3 and other digital audio standards. For devices like USB Flash Disk, the ATJ2073
can act as a USB mass storage slave device to personal computer system. The ATJ2073 has low power
consumption to allow long battery life and an efficient flexible on-chip DC-DC converter that allows many
different battery configurations, including 1xAA, 1xAAA, 2xAA,2xAAA.
2
Features
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24-bit DSP Core with on-chip ICE support
On-chip DSP 16Kx24 PM and (16K-256)x24 DM, can be switched to be MCU memory space
Integrated 8bit MCU with on-chip ICE support which the instructions are compatible with the Z80 CPU
Internal 16k bytes SRAM accessed by MCU
External up to 25-bit code address space with 7 chips select
Support 14.318MHz/16.368MHz/17.734475MHz/24.576MHz OSC with on-chip PLL for DSP
Supported up to 3*4Gbyte Nand type Flash
2-channel DMA for MCU
1-channel CTC(Counter/Timer Controller) for MCU
On-chip interrupt controller for MCU
Built-in power management unit(PMU), supporting 1 or 2 batteries operation
Support RTC with 32.768kHz or 76.8kHz OSC
Built-in USB1.1 interface
Support SPDIF IN/UART/IR interface
Support on-chip Stereo 18 bit Sigma-Delta DAC
Support external 6800 or 8086 series interface LCM
Support 4x13 matrix Keyboard Circuit Auto Scan
Support 20 General Purpose Input/Output
Support external Epson Series LCM Frame Buffer up to 320x240 dots
Support on-chip 1/3 biased 1/4 duty LCD driver(4x13dots, multiplexed )
Support external CMOS image sensor interface
On-chip 16-bit ADC for Microphone input support , sample rate at 8K/11K/12K/16K/22K/24KHz
On-chip 2 channel headphone power amplifiers
128-pin 14x14x1.4mm LQFP package
Page 4 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Architecture Overview
Nor/Nand Flash
Smart Media Cand
Compact Flash Card
Multi Media Card
IDE Driver
GPIO
FM
Module
Mouse/
Keyboard
USB
1.1
ICE
8Bit
MCU
PlatForm
24bit DSP
SPDIF
Bus/DMA/IRQ
Controller
gain
DAC
UART/ IR
zRAM
16K*8
Page 5 of 45
Microphone
Headphone Amplifeer
SPDIF
ICE Port
ADC
General Purpose Input /Output
LED/ILCD
KeyScan/
Switchs
Ext.Mem
I/F
USB Bus
MIC IN
3
Data Sheet
IPM
16K*24
IDM
16K*24
PMU
PLL1/2
XTAL
Battery
1AAor2AA
24.576MHZ
Earphone
RTC
32.768KHZ
Actions Semiconductor Co.,LTD
ATJ2073
4
Data Sheet
Pin Descriptions
4.1 Pinout
Page 6 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
4.2 Pin sort by number
Pin No.
Pin Name
I/O
Type
VCC
PWR
GIOF3
BI
Z
Bit3 of general purpose I/O port F
KEYO3
O
Z
Bit3 of key scan circuit output
SEG15
O
Z
SEG15 of int. 4comX28seg LCD driver
GIOF1
BI
Z
Bit1 of general purpose I/O port F
KEYO1
O
Z
Bit1 of key scan circuit output
SEG13
O
Z
SEG13 of int. 4comX28seg LCD driver
GIOF0
BI
Z
Bit0 of general purpose I/O port F
KEYO0
O
Z
Bit0 of key scan circuit output
SEG12
O
Z
SEG12 of int. 4comX28seg LCD driver
GIOE7
BI
Z
Bit7 of general purpose I/O port E
KEYI11
I
Z
Bit11 of key scan circuit input
SEG11
O
Z
SEG11 of int. 4comX28seg LCD driver
GIOE6
BI
Z
Bit6 of general purpose I/O port E
KEYI10
I
Z
Bit10 of key scan circuit input
SEG10
O
Z
SEG10 of int. 4comX28seg LCD driver
GIOE5
BI
Z
Bit5 of general purpose I/O port E
KEYI9
I
Z
Bit9 of key scan circuit input
SEG9
O
Z
SEG9 of int. 4comX28seg LCD driver
GIOE4
BI
Z
Bit4 of general purpose I/O port E
KEYI8
I
Z
Bit8 of key scan circuit input
SEG8
O
Z
SEG8 of int. 4comX28seg LCD driver
GIOE3
BI
Z
Bit3 of general purpose I/O port E
KEYI7
I
Z
Bit7 of key scan circuit input
SEG7
O
Z
SEG7 of int. 4comX28seg LCD driver
10
10(1)
10(2)
GIOD7
BI
Z
Bit7 of general purpose I/O port D
TCPD7
O
Z
Bit7 of Epson Series LCM data bus
KEYI3
I
Z
Bit3 of key scan circuit input
10(3)
SEG3
O
Z
SEG3 of int. 4comX28seg LCD driver
11
11(1)
GIOD6
BI
Z
Bit6 of general purpose I/O port D
TCPD6
O
Z
Bit6 of Epson Series LCM data bus
1
2
2(1)
2(3)
3
3(1)
3(3)
4
4(1)
4(3)
5
5(1)
5(3)
6
6(1)
6(3)
7
7(1)
7(3)
8
8(1)
8(3)
9
9(1)
9(3)
Page 7 of 45
Reset
Default
Short Description
Power supply for Pads circuits
Actions Semiconductor Co.,LTD
ATJ2073
11
(2)
Data Sheet
KEYI2
I
Z
Bit2 of key scan circuit input
SEG2
O
Z
SEG2 of int. 4comX28seg LCD driver
12
12(1)
12(2)
GIOD5
BI
Z
Bit5 of general purpose I/O port D
TCPD5
O
Z
Bit5 of Epson Series LCM data bus
KEYI1
I
Z
Bit1 of key scan circuit input
12(3)
SEG1
O
Z
SEG1 of int. 4comX28seg LCD driver
13
GND
PWR
/
Digital signal ground
GIOD4
BI
Z
Bit4 of general purpose I/O port D
TCPD4
O
Z
Bit4 of Epson Series LCM data bus
KEYI0
I
Z
Bit0 of key scan circuit input
SEG0
O
Z
SEG0 of int. 4comX28seg LCD driver
VDD
PWR
16
16(1)
16(3)
GIOD3
BI
Z
Bit3 of general purpose I/O port D
TCPD3
O
Z
Bit3 of Epson Series LCM data bus
COM3
O
Z
COM3 of int. 4comX28seg LCD driver
17
17(1)
17(3)
GIOD2
BI
Z
Bit2 of general purpose I/O port D
TCPD2
O
Z
Bit2 of Epson Series LCM data bus
COM2
O
Z
COM2 of int. 4comX28seg LCD driver
18
18(1)
18(3)
GIOD1
BI
Z
Bit1 of general purpose I/O port D
TCPD1
O
Z
Bit1 of Epson Series LCM data bus
COM1
O
Z
COM1 of int. 4comX28seg LCD driver
19
19(1)
19(3)
GIOD0
BI
Z
Bit0 of general purpose I/O port D
TCPD0
O
Z
Bit0 of Epson Series LCM data bus
COM0
O
Z
COM0 of int. 4comX28seg LCD driver
20
20(1)
MWR-
BI
H
Ext. memory write active signal
WE-
O
H
Nand type flash write enable
21
21(1)
MRD-
BI
H
Ext. memory read active signal
RE
O
H
Nand type flash read enable
22
A0
BI
L
Bit0 of ext. memory address bus
23
A1
BI
L
Bit1 of ext. memory address bus
24
A2
BI
L
Bit2 of ext. memory address bus
25
A3
BI
L
Bit3 of ext. memory address bus
26
A4
BI
L
Bit4 of ext. memory address bus
27
A5
BI
L
Bit5 of ext. memory address bus
11(3)
14
14(1)
14(2)
14(3)
15
Page 8 of 45
Power supply for core
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
28
A6
BI
L
Bit6 of ext. memory address bus
29
A7
BI
L
Bit7 of ext. memory address bus
30
A8
BI
L
Bit8 of ext. memory address bus
31
NMI-
SIU
H
Ext. non-maskable interrupt input
32
GND
PWR
/
Digital signal ground
33
GND
PWR
/
Digital signal ground
34
VCC
PWR
35
A9
BI
L
Bit9 of ext. memory address bus
36
A10
BI
L
Bit10 of ext. memory address bus
37
A11
BI
L
Bit11 of ext. memory address bus
38
A12
BI
L
Bit12 of ext. memory address bus
39
A13
BI
L
Bit13 of ext. memory address bus
40
ZICEDO
O
L
Debug pin, data output from DSU
41
ZICEDI
SIU
H
Debug pin, data input to DSU
42
ZICECK
SIU
H
Debug pin, clock into DSU
43
CE2-
O
H
Ext. memory chip select 2
44
TEST
SI
L
Test mode control, 0:normal mode 1:test
mode
45
ZICERST-
SIU
H
Debug pin, to reset DSU
46
CE3-
O
H
Ext. memory chip select 3
47
ZICEEN-
SIU
H
Debug pin, to enable DSU
48
CE4-
O
H
Ext. memory chip select 4
49
RESET-
SI
H
System reset input
50
A14
O
L
Bit14 of ext. memory address bus
51
CE5-
O
H
Ext. memory chip select 5
52
D0
BI
Z
Bit0 of ext. memory data bus
53
D1
BI
Z
Bit1 of ext. memory data bus
54
D2
BI
Z
Bit2 of ext. memory data bus
55
D3
BI
Z
Bit3 of ext. memory data bus
56
D4
BI
Z
Bit4 of ext. memory data bus
57
D5
BI
Z
Bit5 of ext. memory data bus
58
D6
BI
Z
Bit6 of ext. memory data bus
59
D7
BI
Z
Bit7 of ext. memory data bus
60
CE0-
O
H
Ext. memory chip select 0
61
CE1-
O
H
Ext. memory chip select 1
Page 9 of 45
Power supply for Pads circuits
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
62
CE6-
O
63
VDD
PWR
64
LOSCI
AI
/
Low frequency crystal OSC input
65
LOSCO
AO
/
Low frequency crystal OSC output
66
GND
PWR
/
Digital signal ground
67
67(1)
A15
O
L
Bit15 of ext. memory address bus
CLE
O
L
Command latch enable of Nand type flash
68
68(1)
A16
O
L
Bit16 of ext. memory address bus
ALE
O
L
Address latch enable of Nand type flash
69
A17
O
L
Bit17 of ext. memory address bus
70
A18
O
L
Bit18 of ext. memory address bus
71
A19
O
L
Bit19 of ext. memory address bus/GPO
72
A20
O
L
Bit20 of ext. memory address bus/GPO
73
A21
O
L
Bit21 of ext. memory address bus/GPO
74
A22
O
L
Bit22 of ext. memory address bus/GPO
75
A23
O
L
Bit23 of ext. memory address bus/GPO
76
A24
O
L
Bit24 of ext. memory address bus/GPO
77
VCC
PWR
78
USBD-
A
/
USB negative connect
79
USBD+
A
/
USB positive connect
80
USBVBUS
I
L
USB cable power signal
81
PVDD
A
/
Bypass capacitor for power amplifier
82
PAOR
A
/
Output of right channel power amplifier
83
PAOL
A
/
Output of
84
PGND
PWR
/
Ground for power amplifier circuits
85
PAIR
A
/
Input of right channel power amplifier
86
PAIL
A
/
Input of left channel power amplifier
87
AOUTR
A
/
Int. sigma-dalta DAC right channel analog
output
88
AOUTL
A
/
Int. sigma-dalta DAC left channel analog
output
89
VRDA
A
/
Reference voltage for ADC
90
NC
/
/
91
VRAD
A
/
Reference voltage for ADC
92
AGCI
A
/
Microphone ADC amplifier input
Page 10 of 45
H
Ext. memory chip select 6
Power supply for core
Power supply for Pads circuits
left channel power amplifier
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
93
MICOUT
A
/
Microphone pre-amplifier output
94
MICIN
A
/
Microphone pre-amplifier input
95
VMIC
A
/
Power supply for microphone bias circuits
96
AGND
PWR
/
Analog ground for record, and ADC blocks
97
AVCC
PWR
Power supply for record, and ADC blocks
98
BATSEL
I
Battery select, 0:one battery 1:two batteries
99
IBIAS
I
Int. bias pin with a ext.R(1.5Mohm) to
ground
100
VREFI
A
Reference voltage input (1.5v)
101
VL0
AI
Battery monitor reference voltage input ( for
example 1.40v)
102
VL1
AI
Battery monitor reference voltage input (for
example 1.30v)
103
VL2
AI
Battery monitor reference voltage input (for
example 1.15v)
104
VL3
AI
Battery monitor reference voltage input (for
example 1.05v)
105
DCDIS
I
106
VBAT
I
107
DCF2
AI
/
VCC DC-DC feedback pin
108
DCF1
AI
/
VDD DC-DC feedback pin
109
VP1
PWR
Power supply for int. regulator
110
VDD
PWR
Power supply for core
111
VP2
AI
/
Input for int. power switch
112
DCOP2
AO
/
VCC DC-DC pulse output
113
DCOP1
AO
/
VDD DC-DC pulse output
114
AVDD
PWR
115
AVSS
PWR
/
Ground for PLL analog circuits
116
HOSCI
AI
/
High frequency crystal OSC input
117
HOSCO
AO
/
High frequency crystal OSC output
118
GND
PWR
/
Digital signal ground
119
XSCLK
O
H
Epson Series LCM XSCLK output
120
DISPOFF
O
Z
Epson Series LCM display off control output
121
121(1)
121(3)
FRAME
O
Z
Epson Series LCM frame signal output
LCM_CE
O
Z
6800 Series LCM CE
V2
O
Z
Int. 4comX28seg LCD driver V2
Page 11 of 45
L
Int DC-DC converter disable,
0:enable 1:disable
Battery signal input
(1.0-1.5v)
Power supply for PLL analog circuits
Actions Semiconductor Co.,LTD
ATJ2073
122
Data Sheet
VCC
PWR
123
123(1)
YSCLK_LP
O
L
Epson Series LCM YSCLK/LP signal output
LCM_RW-
O
L
6800 Series LCM RW-
124
124(1)
124(2)
GIOC2
BI
Z
Bit2 of general purpose I/O port C
SIN2
I
Z
UART2 serial input
IRRX
I
Z
IR receive input
125
125(1)
125(3)
YDU
O
Z
Epson Series LCM YDU signal output
LCM_CS-
O
Z
6800 Series LCM CS-
V1
O
Z
Int. 4comX28seg LCD driver V1
126
126(1)
126(2)
GIOC3
BI
Z
Bit3 of general purpose I/O port C
SOUT2
O
Z
UART2 serial output
IRTX
O
Z
IR transmit output
127
127(1)
GIOC4
BI
Z
Bit4 of general purpose I/O port C
SPDIFRX
BI
Z
SPDIF receive input
128
128(1)
128(3)
GIOF4
BI
Z
Bit4 of general purpose I/O port F
KEYO4
O
Z
Bit4 of key scan circuit output
SEG16
O
Z
SEG16 of int. 4comX28seg LCD driver
Page 12 of 45
Power supply for Pads circuits
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
4.3 Pin sort by Function
Type
Pin
No.
Pin Name
I/O
Type
Reset
Default
1
VCC
PWR
Power supply for Pads circuits
34
VCC
PWR
Power supply for Pads circuits
77
VCC
PWR
Power supply for Pads circuits
122
VCC
PWR
Power supply for Pads circuits
97
AVCC
PWR
Power supply for record, and ADC
blocks
15
VDD
PWR
Power supply for core
63
VDD
PWR
Power supply for core
110
VDD
PWR
Power supply for core
114
AVDD
PWR
Power supply
circuits
13
GND
PWR
/
Digital signal ground
32
GND
PWR
/
Digital signal ground
33
GND
PWR
/
Digital signal ground
66
GND
PWR
/
Digital signal ground
118
GND
PWR
/
Digital signal ground
84
PGND
PWR
/
Ground for power amplifier circuits
96
AGND
PWR
/
Analog ground for record, t and
ADC blocks
115
AVSS
PWR
/
Ground for PLL analog circuits
109
VP1
PWR
Power supply for int. regulator
98
BATSEL
I
Battery select, 0:one battery 1:two
batteries
99
IBIAS
I
Int. bias pin with a ext.R(1.5Mohm)
to ground
100
VREFI
A
Reference voltage input (1.5v)
101
VL0
AI
Battery monitor reference voltage
input (for example 1.40v)
102
VL1
AI
Battery monitor reference voltage
input (for example 1.30v)
103
VL2
AI
Battery monitor reference voltage
input (for example 1.15v)
104
VL3
AI
Battery monitor reference voltage
input (for example 1.05v)
Power
DC-DC
Page 13 of 45
Short Description
for
PLL
analog
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
105
DCDIS
I
106
VBAT
I
107
DCF2
AI
/
VCC DC-DC feedback pin
108
DCF1
AI
/
VDD DC-DC feedback pin
111
VP2
AI
/
Input for int. power switch
112
DCOP2
AO
/
VCC DC-DC pulse output
113
DCOP1
AO
/
VDD DC-DC pulse output
45
ZICERST-
SIU
H
Debug pin, to reset DSU
47
ZICEEN-
SIU
H
Debug pin, to enable DSU
41
ZICEDI
SIU
H
Debug pin, data input to DSU
42
ZICECK
SIU
H
Debug pin, clock into DSU
40
ZICEDO
O
L
Debug pin, data output from DSU
INT
31
NMI-
SIU
H
Ext. non-maskable interrupt input
TEST
44
TEST
SI
L
Test mode control, 0:normal mode
1:test mode
Reset-
49
RESET-
SI
H
System reset input
60
CE0-
O
H
Ext. memory chip select 0
61
CE1-
O
H
Ext. memory chip select 1
43
CE2-
O
H
Ext. memory chip select 2
46
CE3-
O
H
Ext. memory chip select 3
48
CE4-
O
H
Ext. memory chip select 4
51
CE5-
O
H
Ext. memory chip select 5
62
CE6-
O
H
Ext. memory chip select 6
4
GIOF0
BI
Z
Bit0 of general purpose I/O port F
KEYO0
O
Z
Bit0 of key scan circuit output
SEG12
O
Z
SEG12 of LCD4*28
GIOF1
BI
Z
Bit1 of general purpose I/O port F
KEYO1
O
Z
Bit1 of key scan circuit output
SEG13
O
Z
SEG13 of LCD4*28
GIOF3
BI
Z
Bit3 of general purpose I/O port F
KEYO3
O
Z
Bit3 of key scan circuit output
SEG14
O
Z
SEG14 of LCD4*28
GIOF4
BI
Z
Bit4 of general purpose I/O port F
KEYO4
O
Z
Bit4 of key scan circuit output
SEG15
O
Z
SEG15 of LCD4*28
ICE
Interface
Chip
Select
Interface
3
2
KeyBoard
Interface
128
Page 14 of 45
L
Int DC-DC converter disable,
0:enable 1:disable
Battery signal input
(1.0-1.5v)
Actions Semiconductor Co.,LTD
ATJ2073
9
8
7
6
5
19
18
17
16
Display
Epson
Series LCM
Interface
14
12
Page 15 of 45
Data Sheet
GIOE3
BI
Z
Bit3 of general purpose I/O port E
KEYI7
I
Z
Bit7 of key scan circuit input
SEG7
O
Z
SEG7 of LCD4*28
GIOE4
BI
Z
Bit4 of general purpose I/O port E
KEYI8
I
Z
Bit8 of key scan circuit input
SEG8
O
Z
SEG8 of LCD4*28
GIOE5
BI
Z
Bit5 of general purpose I/O port E
KEYI9
I
Z
Bit9 of key scan circuit input
SEG9
O
Z
SEG9 of LCD4*28
GIOE6
BI
Z
Bit6 of general purpose I/O port E
KEYI10
I
Z
Bit10 of key scan circuit input
SEG10
O
Z
SEG10 of LCD4*28
GIOE7
BI
Z
Bit7 of general purpose I/O port E
KEYI11
I
Z
Bit11 of key scan circuit input
SEG11
O
Z
SEG11 of LCD4*28
GIOD0
BI
Z
Bit0 of general purpose I/O port D
TCPD0
O
Z
Bit0 of Epson Series LCM data bus
COM0
O
Z
COM0 of LCD4*28
GIOD1
BI
Z
Bit1 of general purpose I/O port D
TCPD1
O
Z
Bit1 of Epson Series LCM data bus
COM1
O
Z
COM1 of LCD4*28
GIOD2
BI
Z
Bit2 of general purpose I/O port D
TCPD2
O
Z
Bit2 of Epson Series LCM data bus
COM2
O
Z
COM2 of LCD4*28
GIOD3
BI
Z
Bit3 of general purpose I/O port D
TCPD3
O
Z
Bit3 of Epson Series LCM data bus
COM3
O
Z
COM3 of LCD4*28
GIOD4
BI
Z
Bit4 of general purpose I/O port D
TCPD4
O
Z
Bit4 of Epson Series LCM data bus
KEYI0
I
Z
Bit0 of key scan circuit input
SEG0
O
Z
SEG0 of LCD4*28
GIOD5
BI
Z
Bit5 of general purpose I/O port D
TCPD5
O
Z
Bit5 of Epson Series LCM data bus
KEYI1
I
Z
Bit1 of key scan circuit input
SEG1
O
Z
SEG1 of LCD4*28
Actions Semiconductor Co.,LTD
ATJ2073
11
GIOD6
BI
Z
Bit6 of general purpose I/O port D
TCPD6
O
Z
Bit6 of Epson Series LCM data bus
KEYI2
I
Z
Bit2 of key scan circuit input
SEG2
O
Z
SEG2 of LCD4*28
GIOD7
BI
Z
Bit7 of general purpose I/O port D
TCPD7
O
Z
Bit7 of Epson Series LCM data bus
KEYI3
I
Z
Bit3 of key scan circuit input
SEG3
O
Z
SEG3 of LCD4*28
119
XSCLK
O
H
Epson Series LCM XSCLK output
120
DISPOFF
O
Z
Epson Series LCM display off
control output
121
FRAME
O
Z
Epson Series LCM frame signal
output
LCM_CE
O
Z
6800 Series LCM CE
YSCLK_LP
O
L
Epson Series
signal output
LCM_RW-
O
L
6800 Series LCM RW-
YDU
O
Z
Epson Series LCM YDU signal
output
LCM_CS-
O
Z
6800 Series LCM CS-
FRAME
O
Z
Epson Series LCM frame signal
output
LCM_CE
O
Z
6800 Series LCM CE
YSCLK_LP
O
L
Epson Series
signal output
LCM_RW-
O
L
6800 Series LCM RW-
YDU
O
Z
Epson Series LCM YDU signal
output
LCM_CS-
O
Z
6800 Series LCM CS-
52
D0
BI
Z
Bit0 of ext. memory data bus
53
D1
BI
Z
Bit1 of ext. memory data bus
54
D2
BI
Z
Bit2 of ext. memory data bus
55
D3
BI
Z
Bit3 of ext. memory data bus
56
D4
BI
Z
Bit4 of ext. memory data bus
57
D5
BI
Z
Bit5 of ext. memory data bus
58
D6
BI
Z
Bit6 of ext. memory data bus
59
D7
BI
Z
Bit7 of ext. memory data bus
19
GIOD0
BI
Z
Bit0 of general purpose I/O port D
10
123
125
121
123
125
6800 Series
LCM
Interface
Page 16 of 45
Data Sheet
LCM
LCM
YSCLK/LP
YSCLK/LP
Actions Semiconductor Co.,LTD
ATJ2073
18
17
Display
LCD4*28
Interface
16
14
12
11
10
9
8
7
Page 17 of 45
Data Sheet
TCPD0
O
Z
Bit0 of Epson Series LCM data bus
COM0
O
Z
COM0 of LCD4*28
GIOD1
BI
Z
Bit1 of general purpose I/O port D
TCPD1
O
Z
Bit1 of Epson Series LCM data bus
COM1
O
Z
COM1 of LCD4*28
GIOD2
BI
Z
Bit2 of general purpose I/O port D
TCPD2
O
Z
Bit2 of Epson Series LCM data bus
COM2
O
Z
COM2 of LCD4*28
GIOD3
BI
Z
Bit3 of general purpose I/O port D
TCPD3
O
Z
Bit3 of Epson Series LCM data bus
COM3
O
Z
COM3 of LCD4*28
GIOD4
BI
Z
Bit4 of general purpose I/O port D
TCPD4
O
Z
Bit4 of Epson Series LCM data bus
KEYI0
I
Z
Bit0 of key scan circuit input
SEG0
O
Z
SEG0 of LCD4*28
GIOD5
BI
Z
Bit5 of general purpose I/O port D
TCPD5
O
Z
Bit5 of Epson Series LCM data bus
KEYI1
I
Z
Bit1 of key scan circuit input
SEG1
O
Z
SEG1 of LCD4*28
GIOD6
BI
Z
Bit6 of general purpose I/O port D
TCPD6
O
Z
Bit6 of Epson Series LCM data bus
KEYI2
I
Z
Bit2 of key scan circuit input
SEG2
O
Z
SEG2 of LCD4*28
GIOD7
BI
Z
Bit7 of general purpose I/O port D
TCPD7
O
Z
Bit7 of Epson Series LCM data bus
KEYI3
I
Z
Bit3 of key scan circuit input
SEG3
O
Z
SEG3 of LCD4*28
GIOE3
BI
Z
Bit3 of general purpose I/O port E
KEYI7
I
Z
Bit7 of key scan circuit input
SEG7
O
Z
SEG7 of LCD4*28
GIOE4
BI
Z
Bit4 of general purpose I/O port E
KEYI8
I
Z
Bit8 of key scan circuit input
SEG8
O
Z
SEG8 of LCD4*28
GIOE5
BI
Z
Bit5 of general purpose I/O port E
KEYI9
I
Z
Bit9 of key scan circuit input
Actions Semiconductor Co.,LTD
ATJ2073
SEG9
O
Z
SEG9 of LCD4*28
GIOE6
BI
Z
Bit6 of general purpose I/O port E
KEYI10
I
Z
Bit10 of key scan circuit input
SEG10
O
Z
SEG10 of LCD4*28
GIOE7
BI
Z
Bit7 of general purpose I/O port E
KEYI11
I
Z
Bit11 of key scan circuit input
SEG11
O
Z
SEG11 of LCD4*28
GIOF0
BI
Z
Bit0 of general purpose I/O port F
KEYO0
O
Z
Bit0 of key scan circuit output
SEG12
O
Z
SEG12 of LCD4*28
GIOF1
BI
Z
Bit1 of general purpose I/O port F
KEYO1
O
Z
Bit1 of key scan circuit output
SEG13
O
Z
SEG13 of LCD4*28
GIOF3
BI
Z
Bit3 of general purpose I/O port F
KEYO3
O
Z
Bit3 of key scan circuit output
SEG14
O
Z
SEG14 of LCD4*28
GIOF4
BI
Z
Bit4 of general purpose I/O port F
KEYO4
O
Z
Bit4 of key scan circuit output
SEG15
O
Z
SEG15 of LCD4*28
A15
O
L
Bit15 of ext. memory address bus
CLE
O
L
Command latch enable of Nand type
flash
A16
O
L
Bit16 of ext. memory address bus
ALE
O
L
Address latch enable of Nand type
flash
52
D0
BI
Z
Bit0 of ext. memory data bus
53
D1
BI
Z
Bit1 of ext. memory data bus
54
D2
BI
Z
Bit2 of ext. memory data bus
55
D3
BI
Z
Bit3 of ext. memory data bus
56
D4
BI
Z
Bit4 of ext. memory data bus
57
D5
BI
Z
Bit5 of ext. memory data bus
58
D6
BI
Z
Bit6 of ext. memory data bus
59
D7
BI
Z
Bit7 of ext. memory data bus
20
MWR-
BI
H
Ext. memory write active signal
WE-
O
H
Nand type flash write enable
MRD-
BI
H
Ext. memory read active signal
6
5
4
3
2
128
67
68
NAND
TYPE
FLASH
Or
SMC
Interface
21
Page 18 of 45
Data Sheet
Actions Semiconductor Co.,LTD
ATJ2073
RE
O
H
Nand type flash read enable
MWR-
BI
H
Ext. memory write active signal
WE-
O
H
Nand type flash write enable
MRD-
BI
H
Ext. memory read active signal
RE
O
H
Nand type flash read enable
22
A0
BI
L
Bit0 of ext. memory address bus
23
A1
BI
L
Bit1 of ext. memory address bus
24
A2
BI
L
Bit2 of ext. memory address bus
25
A3
BI
L
Bit3 of ext. memory address bus
26
A4
BI
L
Bit4 of ext. memory address bus
27
A5
BI
L
Bit5 of ext. memory address bus
28
A6
BI
L
Bit6 of ext. memory address bus
29
A7
BI
L
Bit7 of ext. memory address bus
30
A8
BI
L
Bit8 of ext. memory address bus
35
A9
BI
L
Bit9 of ext. memory address bus
36
A10
BI
L
Bit10 of ext. memory address bus
37
A11
BI
L
Bit11 of ext. memory address bus
38
A12
BI
L
Bit12 of ext. memory address bus
39
A13
BI
L
Bit13 of ext. memory address bus
50
A14
O
L
Bit14 of ext. memory address bus
67
A15
O
L
Bit15 of ext. memory address bus
CLE
O
L
Command latch enable of Nand type
flash
A16
O
L
Bit16 of ext. memory address bus
ALE
O
L
Address latch enable of Nand type
flash
69
A17
O
L
Bit17 of ext. memory address bus
70
A18
O
L
Bit18 of ext. memory address bus
71
A19
O
L
Bit19 of ext. memory address bus
/GPO
72
A20
O
L
Bit20 of ext. memory address bus
/GPO
73
A21
O
L
Bit21 of ext. memory address bus
/GPO
74
A22
O
L
Bit22 of ext. memory address bus
/GPO
75
A23
O
L
Bit23 of ext. memory address bus
/GPO
20
21
NOR
TYPE
FLASH
Interface
68
Page 19 of 45
Data Sheet
Actions Semiconductor Co.,LTD
ATJ2073
Crystal
Interface
USB
Interface
Power
Amplifier
Interface
DAC
Output
Interface
ADC
Interface
Page 20 of 45
Data Sheet
76
A24
O
L
Bit24 of ext. memory address bus
/GPO
52
D0
BI
Z
Bit0 of ext. memory data bus
53
D1
BI
Z
Bit1 of ext. memory data bus
54
D2
BI
Z
Bit2 of ext. memory data bus
55
D3
BI
Z
Bit3 of ext. memory data bus
56
D4
BI
Z
Bit4 of ext. memory data bus
57
D5
BI
Z
Bit5 of ext. memory data bus
58
D6
BI
Z
Bit6 of ext. memory data bus
59
D7
BI
Z
Bit7 of ext. memory data bus
64
LOSCI
AI
/
Low frequency crystal OSC input
65
LOSCO
AO
/
Low frequency crystal OSC output
116
HOSCI
AI
/
High frequency crystal OSC input
117
HOSCO
AO
/
High frequency crystal OSC output
78
USBD-
A
/
USB negative connect
79
USBD+
A
/
USB positive connect
80
USBVBUS
I
L
USB cable power signal
81
PVDD
A
/
Bypass capacitor for power amplifier
82
PAOR
A
/
Output of right channel power
amplifier
83
PAOL
A
/
Output of
amplifier
85
PAIR
A
/
Input of
amplifier
right
channel
power
86
PAIL
A
/
Input of
amplifier
left
channel
power
87
AOUTR
A
/
Int. sigma-dalta DAC right channel
analog output
88
AOUTL
A
/
Int. sigma-dalta DAC left channel
analog output
89
VRDA
A
/
Reference voltage for ADC
90
NC
/
/
91
VRAD
A
/
Reference voltage for ADC
92
AGCI
A
/
Microphone ADC amplifier input
93
MICOUT
A
/
Microphone pre-amplifier output
94
MICIN
A
/
Microphone pre-amplifier input
95
VMIC
A
/
Power supply for microphone bias
circuits
left channel power
Actions Semiconductor Co.,LTD
ATJ2073
124
UART
Interface
126
124
IR
Interface
126
SPDIF
Interface
Page 21 of 45
127
Data Sheet
GIOC2
BI
Z
Bit2 of general purpose I/O port C
SIN2
I
Z
UART2 serial input
IRRX
I
Z
IR receive input
GIOC3
BI
Z
Bit3 of general purpose I/O port C
SOUT2
O
Z
UART2 serial output
IRTX
O
Z
IR transmit output
GIOC2
BI
Z
Bit2 of general purpose I/O port C
SIN2
I
Z
UART2 serial input
IRRX
I
Z
IR receive input
GIOC3
BI
Z
Bit3 of general purpose I/O port C
SOUT2
O
Z
UART2 serial output
IRTX
O
Z
IR transmit output
GIOC4
BI
Z
Bit4 of general purpose I/O port C
SPDIFRX
BI
Z
SPDIF receive input
Actions Semiconductor Co.,LTD
ATJ2073
5
Data Sheet
Functional Description
5.1 DSP Core
24-bit Harvard architecture DSP with on-chip ICE support is built in. it works with a memory word length of
24 bits. ATJ2073 has 16KB*24bit Program Memory (PM) and (16KB-256)*24bit Data Memory (DM).
Memory-Mapped Register include DAC interface. Process capability is controlled by software Up to 48
MIPS.
5.2 MCU Core
Integrated 8-bit MCU with on-chip ICE support. Instruction set is compatible with Z80.
Process capability is controlled by software Up to 24.576 MHz.
5.3 System Memory Mapping
MCU 64KB Memory Space Map
0000H
16KB
Internal
Memory
Space
(MCU.A15=0)
16KB
IPMH
16KB
IPMM
16KB
IPML
16KB
IDMH
16KB
IDMM
16KB
IDML
16KB
VRAM
9.6KB
8000H
Entended
Memory
Space
(MCU.A15=1)
FFFFH
32KB
BANK0(32KB)
BANK1(32KB)
BANK2(32KB)
BANK3(32KB)
......
BANK..(32KB)
Page 22 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
Assuming MCU instruction uses A[15:0] to access memory space.
If A[15]=0 -> mapped to internal SRAM ,then
If A[14]=0, mapped to lower 16KB (ZRAM)
If A[14]=1, mapped to upper 16KB (IPMH/IPMM/IPML/IDMH/IDMM/IDML/VRAM) when they are
mapped into MCU memory space. Additional three extended bits of SRAM Page Register (IO index=0x05) are
used to decode which page to access.
Bit 2 1 0
Accessed Page
000
16K of IPM low byte
001
16K of IPM middle byte
010
16K of IPM high byte
011
reserved
100
16K of IDM low byte
101
16K of IDM middle byte
110
16K of IDM high byte
111
on-chip VRAM (Video RAM)
IPM/IDM can map to MCU memory space in 8K unit.
If A[15]=1 -> External address pin A25~A15 are IO mapped at 01h and 02h for EMA15-25. While
EMA26-28 are used to decode CE0- ~ CE6-.
CE0- is used to access boot code from ROM/MASK/NOR-type Flash
CE1- to CE6- can be configured to access ROM, or RAM or NAND-type Flash
5.4 USB1.1 Interface
Compliant with USB SPEC 1.1. Certified by USB IF.
4 endpoints are provided. Support bulk, control, interrupt and isochronous transfer mode . Endpoint 1 and
endpoint 2 employ two independent FIFOs for bulk or isochronous transfers. Endpoint 0 and endpoint 3 have
8 bytes maximum packet size. There are 4 interrupt requests for each endpoint respectively. Generally, this
setting should be satisfying for most practical needs.
5.5 MPEG Decoder
With system software, ATJ2073 is competent for MPEG 1/2/2.5 Layer I/II/III decode.
Sample rates (SR) and bit rates (BR) supported is shown as the following table.
MPEG 2.5
SR\BR
8
16
24
32
40
48
56
64
80
96
112
128
144
160
8
16
24
32
40
48
56
64
80
96
112
128
144
160
8
11.025
12
MPEG 2
SR\BR
Page 23 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
16
22.05
24
MPEG 1
SR\BR
32
40
48
56
64
80
96
112
128
160
192
224
256
320
32
44.1
48
Table 1.
Sample rates and Bit rates of Layer III supported
MPEG 2
SR\BR
8
16
24
32
40
48
56
64
80
96
112
128
144
160
32
48
56
64
80
96
112
128
160
192
224
256
320
384
16
22.05
24
MPEG 1
SR\BR
32
44.1
48
Table 2.
Sample rates and Bit rates of Layer II supported
MPEG 2
SR\BR
32
48
56
64
80
96
112
128
144
160
176
192
224
256
32
64
96
128
160
192
224
256
288
320
352
384
416
448
16
22.05
24
MPEG 1
SR\BR
32
44.1
48
Table 3.
Sample rates and Bit rates of Layer I supported
5.6 Microphone Interface
Microphone interface is composed of microphone pre-amplifier and 16-bit ADC.
Microphone pre-amplifier has 35db gain at least for suitable recording volume so the noise of microphone
power supply must be very low. It is composed of a regulator and an external first order RC LPF. AGC
function is implemented by a variable gain amplifier and 4 register bits (MCU code control).
The ADC adopts switched-capacitor successive approximation method. Its input is from microphone preamplifier’s output. Function enable, sampling frequency select, and some other control signals are all from
Page 24 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
one register.
DC
DB
DA
D9
D6
D5
A
D
C
1.5v
DE_4
MICIN
MICOUT
AVCC AGND
D4_[3:0]
AGCI
5.7 SPDIF Interface
The AES/EBU interface is a means for serially communicating digital audio data through one
single transmission line. It provides two channels for audio data, a method for
communicating control information, and has error detection capabilities. The control
information is transmitted as one bit per sample and accumulates in a block structure. The
data is bi-phase encoded, which enables the receiver to extract a clock from the data .
Coding violations, defined as preambles, are used to identify sample and block boundaries.
2 8-level by 8-bit FIFO are used to buffer data for TX and RX. After received 192 frame- four bytes of
channel status was appended into the RX FIFO. When TX FIFO is empty and SPDIF is enabled, 0 is send out
for all frame.
X Channel A
Y Channel B
Z Channel A
Y Channel B
Sub-frame
Frame 191
X Channel A
Sub-frame
Frame 0
Start of Channel Status Block
Figure 7.1.
1
0
Y Channel B
Frame 1
Frame/Block Format
0
0
1
1
1 0 1 1 0 0 1 1 0 1 0 1
Figure 7.2. Biphase-Mark Encoding
Page 25 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
Figure 7.3. Preamble Forms
Sub-frame
Preamble
3 4
AuxData
7 8
2728293031
MSB
0
LSB
bit
Audio Data
VUC P
Validity
User Data
Channel Status Data
Parity Bit
Figure 7.4.
Sub-frame Format
5.8 Power Management Unit (PMU)
PMU consists of DC-DC converter and regulator and battery monitor.
ATJ2073 need two power trails if work rightly, VDD (Core Power) and VCC (I/O Power). The power level
is decided by external voltage-divided resistance network . Due to describe clearly , we assume VDD=2.35V,
VCC=3.15V.
There are two battery modes with ATJ2073, one-battery mode and two-battery mode, selected by BATSEL.
In one-battery mode, if pin VBAT > 0.8V, some internal circuit (C1) begin to work first and it will rise up
VDD. When VDD reaches 2.35V, that internal circuit (C1) stops and another circuit (C2) takes over the
PFM for both VDD and VCC DC-DC converter.
In two-battery mode, if pin VBAT > 1.3V, the internal regulator is enabled to supply VDD. If 0.8V < VBAT
< 1.3V, C2 will stimulate VDD DC-DC converter to maintain VDD. The judgement between VBAT and
1.3V must have hysteresis for preventing ATJ2073 from unstable toggle between regulator mode and
DC-DC mode. The VCC DC-DC converter always runs to maintain VCC.
Battery monitor compares the battery voltage at the VBAT pin with four reference voltage pins named VL0,
VL1, VL2, VL3. The four reference voltages are decided by external resistance network. For normal dry
battery (1.5V) , the value can be : 1.4V, 1.3V, 1.15V, and 1.05V.
If VBAT < VL3, ATJ2073 will go into STANDBY mode;
If VBAT < 0.8V, ATJ2073 will go into OFF mode, but the low frequency OSC and RTC timer are still
active.
You can disable the clock of block when you do not use that block. Even more you can stop all the clock,
but low frequency OSC, while you design appropriately.
Page 26 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
DCDIS
BATOK
LOSCO
LOSCI
DF_6
BATOK
RTC
...
DCDIS
reset
rstBATOK
DF_7
DF_6
MUX
BATOK
DCDIS
DCDC2
DCF2
DCOP2
DCDC1
DCOP1
DCF1
regulator
VP1
SEL
DCDIS
SEL
BATOK
DF_5
DF_4
VP2
DCDIS
VDD
rst-
DCDISSEL
1.5v
0.8v
VBAT
6
VL0
VL1
VL2
VL3
RESET- DCDIS BATSEL VREFI
Control Interfaces
6.1 How System Power Up
When pin VBAT get to about 0.8V level , DC-DC converter. will begin to rise up VDD and VCC. Low
frequency oscillator will begin to work too. After a duration , POR(Power On Reset) will deassert .
ATJ2073 finishes Power Up sequence . If pin RESET- is not assert, MCU will run from address=0x8000.
Boot code at address=0x8000 will be as the following:
JP 8003h
LD A, 01h
OUT (04h), A
JP Start
……
Start:
Page 27 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
VBAT
VDD
VCC
LOSC
POR
MCU
JP 8003
6.2 Key Matrix Scan
When key scan circuit is enabled, ATJ2073 will scan the keyboard periodly. It drives pin KEYOUTn
[n=0…7] low pulse in turn . When a key is pressed, pin KEYINn connecting the key will be found low
level.
There are 12 internal 8-bit registers for key value latch per scan. But only another one register (Key Scan
Data Register ) for MCU to access key value . Those 12 internal registers are mapped into this register, and
an internal pointer is used to point to the current register to return scan data when read. Any IO write to this
register will clear the internal register, and the pointer will increase by 1 and point to the next register after
read is performed.
Page 28 of 45
Actions Semiconductor Co.,LTD
ATJ2073
KeyIn0
KeyIn1
KeyIn2
KeyIn3
KeyIn4
KeyIn5
KeyIn6
KeyIn7
KeyIn8
KeyIn9
KeyIn10
KeyIn11
Data Sheet
KeyOut0
KeyOut1
KeyOut2
KeyOut3
KeyOut4
KeyOut5
KeyOut6
KeyOut7
1st Reg
2nd Reg
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3
2nd Reg
3rd Reg
b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
4th Reg
5th Reg
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3
5th Reg
6th Reg
b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
7th Reg
8th Reg
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3
8th Reg
9th Reg
b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
10th Reg
11th Reg
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3
11th Reg
12th Reg
b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
Example:
Reg$C0 Readback is $FF,$AF,$F7,$FF,$FF,$FE,$FF,$FF,$FF,$FF,$FF,$FE,
indicate following 5 keys have pressed : [KeyOut ,KeyIn]
[1,0], [1,2], [1,7], [3,4], [7,4]
6.3 4*13 LCD Driver
ATJ2073 builds in 1/3 biased 1/4 duty LCD driver. It outputs COM and SEG signals to LCD glass directly.
Bias voltage pin V1 and V2 need connect by-pass capacitor to ground. V0=GND, V3=VCC.
Page 29 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
V3
V2
COM0
V1
V0
V3
V2
COM1
V1
V0
V3
V2
COM2
V1
V0
V3
V2
COM3
V1
V0
V3
V2
SEGn
V1
V0
ON=V0
OFF=V2
ON=V3
OFF=V1
n
COM0
COM1
COM2
COM3
ON
OFF
2
3 +1+1+1
1+1+1+1
12
2
3 1.732
6.4 8080/6800 LCM Interface
ATJ2073 supports high-speed 8-bit parallel bi-directional LCM with 6800-series or 8080-series interface
Page 30 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
1. LCM with 8080-series interface:
Use A0 to select Data register or Command register in LCM.
CEx- is used as chip select. Pin CS2 of LCM is pull high to VCC.
MWR- is write enable signal, ATJ2073 latches D[7:0] at the rising edge.
MRD- is read enable signal and LCM drives D[7:0] when MRD- is low.
2. LCM with 6800-series interface:
Use A0 to select Data register or Command register in LCM.
LCM_CS- is used as chip select. Pin CS2 of LCM is pull high to VCC.
LCM_RW- is read/write indication signal and high indicates read operation.
LCM_CE- is latch signal. It should latch D[7:0] at the falling edge.
Page 31 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
Pin Configurations
7
ATJ2073 has many Multiple Function Pins (MFP), these pins are multiplexed by several functions.
Pin name will indicate the default function. Other functions can be enabled by system I/O register.
PIN
FUNCTION
Number
Name
GPIO
SEGMENT LCD
17
GIOD0
GIOD0
COM0
LCMD0
16
GIOD1
GIOD1
COM1
LCMD1
15
GIOD2
GIOD2
COM2
LCMD2
14
GIOD3
GIOD3
COM3
LCMD3
13
GIOD4
GIOD4
SEG0
KEYI0
LCMD4
12
GIOD5
GIOD5
SEG1
KEYI1
LCMD5
11
GIOD6
GIOD6
SEG2
KEYI2
LCMD6
10
GIOD7
GIOD7
SEG3
KEYI3
LCMD7
9
GIOE3
GIOE3
SEG7
KEYI7
8
GIOE4
GIOE4
SEG8
KEYI8
7
GIOE5
GIOE5
SEG9
KEYI9
6
GIOE6
GIOE6
SEG10
KEYI10
5
GIOE7
GIOE7
SEG11
KEYI11
4
GIOF0
GIOF0
SEG12
KEYO0
3
GIOF1
GIOF1
SEG13
KEYO1
2
GIOF3
GIOF3
SEG15
KEYO3
128
GIOF4
GIOF4
SEG16
KEYO4
121
FRAME
V2
125
YDU
V1
Enable
Condition
Page 32 of 45
Default:
IO[B0]=0x00,
IO[B1]=0x00
IO[B0]=0x2A,
IO[B1] [7:5]=101
KEY BOARD
IO[B0]=0x3F,
IO[B1][7:6]=11
TCP LCM
IO[B0][5:2]=0101
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
PIN
Number
FUNCTON
Name
NAND FLASH
UART
IrDA
20
MWR-
WE-
21
MRD-
RE
67
A15
CLE
68
A16
ALE
121
FRAME
LCM_CE
123
YSCLK_LP
LCM_RW-
125
YDU
LCM_CS-
124
GIOC2
SIN2
IRRX
126
GIOC3
SOUT2
IRTX
127
GIOC4
Enable
Default
SPDIF
SPDIFRX
IO[28]=0xFE
IO[70].1=1
IO[70].1=1
IO[70].2=1
Condition
Page 33 of 45
Actions Semiconductor Co.,LTD
ATJ2073
8
Data Sheet
Electrical Characteristics
8.1 Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
Input voltage
MIN.
MAX.
Unit
VDD
-0.5
+2.7
V
VCC
-0.5
+3.6
V
VCC >= 3.3
-0.5
+3.9
V
VCC < 3.3
-0.5
VCC+0.6
V
-50
+125
Vi
Storage temperature
Condition
Tstg
Cautions
1. Do not short-circuit two or more output pins simultaneously.
2. If even one of the above parameters exceeds the absolute maximum ratings even
momentarily, the quality of the product may be degraded. The absolute maximum ratings,therefore,
specify the value exceeding which the product may be physically damaged. Use the product well within
these ratings.
The specifications and conditions shown in DC Characteristics and AC characteristics are the ranges for
normal operation and quality assurance of the product.
8.2 Capacitance (TA = 25
, VCC = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Input capacitance
CI
─
15
pF
I/O capacitance
CIO
fc = 1 MHz
Unmeasured pins returned to 0 V
─
15
pF
8.3 DC Characteristics (TA = 25
, VDD = 2.35 V, VCC = 3.15 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX
.
Unit
High-level
output voltage
VOH
IOH = -2 mA
2.4
─
─
V
Low-level
output voltage
VOL
IOL = 2 mA
─
─
0.4
V
High-level input
voltage
VIH
0.6*
VCC
─
VCC
+ 0.6
V
Low-level input
voltage
VIL
-0.3
─
0.4V
CC
V
Input
leakage
current
ILI
VCC = 3.6 V, VI = VCC, 0 V
─
─
±10
uA
Output leakage
current
ILO
VCC = 3.6 V, VI = VCC, 0 V
─
─
±5
uA
GPIO
Idrive1
Gpioc1,Gpioc3,Gpioc5
─
2.60
─
mA
Page 34 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Drive
Idrive2
Supply Current
Two batteries
mode
Data Sheet
Other Gpio
─
1.25
─
mA
In Fullspeed mode (MCU run
24.576MHz
in
internal
SRAM,DSP run 24MIPS)
─
40
─
mA
─
100
─
uA
─
16
─
mA
─
18
─
uA
In Standby mode
Ivdd
In Fullspeed mode (MCU run
24.576MHz
in
internal
SRAM,DSP run 24MIPS)
In Standby mode
Ivcc
Notes 1. IvDD is a total core power supply current for the VDD power supply. IvDD is applied to the LOGIC
and PLL and OSC block.
Ivcc is a total I/O power supply current for the 3.3 V power supply. Ivcc is applied to the USB,
IO, TP, and AD block.
8.4 AC Characteristics (TA = 25
, VDD = 2 to 2.7 V, VCC = 2.7 to 3.6 V)
AC test input waveform
VCC
All input pins
0V
0.6VCC
0.4VCC
Test Points
0.6VCC
0.4VCC
AC test output measuring points
VCC
All output pins
0V
0.5VCC
Test Points
0.5VCC
(1) Reset parameter
Parameter
Symbol
Reset input low-level tWRSL
width
Condition
MIN.
RESET# pin
160
MAX. Unit
ns
tWRSL
VCC
RESET#
0V
(2) Initialization parameter
Parameter
Symbol
Data sampling time
(from RESET# )
tSS
Page 35 of 45
Condition
MIN.
MAX. Unit
61.04
us
Actions Semiconductor Co.,LTD
ATJ2073
Output delay
RESET# )
time
Data Sheet
(from tOD
61.04
us
32.768KHz
RESET#
I/O PINs
tSS tOD
Hi-Z
Normal Operation
Sampling Point
(3) GPIO interface parameter
Parameter
Symbol
Condition
MIN.
MAX. Unit
Input level width
tGPIN
Normal operation
11/
fMCUclk
s
GPIO input rise time tGPRISE
200
ns
GPIO input fall time tGPFALL
200
ns
Output level width
tGPOUT
11/
fMCUclk
ns
Notes 1. fMCUclk is the frequency that MCU is running upon.
(a) Input level width
(b) Input rise/fall time
(c) Output level width
Page 36 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
(4) Ordinary ROM parameter
Parameter
Symbol
Condition
Note
tACC
HOSC=24.576MH 102
z
ns
)Note
tCE
HOSC=24.576MH 82
z
ns
Data input setup time
tDS
HOSC=24.576MH 0
z
ns
Data input hold time
tDH
HOSC=24.576MH 0
z
ns
Data access time (from address)
Data access time (from CEx#
MIN.
MAX. Unit
t ACC
A[24:0]
t CE
CEn-/MRD-
t DS
t DH
D[7:0](I)
(5) External system bus parameter
Parameter
Note 1, 2
Address setup time (to command signal )
Note 1, 2
Address hold time (from command signal )
Note 1
Data output setup time (to command signal )
Data output hold time (from command signal )
Note
Symbol
Condition
MIN. MAX. Unit
tXAS
Memory Read 0.5T
ns
tXAS
Memory Write 1.5T
ns
tXAH
0.5T
ns
tWXDS
0
T
ns
tWXDH
3
0.5T
ns
0
2T
ns
1
Data input setup time (to command signal )Note 1 tRXDS
Note 1
Data input hold time (from command signal )
tRXDH
0
ns
Notes 1. MRD#, MWR# are called the command signals for the External System Bus Interface.
2. T (ns) = 1000 / fMCUCLK
Page 37 of 45
Actions Semiconductor Co.,LTD
ATJ2073
MCUCLK
Data Sheet
2
1
3
t XAS
t XAH
A[24:0]
CEn-
t RXDS
MRD-
t RXDH
D[7:0](I)
MWR-
t XAS
t XAH
D[7:0](O)
t WXDS
t WXDH
Bus Operation
(a) Instruction fetch cycle
MCU CLK
MRD#
CEn#
(b) Memory read cycle
MCU CLK
MRD#
CEn#
(c) Memory write cycle
MCU CLK
MWR#
CEn#
Page 38 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
(6) Keyboard interface parameter
Parameter
Symbol
Condition
MIN. MAX. Unit
KEYOUT (7:0) low-level width
tSCAN
Debounce time=2.5ms
130
us
Voltage stabilization time
tKWAIT Debounce time=2.5ms
(KEYOUT n
KEYOUT (n+1) )
0
us
Key scan interval time
tKI
Debounce time=2.5ms
130
us
Key input delay time (from KEYOUT tKS
n )
Debounce time=2.5ms
0
us
Key input hold time (from KEYOUT tKH
n )
Debounce time=2.5ms
0
us
Remarks
1. KEYOUT(7:0) is multiplexed with GIOF(7:0); KEYIN(3:0) is multiplexed with GIOD(7:4); KEYIN(11:4) is
multiplexed with GIOE(7:0)
2. Keyscan Debouncing time is set thru Bit(2:0) of the MFP Configuration1 Register[0xB1h]
3. n = 0 to 7
(a) Keyboard scan parameter 1
KEYOUTn
tKWAIT
(output)
KEYOUT(n+1)
tSCAN
(output)
Remark n=0 to 6
(b) Keyboard scan parameter 2
KEYOUT0
(output)
KEYOUT1
ss
ss
(output)
KEYOUT7
tKWAIT tKI
ss
(output)
(c) Keyboard port parameter
Page 39 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
KEYOUTn
(output)
tKH
tKS
KEYIN(7:0)
(input)
Remark n=0 to 7
(7) Serial interface parameter
Prescale Value
13
1.625
Baud Rate
Divisor
%Error
600
192
0.16%
-
1200
96
0.16%
1800
64
2000
Divisor
%Error
1
Divisor
%Error
-
-
-
-
-
-
-
0.16%
-
-
-
-
58
0.53%
-
-
-
-
2400
48
0.16%
-
-
-
-
3600
32
0.16%
256
0.16%
-
-
4800
24
0.16%
192
0.16%
-
-
7200
16
0.16%
128
0.16%
208
0.16%
9600
12
0.16%
96
0.16%
156
0.16%
14400
8
0.16%
64
0.16%
104
0.16%
19200
6
0.16%
48
0.16%
78
0.16%
28800
4
0.16%
32
0.16%
52
0.16%
38400
3
0.16%
24
0.16%
39
0.16%
57600
2
0.16%
16
0.16%
26
0.16%
115200
1
0.16%
8
0.16%
13
0.16%
230400
-
-
4
0.16%
-
-
460800
-
-
2
0.16%
-
-
750000
-
-
-
921600
-
-
1
1500000
-
-
-
0.16%
-
2
1
0.00%
0.00%
Note :
Data transfer rate per bit, which is determined by the divisor of the baud-rate generator that is set with UART1/2
Baud Rate Registers and clock prescaler that is set with UART1/2 Control Registers.
Page 40 of 45
Actions Semiconductor Co.,LTD
ATJ2073
9
Data Sheet
Typical Performance Characteristics
9.1 A/D Converter Characteristics
(TA = 25 , VDD = 2.35 V, VCC = 3.3 V, Sample Rate=32KHz)
Parameter
Symbol
Dynamic range
DR
Total Harmonic Distortion + Noise
THD+N
Frequency Response (20-13KHz)
FR
Full Scale Input Voltage(Gain=0dB)
Vifs
Min
Typ.
50
Max
Unit
60
dB
53
dB
±1
800
dB
mVpp
9.2 D/A Converter
I2S interface parameter
Characteristics Table
Parameter
Symbol
Clock Output Frequency
t
SOCLK
Wordstrobe Hold Time t
SOISS
after falling edge of clock
Data Hold Time after t
SOODC
falling edge of clock
Page 41 of 45
Test Conditions
Min. Typ. Max.
48 kHz/s Stereo 16
bit/s
651
Unit
ns
t
10
SOCLK/
ns
2
t
10
SOCLK/
ns
2
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
D/A Converter Characteristics
(TA =25 , VDD=2.35V, VCC=3.3V, Sample Rate=48KHz, Bias Current=8uA, Quantizer
Level=0x05, Volume Level = 0x0D)
Min
Typ
Max
Unit
Parameter
Symbol
Signal / Noise Ratio
SNR
81
dB
Total Harmonic Distortion *
THD+N
0.05
%
Frequency Response 20-20KHz
FR
Output Common Mode Voltage
Vcm
1.5
V
Full Scale Output Voltage
Vofs
0.38
Vrms
Interchannel Isolation
Iso
75
dB
Mmg
0.025
dB
(1KHz)
Interchannel Gain Mismatch(1KHz)
±0.6
dB
* with 32 Ohm load.
9.3 Internal Power Amplifier (2 channels)
Test circuit:
R2
3k
A
B
R1
2.2u
4.7k
PAI
PAO
47u
Output Power:
> 2 x 4mW (32Ohm, use Avdd=2.15V )
> 2 x 10mW (32Ohm, use Avcc=3.00V )
Page 42 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
9.4 MCU/DSP Dissipation (Ivdd VS. Frequency)
MCU Dissipation (Vbat=3.0V,DSP under reset, MCU runs in internal SRAM)
Clock Source
Divisor factor
Ivdd(Max)
32.768KHZ
/(1—1024)
350uA
/1
8.5mA
/2
4.7mA
/4
2.9mA
/8
1.8mA
/16
1.4mA
/32
1.1mA
/64
0.96mA
/128
0.88mA
/256
0.85mA
/512
0.84mA
/1024
0.83mA
24.576MHz
DSP Dissipation (Vbat=3.0V,MCU in Debug mode)
DSP Speed (MIPS)
Ivdd (Max)
6
11.7mA
12
18.8mA
24
30.7mA
36
43.2mA
48
55.9mA
Page 43 of 45
Actions Semiconductor Co.,LTD
ATJ2073
10
Data Sheet
Outline Dimension
Page 44 of 45
Actions Semiconductor Co.,LTD
ATJ2073
Data Sheet
Actions Semiconductor Co., LTD.
15-1,No.1, HIT Road, Tangjia,
Zhuhai, Guangdong, China
519085
Tel. +86-756-3392353
Fax. +86-756-3392251
Http://www.actions.com.cn
All information and data contained in this data sheet is without any commitment, is not to be considered as an
offer for conclusion of a contract nor shall it be construed as to create any liability. Any new issue of this data
sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective
order confirmation form; the same applies to orders based on development samples delivered. By this publication,
Actions Semiconductor Co.,LTD. does not assume responsibility for patent infringements or other rights of third
parties which may result from its use.
Reprinting is generally permitted, indicating the source.
However, our prior consent must be obtained in all cases.
Page 45 of 45
Actions Semiconductor Co.,LTD