ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR GENERAL DESCRIPTION FEATURES The ICS85222 is a Dual LVCMOS / LVTTL-toDifferential LVHSTL Translator and a member of HiPerClockS™ the HiPerClocks™ family of High Performance Clock Solutions from ICS. The ICS85222 has two single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to LVHSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important. For optimum performance, both output pairs need to be terminated, even if one output pair is unused. • 2 differential LVHSTL outputs ICS • Selectable CLK0, CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.3ns (maximum) • VOH: 1.2V (maximum) • 3.3V and 2.5V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT CLK0 Q0 nQ0 CLK1 Q1 nQ1 Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK0 CLK1 GND ICS85222 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View 85222AM www.icst.com/products/hiperclocks.html 1 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Output Type Description 3, 4 Q1, nQ1 Output Differential output pair. LVHSTL interface levels. 5 GND Power Power supply ground. 6 CLK1 Input Pulldown LVCMOS / LVTTL clock input. 7 CLK0 Input Pulldown LVCMOS / LVTTL clock input. Differential output pair. LVHSTL interface levels. Power Positive supply pin. 8 VDD NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated. Refer to Application Information section for a schematic layout. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 85222AM Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3. 3 3.465 V VDD Positive Supply Voltage 2.375 2. 5 2.625 V IDD Power Supply Current 45 mA Maximum Units 2 VDD + 0.3 V -0.3 1.3 V 150 µA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VIH Input High Voltage CLK0, CLK1 VIL Input Low Voltage CLK0, CLK1 IIH Input High Current CLK0, CLK1 VDD = VIN = 3.465V, VDD = VIN = 2.625V IIL Input Low Current CLK0, CLK1 VDD = VIN = 3.465V, VDD = VIN = 2.625V Minimum Typical -5 µA TABLE 3C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Test Conditions VDD = 3.3V ± 5% Peak-to-Peak Output Voltage Swing Minimum Maximum Units 1 Typical 1.2 V 0 0.4 V VDD = 2.5V ± 5% 0 0.55 V VDD = 3.3V ± 5% 0.6 1.2 V VDD = 2.5V ± 5% 0.45 1.2 V NOTE 1: Outputs terminated with 50Ω to GND. 85222AM www.icst.com/products/hiperclocks.html 3 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR Test Conditions Minimum Typical Maximum Units 350 MHz 1150 ps ƒ ≤ 350MHz 750 350 ps Output Rise Time 20% to 80% 150 800 ps tF Output Fall Time 20% to 80% 150 800 ps odc Output Duty Cycle 950 ƒ≤ 150MHz 48 52 % 150 < ƒ ≤ 250MHz 47 53 % 250 < ƒ ≤ 350MHz 45 55 NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 4B. AC CHARACTERISTICS, VDD = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR tF Test Conditions Minimum Typical Maximum Units 350 MHz 1300 ps ƒ ≤ 350MHz 850 450 ps Output Rise Time 20% to 80% 150 800 ps Output Fall Time 20% to 80% 150 800 ps ƒ≤ 150MHz 45 55 % 150 < ƒ ≤ 350MHz 40 60 NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % odc 85222AM Output Duty Cycle www.icst.com/products/hiperclocks.html 4 1075 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR PARAMETER MEASUREMENT INFORMATION 2.5V ± 5% 3.3V ± 5% V DD Qx SCOPE V DD Qx SCOPE LVHSTL LVHSTL nQx nQx GND GND 0V 0V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT PART 1 nQx CLK0, CLK1 VDD Qx 2 PART 2 nQy nQ0, nQ1 Qy Q0, Q1 tPD t sk(pp) PART-TO-PART SKEW PROPAGATION DELAY nQ0, nQ1 80% 80% Q0, Q1 VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% tR tF t PW t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 85222AM www.icst.com/products/hiperclocks.html 5 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR APPLICATION INFORMATION SCHEMATIC EXAMPLE cally located near the power pin. For ICS85222, the unused output need to be terminated. Figure 1 shows a schematic example of ICS85222. In this example, the inputs are driven by 7Ω output LVCMOS drivers with series terminations. The decoupling capacitors should be physi- VDD=3.3V Zo = 50 Ohm - U1 Q1 Ro ~ 7 Ohm Zo = 50 Ohm R5 43 5 6 7 8 nQ1 Q1 nQ0 Q0 GND CLK1 CLK0 VDD 4 3 2 1 Zo = 50 Ohm + R1 50 R2 50 LVHSTL Input ICS85222 Driver_LVCMOS VDD=3.3V VDD=3.3V C1 0.1u Zo = 50 Ohm - Q2 Zo = 50 Ohm Ro ~ 7 Ohm R6 Zo = 50 Ohm + 43 R3 50 R4 LVHSTL Input 50 Driver_LVCMOS FIGURE 1. ICS85222 LVHSTL BUFFER SCHEMATIC EXAMPLE 85222AM www.icst.com/products/hiperclocks.html 6 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85222. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85222 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 45mA = 155.9mW Power (outputs)MAX = 78.9mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 78.9mW = 157.8mW Total Power_MAX (3.465V, with all outputs switching) = 155.9mW + 157.8mW = 313.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.314W * 103.3°C/W = 102.4°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85222AM www.icst.com/products/hiperclocks.html 7 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 2. VDD Q1 VOUT RL 50Ω FIGURE 2. LVHSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V OL_MAX L -V DD_MAX /R ) * (V L DD_MAX ) OH_MAX -V ) OL_MAX Pd_H = (1.2V/50Ω) * (3.465V - 1.2V) = 54.4mW Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 78.9mW 85222AM www.icst.com/products/hiperclocks.html 8 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85222 is: 443 85222AM www.icst.com/products/hiperclocks.html 9 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUM N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 85222AM www.icst.com/products/hiperclocks.html 10 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Package Temperature ICS85222AM 85222AM 8 Lead SOIC tube 0°C to 70°C ICS85222AMT 85222AM 8 Lead SOIC 2500 tape & reel 0°C to 70°C ICS85222AMLF 85222AML 8 Lead "Lead-Free" SOIC tube 0°C to 70°C ICS85222AMLFT 85222AML 8 Lead "Lead-Free" SOIC 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85222AM www.icst.com/products/hiperclocks.html 11 REV. B MARCH 31, 2005 ICS85222 Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TODIFFERENTIAL LVHSTL TRANSLATOR REVISION HISTORY SHEET Rev Table B T2 T8 85222AM Page 1 2 12 Description of Change Features section - add Lead-Free bullet. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Ordering Information Table - added Lead-Free par t number. Updated data sheet format. www.icst.com/products/hiperclocks.html 12 Date 3/31/05 REV. B MARCH 31, 2005