Integrated Circuit Systems, Inc. ICS9341 133MHz Clock Generator and Integrated Buffer for PowerPC™ General Description Features The ICS9341 generates all clocks required for high speed PowerPC RISC microprocessor systems. Generating clocks in phase with an external reference frequency. Generates the following system clocks: - 4-CPUA (3.3V, up to 133MHz) - 4-CPUB (3.3V, up to 133MHz) - 8-PCI (3.3V, 33.3MHz) - 1-OUT (3.3v, 64MHz) - 1-OUT/2 (3.3V, OUT/2MHz) - 2-REF (3.3V, 14.318MHz) Up to 133MHz frequency support. Stop clocks for power management Spread Spectrum for EMI control ±.25% center spread Skew characteristics: - CPU - CPU: <350ps - CPU - PCI: <500ps - PCI - PCI: <500ps Spread Spectrum may be enabled by driving the SS_EN pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9341 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Block Diagram OSC 2 /4 4 REF (0:1) CPUCLKA (1:4) /2 PLL Spread Spectrum CPUB_STOP# OUT_SEL (0:1) PCI_STOP# SS_EN C o n t r o l STOP 4 /3 PLL2 /6 /5 OUT OUT/2 /2 PD# /4 /5 /6 /8 STOP Power Groups: VDDREF, GNDREF = REF, X1, X2 GNDPCI, VDDPCI = PCICLK VDD66, GND66 = 3V66 VDD48, GND48 = 48MHz VDDCOR, GNDCOR = PLL Core VDDLCPU/2 , GNDLCPU/2 = CPU/2 VDDLIOAPIC, GNDIOAPIC = IOAPIC 9341 Rev A 10/12/99 CPUCLKB (1:4) 8 PCICLK (1:8) Pin Configuration GNDREF X1 X2 VDDPCI PCICLK1 PCICLK2 PCICLK3 PCICLK4 GNDPCI GNDCPUB CPUB1 CPUB2 CPUB3 CPUB4 VDDCPUB VDDPCI PCICLK5 PCICLK6 PCICLK7 PCICLK8 FS0 FS1 *OUT_SEL0 GNDPCI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS9341 X1 X2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1 REF0 VDDREF CPUA1 CPUA2 SS_EN GNDCPUA OUT_SEL1* PD# VDDCPUA CPUA3 CPUA4 CPUB_STOP#** VDDD VDDOUT OUT OUT/2 GNDOUT GNDA GNDD N/C N/C *PCI_STOP# VDDA 48-pin SSOP * Internal pull-up resistor of 120K to 3.3V on indicated inputs ** Internal pull-down resistor of 120K to GND on indicated inputs. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9341 Pin Descriptions Pin number 1 2 3 4, 16 5, 6, 7, 8, 17, 18, 19, 20 9, 24 10 11, 12, 13, 14 15 21, 22 Pin name GND REF X1 X2 VDD PCI Type PWR IN O UT PWR D escription Ground pin for REF clocks. XTAL_IN 14.318M Hz crystal input. XTAL_OUT Crystal output. 3.3Volts power pin for PCICLKs. PCICLK (1:8) O UT PCI clock output at 3.3V . Synchronous to CPU clocks. GND PCI GND CPU B CPUB (1:4) VDD CPU B FS (0:1) PWR PWR O UT PWR IN 40 PD# 42 GND CPU A 43 SS_EN 46 VDD REF PWR Ground pin for PCI clocks. Ground pin for CPUB clocks. CPUCLK outputs up to 133.3M Hz. Pow er pin for the CPU bank B CLK s. 3.3V. Logic - input for frequency selection. These control the output functionality of the O UT and O UT/2 pins. Refer to table for details. Gnd pin for PCICLK s. Pow er for analog outputs. This active low input stops PCI clocks. Not connected Digitial ground Analog ground Ground for output pins. Half the O UT frequency. Dependent on OUT_SEL. Refer to table for details. This output frequency is dependent on OU T_SEL. Refer to table for details. Pow er for OUT pins 3.3V . Pow er for digitial outputs. This active low input stops the CPUB clocks at a logic "0" level when input low . CPUCLK outputs up to 133.3M Hz. Pow er pin for the CPU bank A CLKs. 3.3V . This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. Ground pin for CPUB clocks. Spread spectrum is turned on by driving this input high and turned off by driving low. Pow er pin for REF clocks. REF O UT 14.318M Hz reference clock outputs at 3.3V. 23, 41 *O UT_SEL (0:1) 24 25 26 27, 28 29 30 31 GND PCI VDD A *PCI_STOP# N/C GND D GND A GND OUT PWR PWR IN PWR PWR PWR 32 OUT/2 O UT 33 OUT O UT 34 35 VDD OUT VDD D PWR PWR 36 CPUB_STOP#** 45, 44, 38, 37 39 47, 48 CPUA (1:4) VDD CPU A IN IN O UT PWR IN PWR IN 2 ICS9341 Frequency Selection FS1 FS0 CPUA, CPUB (MHz) PCI (MHz) REF (MHz) 1 1 133.3 33.3 14.318 1 0 100 33.3 14.318 0 1 83.3 33.3 14.318 0 0 66.6 33.3 14.318 OUT_SEL1 OUT_SEL0 OUT (MHz) OUT/2 (MHz) 1 1 48 24 1 0 40 20 0 1 64 32 0 0 Stopped Stopped 3 ICS9341 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9341 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 4 ICS9341 CPU_STOP# Timing Diagram CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. Notes: 1. All timing is referenced to the internal CPUCLK. 2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3. PD# and PCI_STOP# are shown in a high state. PCI_STOP# Timing Diagram PCI_STOP# is an input to the clock synthesizer. It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for the PCI outputs to become enabled/disabled. Notes: 1. All timing is referenced to CPUCLK. 2. Internal means inside the chip. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high state. 5 ICS9341 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL Input High Voltage VIH Input Low Voltage Input High Current Input Low Current Input Low Current VIL IIH IIL1 IIL2 Operating Supply Current IDD3.3OP66 IDD3.3OP83 IDD3.3OP100 IDD3.3OP133 Power Down Supply Current Input frequency Input Capacitance1 1 IDD3.3PD Fi CIN CINX TTrans TS TSTAB Transition Time Settling Time1 Clk Stabilization1 Skew1 tCPUA-CPUB Skew1 tCPU-PCI CONDITIONS MIN TYP 2 VSS-0.3 VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Select @ 66MHz; Max discrete cap loads Select @ 83MHz; Max discrete cap loads Select @ 100MHz; Max discrete cap loads Select @ 133MHz; Max discrete cap loads VT = 1.5 V 6 UNITS VDD+0.3 V 0.8 5 0.1 2.0 -100 215 200 180 160 250 225 200 175 V µA µA µA mA mA mA mA 160 300 µA 12 14.318 13.5 18 16 5 22.5 3 -5 -200 PD# = 0 VDD = 3.3 V Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V MAX 100 3 350 MHz pF pF ms ms ms ps 500 800 ps 1 ICS9341 Electrical Characteristics - CPUA TA = 0 - 70º C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2B IOH = -8.0 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH =1.7 V Output Low Current IOL2B VOL = 0.7 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr2B Fall Time tf2B1 VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle dt2B VT = 1.5 V 1 Skew tsk2B VT = 1.5 V Jitter, Cycle-to-cycle tjcyc-cyc2B1 VT = 1.5 V MIN 2 19 40 TYP 2.4 0.32 -37 26 1.5 1 50 125 230 MAX UNITS V 0.4 V -16 mA mA 2.5 ns 2.5 ns 55 % 175 ps 350 ps TYP 2.4 0.32 -37 26 1.9 1.6 49 90 230 MAX UNITS V 0.4 V -16 mA mA 3 ns 3 ns 55 % 175 ps 350 ps 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPUB TA = 0 - 70º C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2B IOH = -8.0 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH =1.7 V Output Low Current IOL2B VOL = 0.7 V 1 Rise Time tr2B VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf2B VOH = 2.4 V, VOL = 0.4 V Duty Cycle dt2B1 VT = 1.5 V 1 Skew tsk2B VT = 1.5 V Jitter, Cycle-to-cycle tjcyc-cyc2B1 VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 7 MIN 2 19 40 ICS9341 Electrical Characteristics - PCI TA = 0 - 70º C; VDD = VDDL = 3.3 V +/-5%; CL =30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, Cycle-to-cycle1 1 MIN 2.4 25 TYP 3.1 0.17 -60 47 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.8 2.5 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.7 2.5 ns dt1 VT = 1.5 V 45 50 55 % tsk1 tjcyc-cyc1 VT = 1.5 V VT = 1.5 V 150 120 500 500 ps ps 16 TYP 2.9 0.33 -30 23 MAX UNITS V 0.4 V -20 mA mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF, OUT, OUT/2 TA = 0 - 70º C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -12 mA Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 10 mA Output High Current IOH5 VOH = 2.0 V VOL = 0.8 V Output Low Current IOL5 1 MIN 2.4 Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V; OUT 1.5 1.8 4 ns Fall Time1 tf5 VOH = 2.4 V, VOL = 0.4 V; OUT 1.5 2 4 ns Duty Cycle1 dt5 VT = 1.5 V; OUT 45 52 55 % Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V; OUT/2 1.5 2.2 4 ns Fall Time1 tf5 VOH = 2.4 V, VOL = 0.4 V; OUT/2 1.5 2.1 4 ns Duty Cycle1 dt5 VT = 1.5 V; OUT/2 45 50 55 % Rise Time1 4 ns tr5 VOL = 0.4 V, VOH = 2.4 V; REF 1.5 2.7 Fall Time1 tf5 VOH = 2.4 V, VOL = 0.4 V; REF 1.5 2.8 4 ns Duty Cycle1 Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1 dt5 VT = 1.5 V; REF VT = 1.5 V; OUT, OUT/2 VT = 1.5 V; REF 45 50 280 450 55 500 1000 % ps ps tjcyc-cyc5 tjcyc-cyc5 Guaranteed by design, not 100% tested in production. 8 ICS9341 SSOP Package SY M B O L A A1 A2 B C D E e H h L N µ X C O M M O N D IM E N S IO N S M IN . NOM. M AX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 S ee Variations .292 .296 .299 0.025 B SC .400 .406 .410 .010 .013 .016 .024 .032 .040 S ee Variations 0° 5° 8° .085 .093 .100 VA R IAT IO N S M IN . .620 AC D NOM. .625 N MAX. .630 48 Ordering Information ICS9341yF Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 9 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.