Integrated Circuit Systems, Inc. ICS9250-09 Frequency Timing Generator for PENTIUM II Systems General Description Features The ICS9250-09 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the ICS9211-01. Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-09 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Generates the following system clocks: - 4 CPU clocks ( 2.5V, 100/133MHz) - 8 PCI clocks, including 1 free-running (3.3V, 33MHz) - 2 CPU/2 clocks (2.5V, 50/66MHz) - 3 IOAPIC clocks (2.5V, 16.67MHz) - 4 Fixed frequency 66MHz clocks(3.3V, 66MHz) - 2 REF clocks(3.3V, 14.318MHz) - 1 USB clock (3.3V, 48MHz) Efficient power management through PD#, CPU_STOP# and PCI_STOP#. 0.5% typical down spread modulation on CPU, PCI, IOAPIC, 3V66 and CPU/2 output clocks. Uses external 14.318MHz crystal. The CPU/2 clocks are inputs to the DRCG. Key Specification CPU Output Jitter: <250ps CPU/2 Output Jitter. <250ps IOAPIC Output Jitter: <500ps 48MHz, 3V66, PCI Output Jitter: <500ps Ref Output Jitter. <1000ps CPU Output Skew: <175ps CPU/2 Output Skew. <175ps IOAPIC Output Skew <250ps PCI Output Skew: <500ps 3V66 Output Skew <250ps CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads) 3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads) CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads) Pin Configuration Block Diagram 56-pin SSOP 9250-09 Rev J 1/21/00 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9250-09 Pin Descriptions Pin number 1 Pin name GNDREF Type PWR Description Gnd pin for REF clocks 2, 3 REF(0:1) OUT 14.318MHz reference clock outputs at 3.3V 4 5 6 7, 13, 19 VDDREF X1 X2 GNDPCI PWR IN OUT PWR Power pin for REF clocks XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output Gnd pin for PCICLKs 8 PCICLK_F OUT Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected by the PCI_STOP# input. 9, 11, 12, 14, 15, PCICLK[1:7] 17, 18 OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks. 10, 16 VDDPCI PWR 3.3Volts power pin for PCICLKs 20, 24 GND66 PWR Gnd pin for 3V66 outputs 21, 22, 25, 26 3V66[0:3] OUT 66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is driven active.. 23, 27 VDD66 PWR 28 SEL 133/100# IN 29 30 31 32, 33 GND48 48MHz VDD48 SEL[0:1] PWR OUT PWR IN 34 SPREAD# IN 35 PD# IN 36 CPU_STOP# IN 37 PCI_STOP# IN 38 39 43, 47 40, 44 GNDCOR VDDCOR VDDLCPU GNDLCPU PWR PWR PWR PWR 41, 42, 45, 46 CPUCLK[0:3] OUT 48 GNDLCPU/2 PWR 49, 50 CPU/2[0:1] OUT 51 52 VDDLCPU/2 GNDLIOAPIC PWR PWR 53, 54, 55 IOAPIC[0:2] OUT 56 VDDLIOAPIC PWR power pin for the 3V66 clocks. This selects the frequency for the CPU and CPU/2 outputs. High = 133MHz, Low=100MHz Ground pin for the 48MHz output Fixed 48MHz clock output. 3.3V Power pin for the 48MHz output. Function select pins. See truth table for details. Enables spread spectrum when active(Low). modulates all the CPU, PCI, IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and 48MHz clocks. 0.5% down spread modulation. This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at logic "0" when driven active(Low). Does not affect the CPU/2 clocks. This asynchronous input halts the PCICLK[1:7] at logic"0" when driven active(Low). PCICLK_F is not affected by this input. Ground pin for the PLL core Power pin for the PLL core. 3.3V Power pin for the CPUCLKs. 2.5V Ground pin for the CPUCLKs Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state of the SEL 133/100MHz. Ground pin for the CPU/2 clocks. 2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on the state of the SEL 133/100# input pin. Power pin for the CPU/2 clocks. 2.5V Ground pin for the IOAPIC outputs. IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at 16.67MHz. Power pin for the IOAPIC outputs. 2.5V. 2 ICS9250-09 Frequency Select: SEL 133/100- SEL1 SEL0 # 0 0 0 0 0 1 CPU MHz CPU/2 MHz 3V66 MHz PCI MHz 48 MHz REF MHz IOAPIC MHz Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z 14.318 16.67 14.318 16.67 0 1 0 100.00 50.00 66.67 33.33 0 1 1 100.00 50.00 66.67 33.33 1 0 0 1 1 1 0 1 1 1 0 1 48 TCLK/TCLK/2 TCLK/4 TCLK/4 TCLK/8 2 N/A N/A N/A N/A N/A 133.32 66.67 66.67 33.33 Hi-Z 133.32 66.67 66.67 33.33 48 TCLK TCLK/16 N/A 14.318 14.318 N/A 16.67 16.67 Comments Tri-state Reserved 48MHz PLL disabled Test mode (1) Reserved Note: 1. TCLK is a test clock driven on the x1 input during test mode. Power Management Features: 3V66 PCI EF. PCI_F 48RM Hz Osc VCOs LOW LOW LOW LOW LOW OFF OFF ON ON LOW LOW ON ON ON ON LOW ON ON LOW ON ON ON ON ON 0 ON ON ON ON LOW ON ON ON ON 1 ON ON ON ON ON ON ON ON ON CPU_STOP# PD# PCI_STOP# CPUCLK CPU/2 IOAPIC X 0 X LOW LOW 0 1 0 LOW 0 1 1 1 1 1 1 Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. 4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW. 5. CPU/2, IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions except PD# = LOW 3 ICS9250-09 Power Management Requirements: Latency Singal CPU_STOP PCI_STOP# PD# Singal State No. of rising edges of PCICLK 0 (disabled) 1 1 (enabled) 1 0 (disabled) 1 1 (enabled) 1 (normal operation) 0 (power down) 1 3mS 2max. Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device. CPU_STOP# Timing Diagram CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for both the CPU and 3V66 outputs to become enabled/disabled. Notes: 1. All timing is referenced to the internal CPUCLK. 2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3. CPU_STOP# signal is an input singal that must be made synchronous to free running PCICLK_F 4. 3V66 clocks also stop/start before 5. PD# and PCI_STOP# are shown in a high state. 6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz 4 ICS9250-09 PCI_STOP# Timing Diagram PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for the PCI outputs to become enabled/disabled. Notes: 1. All timing is referenced to CPUCLK. 2. PCI_STOP# signal is an input signal which must be made synchronous to PCICLK_F output. 3. Internal means inside the chip. 4. All other clocks continue to run undisturbed. 5. PD# and CPU_STOP# are shown in a high state. 6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 5 ICS9250-09 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9250 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 6 ICS9250-09 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. G roup O ffset Group CPU to 3V66 3 V66 to PCI CPU to IOAPIC Offset 0.0-1 .5 ns CPU leads 1.5-4.0n s 3 V66 leads 1.5-4 .0 ns CPU leads Measurem ent Loads CPU @ 20pF, 3V66 @ 30p F 3V66 @ 3 0pF, PCI @ 30pF C PU @ 20p F, IOAPIC @ 2 0pF Measure Po ints C PU @ 1.25V, 3V66 @ 1.5V 3V66 @ 1.5V, PC I @ 1.5V CPU @ 1.25V, IOAPIC @ 1.5V No te: 1 . All o ffs ets are to b e measu red at risin g ed g es . Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency IDD3.3P D CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Select @ 100MHz; Max discrete cap loads Select @ 133MHz; Max discrete cap loads MIN 2 VSS-0.3 TYP 0.1 2.0 -100 68 80 -5 -200 VDD = 3.3 V Logic Inputs X1 & X2 pins Transition Time1 TTrans To 1st crossing of target Freq. Settling Time1 Clk Stabilization 1 TS TStab From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 180 mA 62 200 uA 12 14.318 27 36 16 5 45 MHz pF pF CL = 0 pF; PWRDWN# = 0 Fi C IN C INX Input Capacitance1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP100 IDD3.3OP133 3 1 ms ms 3 ms Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current 1 SYMBOL CONDITIONS IDD2.5OP 66 Select @ 100MHz; Max discrete cap loads IDD2.5OP 100 Select @ 133MHz; Max discrete cap loads Guaranteed by design, not 100% tested in production. 7 MIN TYP 19 22 MAX 25 40 UNITS mA ICS9250-09 Electrical Characteristics - CPUCLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2B VOL2B IOH2B IOL2B 19 TYP 2.2 0.3 -35 27 Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.2 1.6 ns Fall Time tf2B 1 VOH = 2.0 V, VOL = 0.4 V 0.4 1.25 1.6 ns Duty Cycle VT = 1.25 V 45 48 55 % VT = 1.25 V 80 175 ps VT = 1.25 V 20 150 ps Jitter, Absolute d t2B1 tsk2B1 tj1 σ2B1 tjabs2B1 61 +250 ps Jitter, Cycle-to-cycle tjcyc-cyc2B1 150 250 ps Skew Jitter, One Sigma 1 CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VT = 1.25 V VT = 1.25 V MIN 2 -250 MAX UNITS V 0.4 V -19 mA mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU/2 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2B VOL2B IOH2B IOL2B Rise Time tr2B 1 Fall Time tf2B1 Duty Cycle Jitter, Absolute d t2B1 tj1 σ2B1 tjabs2B1 Jitter, Cycle-to-cycle tjcyc-cyc2B1 Jitter, One Sigma 1 CONDITIONS 19 TYP 2.3 0.3 -35 27 VOL = 0.4 V, VOH = 2.0 V 0.4 1.1 1.6 ns VOH = 2.0 V, VOL = 0.4 V 0.4 1 1.6 ns VT = 1.25 V 45 48 55 % 20 150 ps 70 +250 ps 100 250 ps IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V MIN 2 VT = 1.25 V VT = 1.25 V VT = 1.25 V -250 Guaranteed by design, not 100% tested in production. 8 MAX UNITS V 0.4 V -19 mA mA ICS9250-09 Electrical Characteristics - 3V66 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, One Sigma 1 1 Jitter, Absolute Jitter, Cycle-to-cycle1 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 25 TYP 3.1 0.25 -60 44 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.6 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.3 2 ns d t1 VT = 1.5 V 45 48 55 % tsk1 VT = 1.5 V 120 175 ps tj1 σ1 VT = 1.5 V 43 150 ps tjabs1 VT = 1.5 V VT = 1.5 V 100 250 ps 150 500 ps tjcyc-cyc1 -250 Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, One Sigma 1 1 Jitter, Absolute Jitter, Cycle-to-cycle1 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 25 TYP 3.1 0.2 -60 45 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.7 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.6 2 ns d t1 VT = 1.5 V 45 50 55 % tsk1 VT = 1.5 V 360 500 ps tj1 σ1 VT = 1.5 V 18 150 ps tjabs1 tjcyc-cyc1 VT = 1.5 V VT = 1.5 V 80 250 ps 155 500 ps -250 Guaranteed by design, not 100% tested in production. 9 ICS9250-09 Electrical Characteristics - 48MHz, REF TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle Rise Time Fall Time 1 1 1 Duty Cycle 1 1 Jitter, Cycle-to-cycle Jitter, Cycle-to-cycle1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 17 TYP 2.9 0.3 -35 23 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V, 48MHz 2 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V, 48MHz 2 4 ns d t5 VT = 1.5 V, 48MHz 50 55 % tr5 VOL = 0.4 V, VOH = 2.4 V, REF 2.2 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V, REF 1.9 4 ns d t5 VT = 1.5 V, REF 52 55 % 200 500 ps 800 1000 ps 19 TYP 2.23 0.3 -36 26 MAX UNITS V 0.4 V -16 mA mA tjcyc-cyc5 tjcyc-cyc5 45 45 VT = 1.5 V, 48MHz VT = 1.5 V, REF Guaranteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma 1 1 Jitter, Absolute Jitter, Cycle-to-cycle1 1 SYMBOL VOH4B VOL4B IOH4B IOL4B CONDITIONS IOH = -12 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V MIN 2 Tr4B VOL = 0.4 V, VOH = 2.0 V 0.4 1.3 1.6 ns Tf4B VOH = 2.0 V, VOL = 0.4 V 0.4 1.25 1.6 ns Dt4B VT = 1.25 V 45 49 55 % Tj1 σ4B VT = 1.25 V 14 150 ps Tjabs4B VT = 1.25 V VT = 1.25 V 65 250 ps 87 500 ps tjcyc-cyc4B -250 Guaranteed by design, not 100% tested in production. 10 ICS9250-09 General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. Ferrite Bead VDD 2) Make all power traces and ground traces as wide as the via pad for lower inductance. C1 Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed. C1 2 3.3V Power Route Connections to VDD: C2 22µF/20V Tantalum C2 22µF/20V Tantalum 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 Ferrite Bead VDD 2.5V Power Route 1 C3 Clock Load 3.3V Power Route = Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load 11 ICS9250-09 Pin 1 Index Area .093 DIA. PIN (Optional) D/2 E/2 PARTING LINE H L DETAIL “A” TOP VIEW BOTTOM VIEW -e- A2 c SEE DETAIL “A” A .004 C -E- A A1 A2 B c D E e H h L N µ SEATING PLANE -DEND VIEW SYMBOL B COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .010 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0° 8° SIDE VIEW VARIATIONS MIN. .720 AD -C- A1 D NOM. .725 N MAX. .730 56 “For current dimensional specifications, see JEDEC 95.” Dimensions in inches 56 Pin 300 mil SSOP Package Ordering Information ICS9250yF-09-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 12 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.