ICS932S200 Integrated Circuit Systems, Inc. Frequency Timing Generator for Dual Server/Workstation Systems General Description Features The ICS932S200 is a dual CPU clock generator for serverworks HE-T, HE-SL-T, LE-T chipsets for P III type processors in a Dual-CPU system. Single ended CPU clocks provide faster than 1.5V/ns transition times by parallel connection of 2 CPU pins to each processor. • CPU Output Jitter: 150ps IOAPIC Output Jitter: 250ps 3V66, PCI Output Jitter: 250ps CPU Output Skew: <175ps PCI Output Skew: <500ps 3V66 Output Skew <250ps IOAPIC Output Skew <250ps CPU to 3V66 Output Offset: 0 - 1.5ns (CPU leads) CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads) CPU to APIC Output Offset: 1.5 - 4.0ns (CPU leads) Block Diagram PLL2 X1 X2 PD# PCI_STOP# CPU_STOP# SPREAD# SEL 133/100# SEL0 SEL1 0427C—07/03/02 48MHz XTAL OSC PLL1 Spread Spectrum • • Key Specification: • • • • • • • • • • • 2 CPU DIVDER 6 IOAPIC DIVDER 3 REF (1:0) CPUCLK (5:0) IOAPIC (2:0) Pin Configuration GND REF0 REF1 VDD X1 X2 GND GND PCICLK_F VDD PCICLK0 PCICLK1 GND PCICLK2 PCICLK3 VDD VDD PCICLK4 GND GND GND VDD VDD GND 3V66_0 3V66_1 VDD SEL 133/100# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS932S200 Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS932S200 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Generates the following system clocks: - 6 CPU clocks ( 2.5V, 100/133MHz) - 6 PCI clocks, including 1 free running(3.3V, 33MHz) - 3 IOAPIC clocks (2.5V, 16.67MHz) - 2 Fixed frequency 66MHz clocks(3.3V, 66MHz) - 2 REF clocks(3.3V, 14.318MHz) - 1 USB clock (3.3V, 48MHz) Efficient power management through PD#, CPU_STOP# and PCI_STOP#. 0.5% typical down spread modulation on CPU, PCI, IOAPIC and 3V66 output clocks. Uses external 14.318MHz crystal. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDL IOAPIC2 IOAPIC1 IOAPIC0 GND VDDL CPUCLK5 CPUCLK4 GND VDDL CPUCLK3 CPUCLK2 GND VDDL CPUCLK1 CPUCLK0 GND VDD GND PCI_STOP# CPU_STOP# PD# SPREAD# SEL1 SEL0 VDD 48MHz GND Control Logic PCI DIVDER Stop 5 PCICLK (4:0) PCICLK_F Config. Reg. 3V66 DIVDER 2 3V66 (1:0) 56-pin 300 mil SSOP 56-pin 240 mil TSSOP ICS932S200 Pin Descriptions Pin number 1, 7, 8, 13, 19 20, 21, 24, 29, 38, 40, 44, 48, 52 3, 2 Pin name Type Description GND PWR Gnd pins REF(1:0) OUT 14.318MHz reference clock outputs at 3.3V VDD PWR Power pins 3.3V X1 X2 PCICLK_F IN OUT OUT XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output Free running PCI clock not affected by PCI_STOP# PCICLK (4:0) OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks. 3V66 (1:0) OUT 66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is driven active.. SEL 133/100# IN 30 33, 32 48MHz SEL (1:0) OUT IN 34 SPREAD# IN 35 PD# IN 36 CPU_STOP# IN 37 PCI_STOP# IN VDDL PWR CPUCLK (5:0) OUT IOAPIC (2:0) OUT 4,. 10, 16, 17, 22, 23, 27, 31, 39 5 6 9 18, 15, 14, 12, 11 26, 25 28 43, 47, 51, 56 50, 49, 46, 45, 42, 41 55, 54, 53 This selects the frequency for the CPU and CPU/2 outputs. High = 133MHz, Low=100MHz Fixed 48MHz clock output. 3.3V Function select pins. See truth table for details. Enables spread spectrum when active(Low). modulates all the CPU, PCI, IOAPIC and 3V66 clocks. Does not affect the REF and 48MHz clocks. 0.5% down spread modulation. This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. This asychronous input halts the CPUCLK and the 3V66 clocks at logic "0" when driven active(Low). This asynchronous input halts the PCICLK at logic"0" when driven active(Low). PCICLK_F is not affected by this input. Power pins 2.5V Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state of the SEL 133/100MHz. IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at 16.67MHz. 0427C—07/03/02 2 ICS932S200 Frequency Select: SEL SEL1 SEL0 133/100# 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 CPU MHz Hi-Z N/A 3V66 MHz Hi-Z N/A PCI MHz Hi-Z N/A 48 MHz Hi-Z N/A REF MHz Hi-Z N/A IOAPIC MHz Hi-Z N/A 100 66.6 33.3 Hi-Z 14.318 16.67 100 66.6 33.3 48.0 TCLK/2 TCLK/4 TCLK/8 TCLK/2 N/A N/A N/A N/A 133 66.6 33.3 Hi-Z 133 66.6 33.3 48.0 14.318 16.67 TCLK TCLK/16 N/A N/A 14.318 16.67 14.318 16.67 Comments Tri-state Reserved 48MHz PLL disabled Test mode (1) Reserved Note: 1. TCLK is a test clock driven on the x1 input during test mode. ICS932S200 Power Management Features: 3V66 PCI PCI_F REF. 48MHz Osc VCOs LOW LOW LOW LOW LOW OFF OFF LOW ON LOW LOW ON ON ON ON 1 LOW ON LOW ON ON ON ON ON 1 0 ON ON ON LOW ON ON ON ON 1 1 ON ON ON ON ON ON ON ON CPU_STOP# PD# PCI_STOP# CPUCLK IOAPIC X 0 X LOW 0 1 0 0 1 1 1 Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. 4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW. 5. IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions except PD# = LOW 0427C—07/03/02 3 ICS932S200 Power Management Requirements: Latency Singal CPU_STOP PCI_STOP# Singal State No. of rising edges of PCICLK 0 (disabled) 1 0 (disabled) 1 1 (enabled) 1 (normal operation) PD# 1 1 (enabled) 0 (power down) 1 3mS 2max. Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device. CPU_STOP# Timing Diagram CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. CPUCLK (internal) PCICLK (internal) CPU_STOP# PCI_STOP# PD# CPUCLK (externall) 3V66 (externall) Notes: 1. All timing is referenced to the internal CPUCLK. 2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3. 3V66 clocks also stop/start before 4. PD# and PCI_STOP# are shown in a high state. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz 0427C—07/03/02 4 ICS932S200 PCI_STOP# Timing Diagram PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for the PCI outputs to become enabled/disabled. CPUCLK (internal) PCICLK (internal) CPU_STOP# PCI_STOP# PD# PCICLK (externall) Notes: 1. All timing is referenced to CPUCLK. 2. Internal means inside the chip. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high state. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 0427C—07/03/02 5 ICS932S200 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# CPUCLK 3V66 PCICLK VCO Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS932S200 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 0427C—07/03/02 6 ICS932S200 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time 1 Settling Time1 Clk Stabilization1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP100 IDD3.3OP133 IDD3.3PD Fi CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Select @ 100MHz; Max discrete cap loads Select @ 133MHz; Max discrete cap loads CL =30 pF; PWRDWN# = 0 VDD = 3.3 V MIN 2 VSS-0.3 -5 -200 12 CIN CINX Logic Inputs X1 & X2 pins TTrans To 1st crossing of target Freq. TS TStab From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. 27 TYP 0.1 2.0 -100 70 80 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 160 mA 102 200 uA 14.32 16 MHz 36 5 45 pF pF 3 ms 1 ms 3 Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current 1 SYMBOL CONDITIONS MIN IDD2.5OP100 Select @ 100MHz; Max discrete cap loads IDD2.5OP133 Select @ 133MHz; Max discrete cap loads Guaranteed by design, not 100% tested in production. 0427C—07/03/02 7 TYP 38 MAX 75 69 90 UNITS mA ms ICS932S200 Electrical Characteristics - CPUCLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP IOH = -12.0 mA 2 2.2 Output High Voltage VOH2B IOL = 12 mA 0.3 Output Low Voltage VOL2B VOH = 1.7 V -35 Output High Current IOH2B VOL = 0.7 V 19 27 Output Low Current IOL2B MAX UNITS V 0.4 V -19 mA mA Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 0.4 0.84 1.6 ns Fall Time VOH = 2.0 V, VOL = 0.4 V 0.4 0.81 1.6 ns VT = 1.25 V 45 50.7 55 % Skew tf2B1 d t2B1 tsk2B1 93 175 ps Jitter, Cycle-to-cycle tjcyc-cyc2B1 108 150 ps Duty Cycle 1 VT = 1.25 V VT = 1.25 V Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA TYP 3.1 MAX UNITS V Output Low Voltage VOL1 IOL = 9.4 mA 0.25 0.4 V Output High Current IOH1 VOH = 2.0 V -60 -22 mA Output Low Current IOL1 VOL = 0.8 V 25 44 tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.44 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.24 2 ns dt1 VT = 1.5 V 45 48.2 55 % tsk1 VT = 1.5 V 83 250 ps tjcyc-cyc1 VT = 1.5 V 110 250 ps Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, Cycle-to-cycle 1 MIN 2.4 1 Guaranteed by design, not 100% tested in production. 0427C—07/03/02 8 mA ICS932S200 Electrical Characteristics - PCICLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IOH = -11 mA 2.4 3.1 V Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA 0.2 0.4 V Output High Current IOH1 VOH = 2.0 V -60 -22 mA Output Low Current IOL1 VOL = 0.8 V 25 45 tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.2 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.1 2 ns dt1 VT = 1.5 V 45 50.8 55 % tsk1 VT = 1.5 V 79 500 ps tj1σ1 VT = 1.5 V 150 ps tjabs1 VT = 1.5 V 250 ps tjcyc-cyc1 VT = 1.5 V 250 ps Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew 1 Jitter, One Sigma Jitter, Absolute 1 Jitter, Cycle-to-cycle 1 1 -250 129 mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Output High Voltage VOH4B IOH = -12 mA 2 2.23 Output Low Voltage VOL4B IOL = 12 mA 0.3 0.4 V Output High Current IOH4B VOH = 1.7 V -36 -16 mA Output Low Current IOL4B VOL = 0.7 V 19 26 Tr4B VOL = 0.4 V, VOH = 2.0 V 0.4 1.35 1.6 ns Tf4B VOH = 2.0 V, VOL = 0.4 V 0.4 1.01 1.6 ns Dt4B VT = 1.25 V 45 50.3 55 % tsk4B1 VT = 1.25 V VT = 1.25 V 63 250 ps 80 250 ps Rise Time Fall Time 1 1 Duty Cycle 1 Skew Jitter, Cycle-to-cycle1 1 MAX UNITS V tjcyc-cyc4B Guaranteed by design, not 100% tested in production. 0427C—07/03/02 9 mA ICS932S200 Electrical Characteristics - 48MHz, REF TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP IOH = -12 mA 2.6 2.9 Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 9 mA 0.3 0.4 V Output High Current IOH5 VOH = 2.0 V -35 -22 mA Output Low Current IOL5 VOL = 0.8 V tr5 VOL = 0.4 V, VOH = 2.4 V, 48MHz 1.9 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V, 48MHz 2 4 ns dt5 VT = 1.5 V, 48MHz 50.2 55 % tr5 VOL = 0.4 V, VOH = 2.4 V, REF 0.7 N/A ns tf5 VOH = 2.4 V, VOL = 0.4 V, REF 0.5 N/A ns dt5 VT = 1.5 V, REF 52 N/A % 239 500 ps 413 1000 ps Rise Time Fall Time 1 1 Duty Cycle Rise Time Fall Time 1 1 1 Duty Cycle 1 1 Jitter, Cycle-to-cycle Jitter, Cycle-to-cycle1 1 MAX UNITS V tjcyc-cyc5 tjcyc-cyc5 17 45 45 VT = 1.5 V, 48MHz VT = 1.5 V, REF Guaranteed by design, not 100% tested in production. 0427C—07/03/02 10 23 mA ICS932S200 c N SYMBOL L E1 E INDEX AREA 1 2 α h x 45° D In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 2.413 2.794 .095 .110 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS .005 .010 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e A h 0.381 L 0.508 1.016 SEE VARIATIONS N α A1 0.635 BASIC 0.635 0° 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 8° 0° 8° MIN MAX MIN MAX 18.288 18.542 .720 .730 JEDEC MO-118 DOC# 10-0034 6/1/00 REV B -C- VARIATIONS e SEATING PLANE b N .10 (.004) C 56 D mm. D (inch) 300 mil SSOP Ordering Information ICS932S200yF-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0427C—07/03/02 11 ICS932S200 c N L E1 INDEX AREA E 1 2 D A A2 A1 -Ce b SEATING PLANE In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N α 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS N aaa C 56 D mm. MIN 13.90 D (inch) MAX 14.10 MIN .547 Reference Doc.: JEDEC Publication 95, MO-153 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) 10-0039 Ordering Information ICS932S200yG-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0427C—07/03/02 12 MAX .555